Hitachi HD74AC195 4-bit parallel-access shift register Datasheet

HD74AC195
4-bit Parallel-Access Shift Register
Description
This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a
direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q 0 towards
Q3.
Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is
loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input.
During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the PE
input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to
perform as a J-K or toggle flip-flop as shown in the function table.
Features
•
•
•
•
•
Shift Right and Parallel Load Capability
J-K (D-Type) Inputs to First Stage
Complement Output from Last Stage
Asynchronous Master Reset
Outputs Source/Sink 24 mA
HD74AC195
Pin Arrangement
MR 1
16 VCC
J 2
15 Q0
K 3
14 Q1
D0 4
13 Q2
D1 5
12 Q3
D2 6
11 Q3
D3 7
10 CP
GND 8
9 PE
(Top view)
Logic Symbol
PE
D0
D1
D2
D3
J
Q3
CP
K
MR
Q0
Q1
Q2
Pin Names
CP
D0 to D3
PE
MR
J, K
Q0 to Q3, Q3
2
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input
Asynchronous Master Reset
J-K or D Type Serial Inputs
Outputs
Q3
HD74AC195
Timing Diagram
CP
MR
J
K
PE
H
D0
L
D1
H
D2
L
D3
Q0
Q1
Q2
Q3
Serial Shift
Serial Shift
Clear
Load
Mode Select-Function Table
Inputs
Outputs
Operating Modes
MR
CP
PE
J
K
Dn
Q0
Q1
Q2
Q3
Q3
Asynchronous Reset
L
X
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
H
H
H
H
X
H
q0
q1
q2
q2
Shift, Reset First Stage
H
H
L
L
X
L
q0
q1
q2
q2
Shift, Toggle First Stage
H
H
H
L
X
q0
q0
q1
q2
q2
Shift, Retain First Stage
H
H
L
H
X
q0
q0
q1
q2
q2
Parallel Load
H
L
X
X
dn
d0
d1
d2
d3
d3
H :
HIGH Voltage Level
L :
LOW Voltage Level
X :
Immaterial
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-toHIGH transition.
:
LOW-to-HIGH clock transition.
3
HD74AC195
Logic Diagram
K
D3
D2
D1
VCC
J
D0
VCC
PE
CP
MR
Q3
Q3
Q2
Q1
Q0
DC Characteristics (unless otherwise specified)
Item
Symbol
Max
Unit
Condition
Maximum quiescent supply current
I CC
80
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = Worst case
Maximum quiescent supply current
I CC
8.0
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = 25°C
4
HD74AC195
AC Characteristics: HD74AC195
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Symbol
VCC (V)*1
Min
Typ
Max
Min
Max
Unit
Maximum clock
f max
3.3
75
—
—
65
—
MHz
5.0
100
—
—
85
—
3.3
1.0
9.0
13.0
1.0
15.0
5.0
1.0
5.5
10.0
1.0
11.5
3.3
1.0
9.0
13.0
1.0
15.0
5.0
1.0
6.5
10.0
1.0
11.5
3.3
1.0
7.5
10.5
1.0
12.0
5.0
1.0
5.5
8.0
1.0
9.5
3.3
1.0
6.0
9.0
1.0
10.5
5.0
1.0
5.0
7.0
1.0
8.0
frequency
Propagation delay
t PLH
CP to Qn or Q3
Propagation delay
t PHL
CP to Qn or Q2
Propagation delay
t PLH
MR to Q2
Propagaion delay
t PHL
MR to Qn
Note:
ns
ns
ns
ns
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74AC195
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol
VCC (V)*1 Typ
Guaranteed Minimum
Unit
Setup time, HIGH or LOW
t su
3.3
3.0
5.5
7.0
ns
5.0
2.0
4.0
5.0
3.3
–0.5
2.0
3.6
5.0
0.5
1.5
2.0
3.3
3.5
5.0
7.0
5.0
2.5
4.0
5.0
3.3
–2.0
0.0
0.0
5.0
–1.5
0.0
0.0
3.3
–1.5
0.5
0.5
5.0
–1.0
0.5
0.5
3.3
–3.0
5.5
7.0
5.0
–3.0
4.5
5.0
J, K or Dn to CP
Hold time, HIGH or LOW
th
J, K or Dn to CP
Setup time, HIGH or LOW
t su
PE to CP
Hold time, HIGH or LOW
th
PE to CP
Recovery time
t rec
MR to CP
Pulse width
Note:
tw
ns
ns
ns
ns
ns
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
5
HD74AC195
Capacitance
Item
Symbol
Typ
Unit
Condition
Input capacitance
CIN
4.5
pF
VCC = 5.5 V
Power dissipation capacitance
CPD
125
pF
VCC = 5.0 V
6
Unit: mm
19.20
20.00 Max
1
7.40 Max
9
6.30
16
8
1.3
0.48 ± 0.10
2.54 Min 5.06 Max
2.54 ± 0.25
0.51 Min
1.11 Max
7.62
+ 0.13
0.25 – 0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-16
Conforms
Conforms
1.07 g
Unit: mm
10.06
10.5 Max
9
1
8
1.27
*0.42 ± 0.08
0.40 ± 0.06
0.10 ± 0.10
0.80 Max
*0.22 ± 0.05
0.20 ± 0.04
2.20 Max
5.5
16
0.20
7.80 +– 0.30
1.15
0° – 8°
0.70 ± 0.20
0.15
0.12 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DA
—
Conforms
0.24 g
Unit: mm
9.9
10.3 Max
9
1
8
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
0.15
*0.22 ± 0.03
0.20 ± 0.03
1.27
0.11
0.14 +– 0.04
1.75 Max
3.95
16
0.10
6.10 +– 0.30
1.08
0° – 8°
0.67
0.60 +– 0.20
0.25 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DN
Conforms
Conforms
0.15 g
Unit: mm
4.40
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
1.10 Max
0.65 Max
0.10
*Dimension including the plating thickness
Base material dimension
6.40 ± 0.20
0.07 +0.03
–0.04
0.20 ± 0.06
1.0
*0.17 ± 0.05
0.15 ± 0.04
0.08
*0.22 +– 0.07
0° – 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-16DA
—
—
0.05 g
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