ONSEMI NCV4269D2

NCV4269
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
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The NCV4269 is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 240 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of an
external resistor divider to the RADJ lead. The regulator is protected
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
Features
•
•
•
•
•
•
•
•
•
•
•
•
5.0 V ± 2.0% Output
Low 240 mA Quiescent Current
Active Reset Output Low Down to VQ = 1.0 V
Adjustable Reset Threshold
150 mA Output Current Capability
Fault Protection
♦ +45 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
Early Warning through SI/SO Leads
Internally Fused Leads in SO−14 and SO−20L Packages
Integrated Pullup Resistor at Logic Outputs (To Use External
Resistors, Select the NCV4279)
Very Low Dropout Voltage
Electrical Parameters Guaranteed Over Entire Temperature Range
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
 Semiconductor Components Industries, LLC, 2004
November, 2004 − Rev. 5
1
MARKING DIAGRAMS
8
8
4269
ALYW
1
SO−8
D SUFFIX
CASE 751
1
14
14
NCV4269
AWLYWW
1
1
SO−14
D SUFFIX
CASE 751A
20
20
NCV4269
AWLYYWW
1
SO−20L
DW SUFFIX
CASE 751D
A
WL, L
YY, Y
WW, W
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
NCV4269/D
NCV4269
I
Q
Error
Amplifier
Current and
Saturation
Control
Reference
and Trim
RSO
RRO
RO
D
or
Reference
SO
RADJ
+
SI
−
GND
Figure 1. Block Diagram
PIN CONNECTIONS
I
1
8
SI
RADJ
D
GND
GND
GND
GND
RO
Q
SO
RO
RADJ
D
GND
SO−8
1
14
RADJ
D
NC
GND
GND
GND
GND
NC
NC
RO
SI
I
GND
GND
GND
Q
SO
SO−14
1
20
SI
I
NC
GND
GND
GND
GND
NC
Q
SO
SO−20L
PACKAGE PIN DESCRIPTION
Package Pin Number
SO−8
SO−14
SO−20L
Pin Symbol
3
1
1
RADJ
4
2
2
D
5
3, 4, 5, 6,
10, 11, 12
4, 5, 6, 7, 14,
15, 16, 17
GND
−
−
3, 8, 9, 13, 18
NC
No connection to these pins from the IC.
6
7
10
RO
Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor to
Q. Leave Open if Not Used.
7
8
11
SO
Sense Output; This Open−Collector Output is Internally Pulled Up by
20 kW pullup resistor to Q. If not used, keep open.
8
9
12
Q
5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.
1
13
19
I
Input; Connect to GND Directly at the IC with a Ceramic Capacitor.
2
14
20
SI
Function
Reset Threshold Adjust; if not used to connect to GND.
Reset Delay; To Set Time Delay, Connect to GND with Capacitor
Ground
Sense Input; If not used, Connect to Q.
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2
NCV4269
MAXIMUM RATINGS (TJ = −40°C to 150°C)
Parameter
Symbol
Min
Max
Unit
Input to Regulator
VI
II
−40
Internally Limited
45
Internally Limited
V
Sense Input
VSI
ISI
−40
−1
45
1
V
mA
VRADJ
IRADJ
−0.3
−10
7
10
V
mA
Reset Delay
VD
ID
−0.3
Internally Limited
7
Internally Limited
V
Ground
Iq
50
−
mA
Reset Output
VRO
IRO
−0.3
Internally Limited
7
Internally Limited
V
Sense Output
VSO
ISO
−0.3
Internally Limited
7
Internally Limited
V
Regulated Output
VQ
IQ
−0.5
−10
7.0
−
V
mA
TJ
TSTG
−
−50
150
150
°C
°C
VI
TJ
−
−40
45
150
V
°C
Reset Threshold Adjust
Junction Temperature
Storage Temperature
Input Voltage Operating Range
Junction Temperature Operating Range
Junction−to−Ambient Thermal Resistance
SO−8
SO−14
SO−20L
RqJA
−
200
70
70
k/W
Junction−to−Pin 4, all GND Pins Grounded.
SO−14
SO−20L
RqJP
−
30
30
k/W
Lead Temperature Soldering and MSL
Symbol
Value
MSL, 20−Lead LS Temperature 260°C Peak (Note 3)
MSL
3
MSL, 20−Lead, LS Temperature 230°C Peak (Note 4)
MSL
1
MSL, 8−Lead, 14−Lead, LS Temperature 260°C Peak (Note 3)
MSL
1
Parameter
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114.
Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115.
2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78.
3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.
4. +5°C/−0°C, 30 Sec Max−at−Peak, 60 − 150 Sec above 183°C.
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3
NCV4269
ELECTRICAL CHARACTERISTICS (TJ = −40°C ≤ TJ ≤ 125°C, VI = 13.5 V unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
VQ
1 mA v IQ v 100 mA 6 V v VI v 16 V
4.90
5.00
5.10
V
Current Limit
IQ
−
150
200
500
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 1 mA, RO, SO High
−
240
250
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 10 mA, RO, SO High
−
250
450
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 50 mA, RO, SO High
−
2.0
3.0
mA
Dropout Voltage
Vdr
VI = 5 V, IQ = 100 mA
−
0.25
0.5
V
Load Regulation
DVQ
IQ = 5 mA to 100 mA
−
10
20
mV
Line Regulation
DVQ
VI = 6 V to 26 V IQ = 1 mA
−
10
30
mV
VRT
−
4.50
4.65
4.80
V
VRAD,JTH
VQ > 3.5 V
1.26
1.35
1.44
V
Reset Pullup Resistance
RSO,INT
−
10
20
40
kW
Reset Output Saturation Voltage
VRO,SAT
VQ < VRT, RRO, INT
−
0.1
0.4
V
Upper Delay Switching Threshold
VUD
−
1.4
1.8
2.2
V
Lower Delay Switching Threshold
VLD
−
0.3
0.45
0.60
V
VD,SAT
VQ < VRT
−
−
0.1
V
Charge Current
ID
VD = 1 V
3.0
6.5
9.5
mA
Delay Time L ³ H
td
CD = 100 nF
17
28
−
ms
Delay Time H ³ L
tt
CD = 100 nF
−
1.0
−
ms
Sense Threshold High
VSI, High
−
1.24
1.31
1.38
V
Sense Threshold Low
VSI, Low
−
1.16
1.20
1.28
V
Sense Output Saturation Voltage
VSO, Low
VSI < 1.20 V; VQ > 3 V; RSO
−
0.1
0.4
V
RSO,INT
−
10
20
40
kW
ISI
−
−1.0
0.1
1.0
mA
REGULATOR
RESET GENERATOR
Reset Switching Threshold
Reset Adjust Switching Threshold
Saturation Voltage on Delay Capacitor
INPUT VOLTAGE SENSE
Sense Resistor Pullup
Sense Input Current
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4
NCV4269
II
I
CI
470 nF
1000 mF
IQ
Q
CQ
22 mF
RADJ1
ISI
VI
SI
D
GND
ID
VSI
RADJ
SO
RO
Iq
VRO
IRADJ
VSO
VQ
VRADJ
VD
CD
100 nF
RADJ2
Figure 2. Measuring Circuit
VI
t
< tRR
VQ
VRT
dV
I
+ D
dt
CD
VD
VUD
t
VLD
td
t
tRR
VRO
VROSAT
Power−on−Reset
t
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Figure 3. Reset Timing Diagram
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5
Secondary
Spike
Overload
at Output
NCV4269
Sense Input Voltage
VSLHIGH
VSLLOW
t
Sense Output Voltage
tPDSOLH
tPDSOHL
HIGH
LOW
t
Figure 4. Sense Timing Diagram
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6
NCV4269
APPLICATION DESCRIPTION
OUTPUT REGULATOR
If the reset adjust option is not needed, the RADJ pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
The output is controlled by a precision trimmed reference.
The PNP output has base drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead D
provides charge current ID (typically 6.5 mA) to the external
delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (VRT, reset
threshold voltage) has been violated. When the
delay capacitor discharges to VLD, the reset signal
RO pulls low.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage VQ
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer VD
passes VUD, the reset signal RO goes high. A discharge of
the delay timer VD is started when VQ drops and stays below
the reset threshold voltage VRT. When the voltage of the
delay timer VD drops below the lower threshold voltage VLD
the reset output voltage VRO is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor
with an internal 20 kW pullup resistor connected to the
output Q, controlled by a low voltage detection circuit. The
circuit is functionally independent of the rest of the IC,
thereby guaranteeing that RO is valid for VQ as low as 1.0 V.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of VDSAT to
the higher level VUD. The time delay follows the equation:
td + [CD (VUD * VDSAT)]ńID
Example:
Using CD = 100 nF.
Use the typical value for VDSAT = 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.
RESET ADJUST (RADJ)
The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 5. The resistor divider keeps the voltage
above the VRADJ,TH (typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
I
CI*
Q
VDD
CQ**
10 mF
RADJ1
0.1 mF
RADJ
RADJ2
NCV4269
D
Microprocessor
VBAT
td + [100 nF (1.8 * 0.1 V)] ń 6.5 mA + 26.2 ms (eq. 3)
(eq. 1)
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) ń RADJ2
RSI1
SI
RSI2
CD
SO
(eq. 2)
RO
I/O
GND
*CI required if regulator is located far from the power supply filter.
** CQ required for Stability. Cap must operate at minimum temperature expected.
Figure 5. Application Diagram
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7
I/O
NCV4269
SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE
MONITOR
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
The value for the output capacitor CQ shown in Figure 5
should work for most applications; however, it is not
necessarily the optimized solution. Stability is guaranteed at
values CQ = 10 mF and an ESR = 10 W within the operating
temperature range. Actual limits are shown in a graph in the
typical data section.
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
output is from an open collector driver with an internal
20 kW pull up resistor to output Q. The reset signal typically
turns the microprocessor off instantaneously. This can cause
unpredictable results with the microprocessor. The signal
received from the SO pin will allow the microprocessor time
to complete its present task before shutting down. This
function is performed by a comparator referenced to the
band gap voltage. The actual trip point can be programmed
externally using a resistor divider to the input monitor SI
(Figure 5). The values for RSI1 and RSI2 are selected for a
typical threshold of 1.20 V on the SI Pin.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 5) is:
SIGNAL OUTPUT
PD(max) + [VI(max) ) VQ(min)] IQ(max) ) VI(max) Iq (eq. 4)
Figure 6 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 5. As the output
voltage (VQ) falls, the monitor threshold (VSILOW), is
crossed. This causes the voltage on the SO output to go low
sending a warning signal to the microprocessor that a reset
signal may occur in a short period of time. TWARNING is the
time the microprocessor has to complete the function it is
currently working on and get ready for the reset
shutdown signal.
where:
VI(max) is the maximum input voltage,
VQ(min) is the minimum output voltage,
IQ(max) is the maximum output current for the application,
and Iq is the quiescent current the regulator consumes at
IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA = (150°C – TA) / PD
VQ
(eq. 5)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. The current
flow
and
voltages
are
shown
in
the
Measurement Circuit Diagram.
SI
VSILOW
VRO
HEATSINKS
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
SO
TWARNING
Figure 6. SO Warning Waveform Time Diagram
RqJA + RqJC ) RqCS ) RqSA
STABILITY CONSIDERATIONS
The input capacitor CI in Figure 5 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1.0 W in series
with CI.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
(eq. 6)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heat sink thermal resistance, and
RqSA = the heat sink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in data sheets of
heatsink manufacturers. Thermal, mounting, and
heatsinking considerations are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor website.
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8
NCV4269
ORDERING INFORMATION
Device
Output Voltage
Package
NCV4269D1
SO 8
SO−8
NCV4269D1R2
NCV4269D2
NCV4269D2R2
50V
5.0
SO 14
SO−14
NCV4269DW
SO 20L
SO−20L
NCV4269DWR2
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9
Shipping
98 Units/Rail
2500 Tape & Reel
55 Units/Rail
2500 Tape & Reel
38 Units/Rail
1000 Tape & Reel
NCV4269
PACKAGE DIMENSIONS
SO−8
D SUFFIX
CASE 751−07
ISSUE AD
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
RECOMMENDED FOOTPRINT
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
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10
mm Ǔ
ǒinches
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCV4269
PACKAGE DIMENSIONS
SO−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
14
8
−B−
1
P 7 PL
0.25 (0.010)
7
G
D 14 PL
0.25 (0.010)
M
F
T B
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
B
R X 45 _
C
−T−
SEATING
PLANE
M
S
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
SO−20L
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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11
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
NCV4269
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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