NUP4202W1 Low Capacitance SC−88 Diode−TVS Array for High Speed Data Lines Protection http://onsemi.com The NUP4202W1 transient voltage suppressor is designed to protect high speed data lines from ESD, EFT, and lightning. Features: • Low Capacitance (3 pF Maximum Between I/O Lines) • ESD Rating of Class 3B (Exceeding 8 kV) per Human Body model • • • and Class C (Exceeding 400 V) per Machine Model Protection for the Following IEC Standards: IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact) IEC 61000−4−4 (EFT) 40 A (5/50 ns) IEC 61000−4−5 (Lightning) 23 A (8/20 ms) UL Flammability Rating of 94 V−0 This is a Pb−Free Device PIN CONFIGURATION AND SCHEMATIC Typical Applications: • • • • • SC−88 LOW CAPACITANCE DIODE TVS ARRAY 500 WATTS PEAK POWER 6 VOLTS High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data Line Protection Digital Video Interface (DVI) and HDMI Monitors and Flat Panel Displays MP3 I/O 1 6 I/O VN 2 5 VP I/O 3 4 I/O MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 1 Symbol Value Unit Peak Power Dissipation 8 x 20 mS @ TA = 25°C (Note 1) Ppk 500 W SC−88 CASE 419B PLASTIC Operating Junction Temperature Range TJ −40 to +125 °C MARKING DIAGRAM Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD 16000 400 20000 20000 V Rating Human Body Model (HBM) Machine Model (MM) IEC 61000−4−2 Air (ESD) IEC 61000−4−2 Contact (ESD) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Nonrepetitive current pulse per Figure 1 (Pin 5 to Pin 2) 6 63 MG G 1 63 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NUP4202W1T2G Package Shipping SC−88 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 2 1 Publication Order Number: NUP4202W1/D NUP4202W1 ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage Conditions VRWM Breakdown Voltage Min Typ (Note 2) VBR IT = 1 mA, (Note 3) Max Unit 5.0 V 6.0 V 5.0 mA 8.5 12.5 V 8.9 20 V 28 A VR = 0 V, f = 1 MHz between I/O Pins and GND 3.0 5.0 pF VR = 0 V, f = 1 MHz between I/O Pins 1.5 3.0 pF Reverse Leakage Current IR VRWM = 5 V Clamping Voltage VC IPP = 5 A (Note 4) Clamping Voltage VC IPP = 8 A (Note 4) Maximum Peak Pulse Current IPP 8x20 ms Waveform Junction Capacitance CJ Junction Capacitance CJ 2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. Nonrepetitive current pulse per Figure 1 (Pin 5 to Pin 2) TYPICAL PERFORMANCE CURVES 100 100 90 90 % OF PEAK PULSE CURRENT PEAK POWER DISSIPATION (%) (TJ = 25°C unless otherwise noted) 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 200 PEAK VALUE IRSM @ 8 ms tr 0 20 TA, AMBIENT TEMPERATURE (°C) 20 4.5 18 CLAMPING VOLTAGE (V) JUNCTION CAPACITANCE (pF) 5.0 4.0 3.5 I/O−Ground 2.5 2.0 I/O lines 1.5 1.0 0.5 0.0 60 80 Figure 2. 8 × 20 ms Pulse Waveform Figure 1. Pulse Derating Curve 3.0 40 t, TIME (ms) 16 14 12 10 8 6 4 2 0 1 2 3 4 0 5 0 VBR, REVERSE VOLTAGE (V) 10 20 30 40 50 PEAK PULSE CURRENT (A) Figure 4. Clamping Voltage vs. Peak Pulse Current (8 x 20 ms Waveform) Figure 3. Junction Capacitance vs Reverse Voltage http://onsemi.com 2 NUP4202W1 APPLICATIONS INFORMATION Option 2 Protection of four data lines with bias and power supply isolation resistor. The new NUP4202W1 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the NUP4202W1 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (SC−88). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. I/O 1 I/O 2 VCC 1 6 10 k 2 5 3 4 I/O 3 I/O 4 NUP4202W1 Configuration Options The NUP4202W1 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or Vcc+Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. The NUP4202W1 can be isolated from the power supply by connecting a series resistor between pin 5 and Vcc. A 10 kW resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the internal TVS diode as reference. I/O 1 I/O 2 Option 1 Protection of four data lines and the power supply using Vcc as reference. I/O 1 I/O 2 1 6 2 5 3 4 NC I/O 3 1 6 2 5 3 4 I/O 4 In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc=Vf + VTVS). VCC I/O 3 I/O 4 For this configuration, connect pin 5 directly to the positive supply rail (Vcc), the data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. ESD Protection of Power Supply Lines When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: http://onsemi.com 3 NUP4202W1 Power Supply IESDpos VCC Protected Data Line Device inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4202W1 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. D1 IESDpos IESDneg D2 IESDneg VF + VCC −VF Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = Vcc + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply D1 D3 D5 D7 D2 D4 D6 D8 0 IESDpos NUP4202W1 Equivalent Circuit VCC Protected Device D1 IESDpos D2 VC = VCC + Vf + (L diESD/dt) IESDneg During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. IESDneg Data Line Power Supply VCC D1 VC = −Vf − (L diESD/dt) Protected Device An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = Vcc + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic IESDpos Data Line D2 The resulting clamping voltage on the protected IC will be: Vc = VF + VTVS. The clamping voltage of the TVS diode is provided in Figure 4 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. http://onsemi.com 4 NUP4202W1 TYPICAL APPLICATIONS UPSTREAM USB PORT VBUS VBUS VBUS VBUS D+ RT D+ RT D− VBUS GND USB Controller D− VBUS NUP4202W1 CT CT DOWNSTREAM USB PORT GND VBUS VBUS NUP2202W1 RT D+ RT D− GND DOWNSTREAM USB PORT CT CT ESD Protection for USB Port RJ45 Connector TX+ TX+ TX− TX− PHY Ethernet (10/100) Coupling Transformers RX+ RX+ RX− RX− NUP4202W1 VCC GND N/C Protection for Ethernet 10/100 (Differential mode) http://onsemi.com 5 N/C NUP4202W1 R1 RTIP R3 R2 RRING T1 VCC T1/E1 TRANCEIVER NUP4202W1 R4 TTIP R5 TRING T2 TI/E1 Interface Protection http://onsemi.com 6 NUP4202W1 PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419B−01 OBSOLETE, NEW STANDARD 419B−02. D e 6 5 4 1 2 3 HE DIM A A1 A3 b C D E e L HE −E− b 6 PL 0.2 (0.008) M E MILLIMETERS MIN NOM MAX 0.80 0.95 1.10 0.00 0.05 0.10 0.20 REF 0.10 0.21 0.30 0.10 0.14 0.25 1.80 2.00 2.20 1.15 1.25 1.35 0.65 BSC 0.10 0.20 0.30 2.00 2.10 2.20 M A3 C A A1 L SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES NOM MAX 0.037 0.043 0.002 0.004 0.008 REF 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 0.045 0.049 0.053 0.026 BSC 0.004 0.008 0.012 0.078 0.082 0.086 MIN 0.031 0.000 NUP4202W1 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 8 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NUP4202W1/D