Renesas M6MGT331S4BKT 33,554,432-bit (2,097,152 - word by 16-bit/4,194,304-word by 8-bit) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit/524,288-word b Datasheet

Renesas LSIs
Preliminary
M6MGB/T331S4BKT
Notice: This is not a final specification.
Some parametric limits are subject to change.
33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT/524,288-WORD BY 8-BIT) CMOS SRAM
Stacked - µ MCP (micro Multi Chip Package)
Description
The M6MGB/T331S4BKT is a Stacked micro Multi Chip
Package (S- µMCP) that contents 32M-bit Flash memory and
4M-bit Static RAM in a 52-pin TSOP for lead free use.
M6MGB/T331S4BKT provides for Software Lock Release
function. Usually, all memory blocks are locked and can not
be programmed or erased, when F-WP# is low. Using
Software Lock Release function, program or erase operation
can be executed.
32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words,
Features
3.3V-only, and high performance non-volatile memory
fabricated by CMOS technology for the peripheral circuit and
Access Time
DINOR (Divided bit-line NOR) architecture for the memory cell.
4M-bit SRAM is a 524,288 bytes / 262,144 words
asynchronous SRAM fabricated by silicon-gate CMOS
technology.
M6MGB/T331S4BKT is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight.
Flash
70ns (Max.)
SRAM
70ns (Max.)
Supply Voltage
VCC=2.7 ~ 3.0V
Ambient Temperature
Ta=-40 ~ 85 °C
Package
52pin TSOP(Type-II),
Lead pitch 0.4mm
Outer-lead finishing:Sn-Cu
Application
Mobile communication products
10.79 mm
PIN CONFIGURATION (TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A8
A19
S-CE1#
WE#
F-RP#
F-WP#
S-VCC
S-CE2
DU
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
M6MGB/T331S4BKT
10.49 mm
F-VCC
S-VCC
GND
A-1-A17
A18-A20
DQ0-DQ15
F-CE#
S-CE#,S-CE2
OE#
WE#
1
:Vcc for Flash
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
A16
BYTE#
S-UB#
GND
S-LB#
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
F-VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
F-CE#
A0
Outline 52PTJ-A
F-WP#
F-RP#
F-RY/BY#
BYTE#
S-LB#
S-UB#
DU
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready/Busy
:Flash/SRAM Byte Enable
:SRAM Lower Byte
:SRAM Upper Byte
:Do not use
Rev.0.1_48a_beez
Renesas LSIs
Preliminary
M6MGB/T331S4BKT
Notice: This is not a final specification.
Some parametric limits are subject to change.
33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT/524,288-WORD BY 8-BIT) CMOS SRAM
Stacked - µ MCP (micro Multi Chip Package)
MCP Block Diagram
F-Vcc
GND
1)
1)
A0 to A20
A0 to A20
F-CE#
F-WP#
F-RP#
BYTE#
32Mbit DINOR
Flash Memory
1)
S-Vcc
DQ0 to DQ15
1)
A0 to A17
WE#
OE#
S-UB#
S-LB#
S-CE1#
S-CE2
4Mbit
SRAM
Note 1): In case of x8 organization, A-1 is added, and only Lower Byte data(DQ0 to DQ7) are assigned to I/O and
Upper Byte data(DQ8 to DQ15) are High-Z.
Note 2): In the flash memory part there are “VCC”s which mean “F-VCC”.
In the SRAM part there are “UB#” and “LB#” which mean “S-UB#” and “S-UB#”, respectively.
Note 3): “DU(Don’t Use)” pin must be OPEN ,otherwise be inputted within 0V ~ Vcc.
Capacitance
Symbol
Parameter
Input
A20-A0, OE#, WE#, F-CE#, F-WP#, F-RP#,
capacitance S-CE1#, S-CE2, BYTE#, S-LB#, S-UB#
Output
COUT
DQ15-DQ0
Capacitance
CIN
2
Conditions
Ta=25°C,
f=1MHz,
Vin=Vout=0V
Min.
Limits
Typ.
Max.
Unit
18
pF
22
pF
Rev.0.1_48a_beez
Renesas LSIs
M6MGB/T331S4BKT
33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT/524,288-WORD BY 8-BIT) CMOS SRAM
Stacked - µ MCP (micro Multi Chip Package)
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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REJ03C0157
© 2003 Renesas Technology Corp.
New publication, effective April 2003.
Specifications subject to change without notice
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