NCP4326
Secondary Controller for
Multi−Output
Quasi−Resonant
Switchmode Power
Supplies
http://onsemi.com
This secondary controller significantly improves the overall
efficiency and cross−regulation figures when used in a Switchmode
Power Supply. Compared to traditional regulation schemes, the
NCP4326 provides superior performance in cross−regulation by
individually regulating outputs. Powered from a main winding, the
device actuates two independent switches that precisely adjust the
considered outputs to resistor−selectable voltages. This controller also
integrates a precision reference voltage, which together with a
dedicated operational amplifier reduces the feedback loop elements to
the minimum. In the end three independent output voltages can be
controlled by a single device.
A skip cycle feature improves the stand by power in light load
condition. Finally, dedicated shutdown pins offer an easy mean to
disable the secondary outputs in applications where a low standby
power performance is key.
MARKING DIAGRAM
NCP4326DG
AWLYWW
SOIC−16
D SUFFIX
CASE 751B
A
WL
Y
WW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
PIN CONNECTIONS
Features
•
•
•
•
•
•
•
•
•
•
•
•
0% to 100% Duty Cycle Range
Integrated Shunt Regulator for Optocoupler Control
Internal Voltage Reference (1.25 V, 1% @ 25°C)
2 Independent Power MOSFET Drivers
Enable/Disable for Each Driver
Independent Soft−Starts on both Output Drivers
Independent Skip Cycle on both Output Drivers
Standby Pin
580 / 650 mA Peak Current Source/Sink Driver Capability
Synchronization Pin
5 V Undervoltage Lock−Out on Vcc
Pb−Free Package is Available
1
16
EN1
FB1
2
15
GND
EN2
3
14
Flux
CP2
4
13
DRV1
FB2
5
12
Vcc
Ct
6
11
DRV2
Sync
7
10
STBY
CPm
8
9
FBm
(Bottom View)
ORDERING INFORMATION
Package
Shipping{
NCP4326DR2
SOIC−16
3000 Tape & Reel
NCP4326DR2G
SOIC−16
(Pb−Free)
3000 Tape & Reel
Device
Applications
• Consumer Electronics Applications:
•
CP1
DVD, Set Top Box, CDR, Game Console
Any Multi−Output Voltage Quasi−Resonant SMPS
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 1
1
Publication Order Number:
NCP4326/D
NCP4326
Mag
VregM
D8
L1
T1
+
2.2 H
C3
2.2 mF
Vout_12V
+
C4
100 F
GND
D5
Q4
+
DRV1
L2
10 H
C5
470 F
Vout_5V
+
C6
100 F
GND
D6
Q5
+
DRV2
L3
10 H
C8
470 F
Vout_3V3
+
C7
100 F
GND
GND
+ C9
470 F
D4
Neg Out
R14
C10
10k
2.2 nF
GND
R5
R15
3.32k
1.1k
Vout_5V
GND
C13
R8
Vout_3V3
R6
825
RES1
10 nF
EN2
C12
100 nF
C14
RES1
10 nF
GND
R10
R9
RES1
VregM
EN1
FB1
GND
EN2
Flux
CP2
DRV1
FB2
VCC
2
4
RES1
C17
CAP
16
15
C11
100 nF
GND
14
13
DRV1
12
6
11
Ct
DRV2
SYNC
STBY
CPm
FBm
7
Mag
GND
CP1
5
C16
CAP
R13
511
1
3
GND
R7
EN1
U3
NCP4326
8
10
DRV2
R18
8.66k
STBY
9
R17
1k
R16 GND
1k
R11
C15
RES1
10 nF
GND
Figure 1. Typical Application Schematic
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2
NCP4326
Mag
VregM
T1
Dem
+ C3L1 2.2 H
2.2mF
D5
Q2 + L2 10 H
C5
470 F
+ C6
Q8 + L3 10 H
C8
470 F
+ C7
D1
R3
150 1N4148
C1
22 F
DRV1
D2
D6
P1
+
R4
15k
R1
D8
C2
220 F
DRV2
U1
NCP1207A
1 DMG HV 8
2
FB
NC 7
C18
3
47pF
4
CS
VCC
GND DRV
TRANSFO
R5
Vout_5V
3.32k
6
5
Vout_3V3
Q1
RES1
R12
0R5
R2
4.7k
R13
511
Mag
GND
R8
C13 1
RES1
10 nF 2
C12
3
100 nF
4
10 nF
RES1
VregM
GND
R17
C10
10k
2.2 nF
5
C16
CAP
R10
RES1
C17
CAP
6
7
8
U3
NCP4326
CP1
EN1
FB1
GND
EN2
Flux
CP2
DRV1
FB2
VCC
Ct
DRV2
SYNC STBY
CPm
FBm
16
15
14
13
Figure 2. Typical Application Schematic
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3
EN1
100 nF
C11
GND
DRV1
12
11
10
DRV2
STBY
R18
8.66k
9
R16
1k GND
U2
SFH6151−2
GND
Vout_3V3
100uF
GND
1.1k
GND
R9
GND
Vout_5V
GND
R15
R6
EN2
825
GND
R7
C14
Vout_12V
100uF
GND
+ C9
470 F
Neg Out
D4
Dem
39k
+ C4
100uF
R17
1k
R11
C15
RES1
10 nF
GND
NCP4326
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Type
Description
1
CP1
Error Amplifier
Output 1
This pin is the output of the error amplifier 1 (monitoring the secondary voltage #1) and is
available for loop compensation purpose.
2
FB1
Voltage
Feedback 1
This is the inverting input of the error amplifier 1. It is connected to the secondary voltage
#1 via a bridge resistor divider.
3
EN2
Soft−Start and
Enable or Disable
the Driver 2
4
CP2
Error Amplifier
Output 2
This pin is the output of the error amplifier 2 (monitoring the secondary voltage #2) and is
available for loop compensation purpose.
5
FB2
Voltage
Feedback 2
This is the inverting input of the error amplifier. It is connected to the secondary voltage #2
via a bridge resistor divider.
6
Ct
Ct Pin
7
Sync
Synchronization
Pin
This pin monitors the main secondary winding, detects the beginning and the end of the
demagnetization phase (TOFF time on the primary winding) and allows the regulation on
the two secondary outputs.
8
CPm
Shunt Regulator
Output
This pin is the output of the shunt regulator (monitoring the main secondary voltage). An
open collector configuration is implemented.
9
FBm
Main Voltage
Feedback
This is the inverting input of the internal error amplifier. It is connected to the main output
voltage via a bridge resistor divider.
10
STBY
Standby
11
DRV2
Output Driver 2
This output directly drives the gate of a power MOSFET.
12
Vcc
Supplies the IC
This pin is connected to the main secondary output voltage and internally powers the IC.
13
DRV1
Output Driver 1
This output directly drives the gate of a power MOSFET.
14
Flux
Voltage image of
the magnetic flux
15
GND
The IC ground
16
EN1
Soft−Start and
Enable or Disable
the driver 1
This pin enables or disables the driver 2. An internal current source with an external
capacitor generates also a soft−start feature for limiting the startup peak current on the
controlled output.
This pin can be left open and by default it enables the driver 2, but without soft−start
feature.
Connect the timing capacitor between Ct and the ground.
This pin is internally pulled up and allows standby mode feature. This pin can be left open
and by default it enables standard working mode. When this pin is pulled down standby
mode is activated and the quiescent current is reduced to the minimum. The output drivers
are disabled.
A RC network connected between this pin and a forward winding or a negative output
winding generates the transformer’s flux image. This flux image is compared to a slow
ramp generated on ENx pin for the soft−start Duty Cycle generation controlling the both
outputs.
−
This pin enables or disables the driver 1. An internal current source with an external
capacitor generates also a soft−start feature for limiting the startup peak current on the
controlled output.
This pin can be left open and by default it enables the driver 1, but without soft−start
feature.
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4
NCP4326
VDD1*
VDD**
*VDD1 is not available in standby mode
**VDD is available all the time
Vcc OK
VCC
VCC
UVLO
2V5
VOLTAGE
REFERENCE
12 VCC
STBY
EN1 16
1V25
Vcc OK
DRV1 13
1 CP1
2 FB1
VDD1
CHANNEL 1
1V25
VDD1
+
STBY
−
4 CP2
STBY 10
2V5
GND
DRV 11
5 FB2
CHANNEL 2
VDD
ICt
6
Ctramp
EN2 3
Ct
VDD
−
7 Sync
Enable or
Int_sync
4V5
1V6
GND
+
GND
Int_Flux
4V0
GND
GND
Offset
0V5
VDD
Clamp
+
0V 1V
GND
GND 15
GND
Flux 14
−
9 FBm
OPAMP with
Open Collector Output
VDD1
−
8 CPm
+
GND
8.5R
R
1V25
GND
GND
Int_Flux
CHANNEL x
VDD
IENx
ENx
5V0
VDD
CPx
VDD
VDD
FBx
−
+
1V25
+
−
GND
GND
Ctramp
+
−
Vcc OK
GND GND
VCC
DRVx
LOGIC
LATCH
GND
Int_Sync
STBY
Figure 3. Internal Circuit Architecture
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5
NCP4326
MAXIMUM RATINGS
Rating
Symbol
Power Supply Voltage on Pin 12 (Vcc), Pin 8 (CPm) and Pin 13/11 (DRV1/DRV2)
Maximum Voltage on all other pins except Pin 12 (Vcc), Pin 8 (CPm) and Pin 13/11
(DRV1/DRV2)
Maximum Current into all pins except Pin 12 (Vcc) and Pin 13/11 (DRV1/DRV2)
when ESD diodes are activated
Maximum current in Pin 7 (Sync)
Value
Unit
16
V
−0.3 to 6
V
5
mA
+3/−3
mA
Thermal Resistance, Junction−to−Case
RθJC
55
°C/W
Thermal Resistance, Junction−to−Air
RθJA
150
°C/W
TJMAX
150
°C
−60 to +150
°C
2
200
kV
V
Maximum Junction Temperature
Storage Temperature Range
ESD Capability
Human Body Model (HBM)
Machine Model (MM)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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6
NCP4326
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +105°C, Vcc = 12 V unless
otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)
11, 13
tr1, 2
−
60
100
ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)
11, 13
tf1, 2
−
40
100
ns
11, 13
VOL1, 2
−
−
1.5
1.0
2.2
1.5
−
0.5
1.0
11
12
13.4
13.5
−
−
Drive Output (Note 1)
Output Voltage Low State @ Vcc = 15 V
(Isink = 250 mA)
(Isink = 20 mA)
Output Voltage Low State with UVLO activated @ Vcc = 4.0 V
(Isink = 1.0 mA) (Note 1)
11, 13
VOL_UVLO1, 2
Output Voltage High State @ Vcc = 15 V
11, 13
VOH1, 2
(Isource = 250 mA)
(Isource = 20 mA)
V
V
V
Standby Pin
Input Threshold Voltage (VSTBY increasing)
10
Vth
−
2.5
−
V
Hysteresis (VSTBY decreasing)
10
VH
−
600
−
mV
Standby Propagation Delay when the Standby Mode is activated
with 1 nF connected to DRVx pin and with VCPx > 4.0 V (Figure 4)
10
Tstby_on
−
550
−
ns
Standby Propagation Delay when the Standby Mode is released,
ENx pin is floating, VCPx > 4.0 V and with 1.0 nF connected to DRVx
pin (Figure 4)
10
Tstby_off
−
1.0
−
s
Pullup Resistor Value
10
Rpullup
−
40
−
k
Enable Soft−Start Mode or Disable Driver Mode Threshold
(Note 2, Figure 5)
3, 16
VENX_TH1
0.5
0.75
1.0
V
Maximum Voltage on ENx pin ending Soft−Start and Enable the
Regulation Mode (Figure 5)
3, 16
VENX_TH2
−
4.5
4.8
V
Voltage on ENx pin when ENx is floating
3, 16
VENX_max1
−
5.0
−
V
Voltage on ENx pin with External Sink Current @ 500 A
3, 16
VENX_max2
−
5.1
−
V
Internal Current Source when VENX = 2.5 V (Note 3)
3, 16
IENX
120
160
220
A
Turn ON Propagation Delay in Soft−Start Mode (Note 4) when
applying an external falling edge on Flux pin from 100 mV to 0 V @
VENX = 1.0 V, VCPx = 5.0 V and 1.0 nF connected to DRVx pin.
(Timing definition see Figure 6)
3, 14 and 11
or
16, 14 and 13
TSS_ON
−
450
800
ns
Turn OFF Propagation Delay in Soft−Start Mode (Note 4) when
applying an external rising edge on Flux pin from 0 V to 100 mV @
VENX = 1.0 V, VCPx = 5.0 V and 1.0 nF connected to DRVx pin.
(Timing definition see Figure 6)
3, 16
TSS_OFF
−
450
800
ns
Discharge time when the controller is placed in Standby or when the
Vcc is removed @ CENX = 330 nF from 90% of VEN_max1 to
VENX_TH1 (Figure 1)
3, 16
Tstby_disch
−
1.0
−
ms
Enable/Soft−Start Pin
1.
2.
3.
4.
The output drivers are kept OFF when the Vcc < UVLO level.
Below the VENX_TH1 threshold the driver is disabled and above this value the soft−start duty cycle generation is allowed.
See characterization curve for charging current versus Vcc and VENX.
Soft−Start mode operation when the VCPx pin = 5.0 V (or when the controlled output voltage is not yet in regulation).
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7
NCP4326
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +105°C, Vcc = 12 V unless
otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Flux Pin
Internal Current Sourced by Flux pin when it is grounded (Note 5)
14
IFlux
−
120
−
A
Maximum Sink Current on Flux pin when the internal 1.0 V clamp is
activated
14
IFlux_max
−
−
1.0
mA
Input Clamp Voltage
High state: when a current is sunk by pin 14 (Ipin 14 = IFlux_max)
Low state: when a current is sourced by pin 14 (Ipin 14 = −1.0 mA)
14
VFlux_H
VFlux_L
−
−
1.4
−60
−
−
V
mV
Internal Voltage gain of input signal sensed on Flux pin
(guaranteed by design)
14
Gain
−
9.5
−
N/A
Input Threshold Voltage (Vpin 7 decreasing)
7
Vsync_th
50
70
100
mV
Hysteresis (Vpin 7 increasing)
7
Vsync_Hyst
−
35
−
mV
Maximum Sink Current on Sync pin when the internal 7.0 V clamp is
activated
7
Isync_max
−
−
3.0
mA
Input Clamp Voltage
High state: when a current is sunk by pin 7 (Ipin 7 = Isync_max)
Low state: when a current is sourced by pin 7 (Ipin 7 = −3.0 mA)
7
7
VCH
VCL
−
−
7.4
−0.3
−
−
Delay between the Sync and DRVx pin (Figures 8 and 9), when
applying a falling edge on Sync in normal mode operation (Note 6)
with 1.0 nF connected to DRVx pin
7 and 11
or
7 and 13
Tprop_ON
−
200
500
ns
4, 7 and 11
or
1, 7 and 13
Tprop_OFF
−
280
500
ns
7
Cpar
−
10
−
pF
Voltage Feedback Input @ TJ = 25°C (Note 7)
* Voltage follower measurement to reach 1% accuracy
2, 5
VFB1, 2
1.241
1.253
1.266
V
Input Bias Current (VFB = 1.30 V)
2, 5
IIB1, 2
−
−0.1
−
A
Open Loop Voltage Gain (VCPx = 1.0 V to 5.0 V)
2, 5
AVOL1, 2
−
90
−
dB
Unity Gain Bandwidth (TJ = 25°C)
2, 5
BW1, 2
−
3.3
−
MHz
Power Supply Rejection Ratio
(Vcc = 10 V to 15 V, Frequency range 120 Hz)
2, 5
PSRR1, 2
−
55
−
dB
Output Current
Sink Current (VCPx = 1.1 V, VFB = 1.45 V)
Source Current (VCPx = 4.5 V, VFB = 1.05 V)
1, 4
1, 4
Isink1, 2
Isource1, 2
2.0
−
+6.0
−13
−
−5.0
Output Voltage Swing
High State (RL = 15 k to Ground, VFB=1.05 V)
Low State (RL = 15 k to Vcc, VFB =1.45 V)
1, 4
1, 4
VOH1, 2
VOL1, 2
4.8
−
5.0
0.7
−
1.1
Synchronization Block
V
Delay between the Ct voltage (VCt) and DRVx pin (Figures 8 and 9),
when applying a rising edge on Ct @ VCPx = 1.7 V in normal mode
operation (Note 6) with 1.0 nF connected to DRVx pin
Internal input capacitance at Vpin 7 = 1.0 V
Error Amplifier Section 1 and 2
mA
V
5. See characterization curves IFlux_pin (VFlux_pin) with −100 mV < VFlux_pin < +100 mV.
6. Normal operation when VENX > VENX_TH3.
7. See characterization curve for Voltage Reference vs. Temperature.
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8
NCP4326
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +105°C, Vcc = 12 V unless
otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Voltage Feedback Input @ TJ = 25°C (Note 8)
* Voltage follower measurement to reach 1% accuracy
9
VFB
1.241
1.253
1.266
V
Input Bias Current (VFB = 1.30 V)
9
IIB
−
−0.1
−
μA
Open Loop Voltage Gain (VCPm = 1.0 V to 5.0 V)
9
AVOL
−
90
−
dB
Unity Gain Bandwidth (TJ = 25°C)
9
BW
−
3.3
−
MHz
Power Supply Rejection Ratio
(Vcc = 10 V to 15 V, Frequency range 120 Hz)
9
PSRR
−
55
−
dB
Output Current − Sink Current (VCPm = 1.1 V, VFB = 1.45 V)
8
Isink
12
60
−
mA
Output Voltage Swing − Low State (RL = 15 k to Vcc, VFB = 1.45 V)
8
VOL
−
0.7
1.1
V
Shunt Regulator
Ct Pin
Minimum Voltage on Ct pin
6
VCT_min
1.4
1.6
−
V
Maximum Voltage on Ct pin when Ct pin is floating
6
VCt_max1
−
4.0
−
V
Maximum Voltage on Ct pin with External Sink Current @ 500 A
6
VCt_max2
−
4.2
−
V
Internal Current Source @ VCt = 2.5 V (Note 9)
6
ICt
450
500
700
A
Discharge time for Ct capacitor @ Ct = 2.7 nF when applying falling
edge on Sync pin to (Vctmin*1.05) (Figure 7)
6
TCt_disch
−
230
500
ns
Startup Threshold
12
VTH
4.8
5.3
6.0
V
Hysteresis
12
Hyste
−
0.5
−
V
−
2.2
3.0
−
17
22
Undervoltage Lockout
IC Current Consumption
Istdby
Power Supply Current in Standby Mode
Vcc = 12 V, STBY = GND, EN1 = EN2 = OPEN (Note 11)
12
Power Supply Current in Working Mode
Vcc= 12 V, STBY = EN1 = EN2 = OPEN
12
mA
Icc
mA
8. See characterization curves for Voltage Reference vs. Temperature.
9. See characterization curve for Charging Current vs. Vcc.
10. When the Vcc < UVLO level, the outputs are automatically disabled.
11. During the standby mode the outputs drivers are disabled but the shunt regulator is kept fully functional in order to supply the primary
feedback.
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9
NCP4326
ENx pin
ENx pin
Tstby_disch
VENX = 5.0 V
VENX_max1*90%
VENX_TH1
Tstby_on
STBY pin
Tstby_off
STBY pin
Vth = 2.5 V
Vth = 2.5 V
DRVx pin
DRVx pin
Vcc/2
Vcc/2
Figure 4. Standby Propagation Delay Definition
ENx pin
Driver in Normal Operation Mode
VENX_TH2
Driver in Soft−Start Mode
VENX_TH1_max
VENX_TH1_min
Driver is disabled
Time
Figure 5. Enable Threshold Definition
Flux Pin
Flux Pin
1.5 V
VINT_Flux
1.0 V
VENX
1.0 V
VENX
0.5 V
VINT_Flux
0.5 V
1.5 V
0.1 V
0.1 V
0V
DRVX Pin
0V
Time
DRVX Pin
TSS_ON
Vcc/2
Time
TSS_OFF
Vcc/2
Time
Time
Figure 6. TSS_ON and TSS_OFF Propagation Delay Definition (in Soft−Start Mode Operation)
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10
NCP4326
Sync Pin
Time
Ct Pin
TCt_disch
VCt_max1
VCt_min*1.05
VCt_min
Time
Figure 7. Discharging Time Definition (Ct Pin)
Sync Pin
Sync Pin
Voltage on Ct Pin
1.6V
CPX
Time
Time
DRVx
DRVx
Tprop_ON
Tprop_OFF
Vcc/2
Vcc/2
Time
Time
Figure 8. Tprop_ON and Tprop_OFF Propagation Delay Definition (in Normal Mode Operation)
Vsync
Vo
0
nl
n p V in
t
2Vo
VCt
VEA
4.0 V
1.5 V
t
Drv
0
Is1 Tprop_ON
Is1_pk
0
Is2
t
Tprop_OFF
t
Is2_pk
0
D blocks
Ts
flyback stroke
t
Figure 9. Tprop_ON and Tprop_OFF Timing Position in the Timing Application Diagram (in Normal Mode Operation)
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NCP4326
14.5
1.10
1.00
14.0
VOL (V)
VOH (V)
VOL @ 250 mA
0.90
VOH @ 20 mA
13.5
0.80
VOH @ 250 mA
0.70
13.0
VOL @ 20 mA
0.60
12.5
0.50
0
20
40
60
80
100
0
120
20
TEMPERATURE (°C)
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. Driver 1 Output Voltage High State
@ VCC = 15 V vs. Temperature
Figure 11. Driver 1 Output Voltage Low State
@ VCC = 15 V vs. Temperature
14.5
1.20
1.10
VOL @ 250 mA
14.0
1.00
VOL (V)
VOH (V)
VOH @ 20 mA
13.5
0.90
VOH @ 250 mA
0.80
13.0
0.70
VOL @ 20 mA
12.5
0
20
40
60
80
100
0.60
120
20
40
60
100
80
120
TEMPERATURE (°C)
Figure 12. Driver 2 Output Voltage High State
@ VCC = 15 V vs. Temperature
Figure 13. Driver 2 Output Voltage Low State
@ VCC = 15 V vs. Temperature
3.0
190
2.9
185
2.8
EN1
180
2.7
175
2.6
IENx (A)
Vth Standby (V)
0
TEMPERATURE (°C)
2.5
2.4
2.3
EN2
170
165
160
2.2
155
2.1
150
2.0
0
20
40
60
80
TEMPERATURE (°C)
100
120
0
20
80
40
60
TEMPERATURE (°C)
100
120
Figure 15. Soft−Start Current Source on Enable
Pin when VENx = 2.5 V vs. Temperature
Figure 14. Standby Pin Threshold Voltage vs.
Temperature
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NCP4326
1.00
4.8
0.95
4.7
0.90
4.6
VENx−TH2 (V)
VENx−TH1 (V)
EN1
0.85
0.80
EN2
0.75
EN1
0.70
4.4
4.3
4.2
0.65
0.60
EN2
4.5
4.1
0
20
40
60
80
100
4.0
120
0
20
TEMPERATURE (°C)
60
80
100
120
TEMPERATURE (°C)
Figure 16. Enable Soft−Start Mode or Disable
Driver Mode vs. Temperature
Figure 17. Max Voltage on ENx Pin Ending
Soft−Start and Enable the Regulation Mode
vs. Temperature
400
5.5
5.4
IEN1
200
5.3
IEN2
0
5.2
5.1
IENx (A)
VENx−max2 (V)
40
EN1
−200
5.0
−400
4.9
EN2
4.8
−600
4.7
−800
4.6
4.5
0
20
40
60
80
100
−1000
120
0
1
2
3
4
5
TEMPERATURE (°C)
VENx (V)
Figure 18. Voltage on ENx Pin with an
External Current Sink @ 500 mA vs.
Temperature
Figure 19. Soft−Start Current Source on
Enable Pin vs. VEN
6
600
190
180
550
TSS_OFF
TSS (ns)
IENx (A)
170
160
150
IEN1
500
TSS_ON
450
IEN2
140
130
400
5
7
9
11
13
0
15
VCC (V)
Figure 20. Soft−Start Current Source on Enable
Pin vs. VCC
20
80
40
60
TEMPERATURE (°C)
100
120
Figure 21. Turn ON and OFF Propagation Delay
in Soft−Start Mode vs. Temperature
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NCP4326
1.50
0.00
−0.01
1.45
−0.02
1.40
Vflux_L (V)
Vflux_H (V)
−0.03
−0.04
1.35
−0.05
1.30
−0.06
−0.07
1.25
1.20
−0.08
−0.09
0
20
40
60
80
100
120
0
20
TEMPERATURE (°C)
Figure 22. High Level Flux Pin Clamp Voltage
vs. Temperature
60
80
100
120
Figure 23. Low Level Flux Pin Clamp Voltage
vs. Temperature
0
100
−200
95
90
Vsync_th (mV)
−400
Iflux (A)
40
TEMPERATURE (°C)
−600
−800
−1000
85
80
75
70
65
−1200
60
−1400
55
−1600
−150
−100
−50
0
50
100
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. Flux Pin Internal Current Source
vs. Flux Voltage
Figure 25. Synchronization Input Voltage
Threshold vs. Temperature
0
1.265
−10
INPUT CURRENT BIAS (nA)
1.270
1.260
Vref (V)
50
150
1.255
Vfb_shunt
1.250
Vfb1
1.245
120
−20
Iib2
−30
−40
Iib_shunt
−50
Iib1
Vfb2
1.240
0
20
40
60
80
TEMPERATURE (°C)
100
120
−60
0
Figure 26. Error Amplifier Internal Voltage
Reference vs. Temperature
20
80
40
60
TEMPERATURE (°C)
100
120
Figure 27. Error Amplifier Input Bias Current
vs. Temperature
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NCP4326
1.0
1200
0.9
1100
0.8
Vol−Shunt (V)
0.7
1000
Vol (mV)
0.6
0.5
0.4
900
800
0.3
0.2
700
0.1
0
0
20
40
60
80
100
600
120
0
10
20
30
ISINK (mA)
TEMPERATURE (°C)
4.6
1.75
4.5
1.70
4.4
Vct−max2 (V)
Vct−min (V)
1.80
1.65
1.60
1.55
4.2
4.1
4.0
1.45
3.9
3.8
1.40
40
60
80
TEMPERATURE (°C)
100
60
4.3
1.50
20
50
Figure 29. Error Amplifier Shunt Regulator Output
Voltage Swing vs. Output Current (Isink)
Figure 28. Error Amplifier Shunt Regulator
Output Voltage Swing vs. Temperature
0
40
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 31. Maximum Voltage Clamp on Ct Pin
@ 500 mA vs. Temperature
Figure 30. Minimum Voltage Clamp on Ct Pin vs.
Temperature
800
700
600
650
400
ICt (A)
ICt (A)
200
600
550
0
−200
−400
−600
500
−800
−1000
450
0
20
40
60
80
100
120
0
1
2
3
4
TEMPERATURE (°C)
VCt (V)
Figure 32. Internal Current Source on Ct Pin
vs. Temperature
Figure 33. Internal Current Source on Ct Pin
vs. VCt
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5
NCP4326
5.50
3.0
5.45
2.9
2.8
5.35
2.7
5.30
2.6
Vth (V)
Istby (mA)
5.40
5.25
5.20
2.5
2.4
5.15
2.3
5.10
2.2
5.05
2.1
5.00
0
20
40
60
80
100
2.0
120
0
80
40
60
TEMPERATURE (°C)
20
TEMPERATURE (°C)
100
120
Figure 35. Power Supply Current in Standby Mode
vs. Temperature
Figure 34. Undervoltage Lockout, Startup
Threshold vs. Temperature
3.0
2.5
Istby (mA)
2.0
1.5
1.0
0.5
0.0
0
5
10
15
VCC (V)
Figure 36. Power Supply Current in Standby
Mode vs. Power Supply Voltage − VCC
20.0
20
19.5
19.0
15
18.0
ICC (mA)
ICC (mA)
18.5
17.5
17.0
10
5
16.5
16.0
0
15.5
15.0
0
20
40
60
80
TEMPERATURE (°C)
100
120
−5
0
Figure 37. Power Supply Current in Working Mode
vs. Temperature
5
10
VCC (V)
15
Figure 38. Power Supply Current in Working
Mode vs. Power Supply Voltage − VCC
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20
NCP4326
APPLICATION INFORMATION
Introduction
The NCP4326 is designed to regulate voltages in multiple
output power supplies running in borderline or critical
conduction mode. It controls two independent switches to
precisely adjust two separate secondary outputs.
A precision reference voltage is integrated together with
a dedicated operational amplifier to reduce the feedback
loop elements to the minimum. A skip cycle feature
improves the standby power in light load condition. A
dedicated shutdown pin offers an easy mean to disable the
secondary outputs.
Q1 On time:
• Q2 is switched ON but no current flows through Q2
due to diode D2 polarized in reverse.
Q1 Off time:
• Q2 is still ON and the energy is delivered to the load.
• Q2 MOSFET is kept ON till the secondary output
reaches the set point.
Mosfet Q2 is switch OFF until a new cycle begins.
Figure 39 illustrates the regulation principle with only one
secondary output regulated by the NCP4326, but it can
regulate independently another one output, that is to say 3
independent outputs.
Regulation Principle
The NCP4326 can handle up to three independent outputs:
it provides the feedback for the main output, and can also
regulates two others secondary outputs.
The secondary outputs behave as a buck converter:
• The voltage is supplied via a secondary winding
voltage
• The switch, inserted in series with the flyback diode, is
controlled by the NCP4326.
Vout_min
D1
L1
+
Sync
+
C1
C2
Vin
GND
Vout1
D2
Q2
+
L2
C3
+
C6
GND
QR
Primary
Controller
Q1
Secondary
Regulation
Primary
Feedback
Opto
Coupler
Secondary Controller
Figure 39. Regulation Principle Schematic
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NCP4326
Detailed Regulation Principle
The Ct capacitor value determines only the voltage swing
present at the Ct pin, which it used to generate the secondary
duty cycle.
The secondary regulation is working in trailing edge mode
control. The trailing edge mode control has been preferred
for its superior cross load performance.
The following picture (Figure 40) shows only one output
regulation, but the second output regulation works similarly
and independently from the other one. Nevertheless, both
regulations use the same synchronization signal:
• Beginning of ON time period (switch ON of the
secondary mosfet)
• The same ramp on Ct pin for adjusting in respect to the
error amplifier level the secondary duty−cycle to the
both outputs drives.
At the beginning of the Ton period the capacitor
connected on Ct pin is discharged and the internal current
source is shunted to VCT_min (1.6 V) via the bipolar
transistor until the end of the Ton period.
The internal current source starts to charge the capacitor
connected on Ct pin at the beginning of the Toff period. As
long as the voltage on the Ct pin is below the CPX pin, the
secondary switch is kept ON (i.e.: The secondary switch is
turned ON at the beginning of the primary on−time). By this
method the secondary power MOSFET can only be
switched ON one time per Toff period and prevents from any
hysteretic switching to the secondary side. The secondary
switch is synchronized with the primary switching
frequency, the secondary controller sets only the duty cycle.
Primary Drain
Switch
ON
Voltage (200 V/div)
Toff
Ton
DRV1 pin signal
(10 V/div)
Switch
OFF
Ct ramp (2 V/div)
Error amplifier
output voltage (CP1
pin) (2 V/div)
Figure 40. Detailed Principle Regulation
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NCP4326
FB Voltage on pin CPx
Duty Cycle Control:
Figure 41 shows the duty cycle value according the opamp
output voltage (CPx pin):
1. If the opamp output (VCPx) is above the maximum
ramp value (VCt_max1) on “Ct” pin then the duty
cycle will be equal to 100%.
2. If VCPx is between the max and the min value of
the ramp voltage, respectively VCt_max1 and
VCt_min1 then the duty cycle will be included
between 0 and 100%.
3. If VCPx is below the min ramp value (VCt_min1)
then the output driver will be place in skip cycle
mode with a null duty cycle.
VOH1, 2min
Duty Cycle = 100%
VCt_max1
0% < Duty Cycle < 100%
Duty Cycle = 0%
VCt_min
VCpx
Time
Figure 41. Duty Cycle Variation versus the
Feedback Voltage
Here after find the experimental results illustrating the skip cycle feature:
0% DC
0% DC
100%
Duty Cycle
DRV2 pin Signal
(10 V/div)
Ct ramp pin signal
(1 V/div)
Variable
Duty Cycle
Figure 42. All Duty Cycle Representation
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Error amplifier
output voltage (CP2
pin) (1 V/div).
NCP4326
Detailed Soft−Start Behavior
the result will not yield a smooth ramp up peak current as in
conventional PWM controllers (see Figure 43).
As depicted in Figure 43, when the secondary duty cycle
is increased smoothly the peak current does not ramp up. It
is not possible to have a ramp up peak current because at the
beginning of the OFF time period the flux stored in the
flyback transformer is at the maximum value so the peak
current yields by this flux will be also at a maximum value.
Consequently, the peak current is not linked to the duty cycle
width. The peak current is only linked to the energy stored
in the flyback transformer and the current sharing during the
primary OFF time.
A soft−start is proposed to avoid a high peak current
during startup sequences in trailing edge mode control.
Increasing smoothly the secondary duty cycle from zero to
the nominal value in trailing edge mode control does not
limit this current (see Figure 43).
NCP4326 is a voltage mode controller type (i.e. the
secondary peak current is not sensed); the peak current
sensing can not be used to ensure a proper peak current ramp
up on secondary side.
Instead of controlling the peak current ramp up, if the
secondary controller smoothly ramps up the duty cycle then
ON Time
Vsync
OFF Time
t
0
VCt
Verror
t
0
Transformateur Flux
t
0
DRV
t
0
ID2
t
0
Figure 43. Increasing Smoothly the Duty Cycle Does Not Yield a Smooth Peak Current Ramp up
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NCP4326
The idea of this soft−start is to reconstruct the flux image
inside the flyback transformer, and to compare this image
with a slow ramp up voltage on enable pin, to generate a
smooth increasing duty cycle in leading edge mode. The
leading edge mode control guarantees that the peak current
ramps up smoothly. Because the secondary duty cycle
finishes at the OFF−time end and starts just before.
At the end of the off time period and due to the primary
controller running in critical conduction mode; the flux in
the transformer is null, so the peak will start from zero to
reach the nominal value.
Figure 44 illustrates the driver synchronization in
soft−start sequence.
The new patented soft−start is based on the flux
transformer reconstruction concept with leading edge mode
control during a startup sequence only.
A startup sequence can be arisen with the 3 following
cases:
1. The power supply unit is just plug on the main
supply, in this case there is a general startup.
2. The power supply unit is running but one or the
both outputs are disabled, thus by enabling the
output a new startup happened.
3. The power supply unit is running but the
secondary controller is in standby mode (STBY
pin grounded), when the standby mode is left, a
startup sequence happen if at least one of the
outputs is enable.
Vsync
ON Time
OFF Time
t
0
Verror
VCt
t
0 Transfo Flux
EN voltage
t
0
DRV
t
0
ID2
t
0
Figure 44. Startup Sequence Illustrating the Leading Edge Mode Control
Due to the internal current source and the external
capacitor connected on enable pin (EN1 and EN2 pin); a
voltage ramp is generated that it fixes the soft−start time; by
playing with the capacitor value the soft−start time can be
adjusted to fit the application startup time.
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NCP4326
How Does the Enable Pin Work?
At the end of the soft−start mode (duration fixed by the
capacitor connected to enable pin) if the output voltage is not
entered in regulation then the duty cycle is fixed to 100%
until the output reaches the regulation.
If the soft−start mode takes a longer time than the time
needed to reach the regulation level, the controller enters in a
mixed mode. During the mixed mode the duty cycle is a mixed
of the soft−start mode duty cycle generation and the duty cycle
from the normal regulation. Thus the transition from the
soft−start mode and the normal operation is done smoothly
without discontinuity on the duty cycle (see Figure 45).
The enable pin cumulates two functions; it
enables/disables the driver and it generates the soft−start
time in leading edge mode control in order to control the
ramp up peak current during a startup sequence.
According the enable pin voltage level (VENX) there are
three modes:
1. DISABLE MODE: when VENx < VENX_TH1
2. SOFT−START MODE;
when VENX_TH1 < VENx < VENX_TH2
3. ENABLE MODE (or NORMAL OPERATION):
when VENX > VENX_TH2
Vsync
t
0
2ndary currents
t
0
PWM REG
t
0
PWM SS
t
0
DRV
Result
t
0
Soft Start Mode
Mixed Mode
Normal Mode
Figure 45. End of Startup Sequence Illustrating the Smooth Transition
from Soft−Start to Normal Mode via the Mixed Mode
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NCP4326
Flux Image Reconstruction
The RC network (Rint & Cint) connected to the negative
output winding does the integration of the voltage present on
this winding that it yields the flux image. Then the voltage
available on Flux pin is clamped between a low and high
level (respectively VFlux_L and VFlux_H) in order to ensure
a positive saw tooth on Flux pin. After that the voltage on
Flux pin is amplified 10 times and an offset is inserted to
ensure the disable function when the enable pin is below
VENX_TH1. More over the internal voltage clamp
(VENX_TH2 = 4.5 V) ending the soft−start duty cycle
generation when the voltage on enable pin is between
VENX_TH2 and VENX_max1.
Next the internal Flux image (label Int_Flux on Figure 46)
is compared with the enable pin voltage for generating the
soft−start duty cycle in leading edge mode control.
On enable pin we have an internal current source that it
charge the external capacitor and fix the soft−start time by
playing with the capacitor value. If the controller is placed
in standby mode then the enable capacitor is discharged by
the internal switch. The internal clamp limits the voltage
range on the enable pin.
With a primary controller working in critical conduction
mode the core flux inside the transformer is null at each
beginning primary switching cycle.
Measuring the flux means integrating the voltage present
on a transformer winding. But a simple integration yields a
saw tooth voltage waveform centered to zero volts. Thus this
saw tooth represents the flux variation in the transformer
core and must be offset in order to have a true image of the
flux with a minimum voltage close to zero volts.
What we need is a triangle with a FIXED lower level,
being equal to or somewhat above zero. This necessitates the
resetting of the integrator at the beginning of each primary
on−time. In practice, it means we quickly discharge the
integrator capacitor just before the primary on−time and
release this capacitor at the start of the primary on−time.
A negative auxiliary winding or a forward winding can be
used to build the flux image via a simple RC network, which
it ensures the integration then the NCP4326 fixes the lower
level.
Figure 46 shows how the flux image is built and used for
the soft−start sequence.
Q1
D1
T1
Pos Out
HV Rail
+
C1
GND
+
Primary
Controller
C2
Q2
Neg Out
D2
Rint
GND
Offset
Int_Flux
0V5
Clamp
Flux
+
1V 0V
−
−
Cint
GND
GND
R
4V5
PWM_SS
+
DRVx
9R
GND
VDD
PWM_REG
Normal_Reg
IENx
ENx_CMD
ENx
+
C_SS V
DD
5V0
Soft−Start Secondary Controller
GND GND
GND GND
Figure 46. Soft−Start Detailed Schematic View
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NCP4326
Soft−start experimental results are illustrated by the Figure 47.
Negative auxiliary
winding (20V/div)
DRV pin Signal
(10V/div)
Switch OFF
Switch ON
Enable pin voltage
(2V/div).
Int_Flux image
(2V/div) (built with
the math function :
Flux *10+0.5V)
Flux pin voltage
(0.5 V/div)
Figure 47. Soft−Start Duty Cycle Generation During the Startup Sequence
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NCP4326
The following Figure 48 show a real soft−start on a typical
application. The limited peak current during the soft−start
allows selecting smaller mosfet (for example SOT23
package without risk of exceeding the max non repetitive
peak current “IDM”).
In a startup sequence, the voltage output is null so the error
amplifier output is at its max value, so the duty cycle from
the PWM_reg signal is at 100% duty cycle. The duty cycle
is only limited by the soft−start feature: the switch ON is
done when the Int_Flux voltage is become lower than the
enable pin voltage and the switch OFF is done when the
Int_Flux is become higher than the enable pin voltage.
Soft start mode
on 1V8 output
Steady state
Normal reg.
Mixed Mode
1V8 output voltage
(0.5V/div)
Output peak current
in the power mosfet
(2A/div)
Figure 48. Startup Sequence with Soft−Start on 1V8 Output at Full Load
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NCP4326
Standby Pin Feature Description
When the standby pin is released the both drivers are kept
in OFF state during Tstby_off time to prevent any parasitic
switches on the driver before the internal power ON of the
controller is fully finished.
Practically the internal standby signal for the driver is
delayed and in the mean time the internal power waking up
is done.
The standby pin enables or disables the controller in order
to save some power when the power supply is in standby
mode. In standby mode all the internal power supplies and
references are shut down, except the VDD1 and the voltage
reference connected to the shunt regulator. The shunt
regulator bloc works during the standby mode for supplying
the feedback to the primary controller.
VDD1 VDD
VCC
VCC
UVLO
*VDD is not available in standby mode
**VDD1 is available all the time
Vcc OK
2V5
VOLTAGE
REFERENCE
VCC
1V25
SoftStart
VDD1
+
STBY
2V5
VCC
Vcc OK
VDD1
DRV1
STBY
DELAY
−
GND
GND
Figure 49. Standby Delay Definition
Synchronization Pin
The RC network (Rsync1 and Csync) filters the secondary
winding and Rsync2 limits the current through the internal
zener diode when the voltage exceeds the zener clamp level
or when the zener conduct in forward mode (when the
voltage winding is negative).
The NCP4326 needs to be synchronized with the primary
controller, a dedicated pin ensures this function just by
sensing a secondary winding voltage and filtering it.
VDD
NCP4326
ICt
Mag
Ct
Rsync1
VDD
Rsync2
Sync
−
+
Csync
Ct
1V6
4V0
GND
D1
GND
GND
Flyback transformer
Enable
GND GND
Figure 50. Synchronization Pin Wiring
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GND
NCP4326
Secondary winding
voltage (20V/div)
Sync pin voltage
(5V/div).
Ct pin voltage
(2V/div)
Figure 51. Soft−Start Duty Cycle Generation During the Startup Sequence.
Primary Feedback Regulation
During the primary on time, the secondary winding
voltage is equal to the input voltage multiplied by the
transformer turn ratio. At the primary switch on or the falling
edge on the secondary winding voltage, the Ct capacitor
voltage is reset to VCt_min and keeps it to this value as long
as the primary switch is in ON state. Then when the primary
ON time ends the Ct capacitor voltage is released, thus with
the internal current source on Ct pin, the voltage capacitor
rises linearly until a new primary switching cycle.
The NCP4326 integrates a precision reference voltage,
which together with a dedicated operational amplifier
reduces the feedback loop elements to the minimum. This
error operational amplifier with the reference voltage has
called the shunt regulator and offers the same behavior of a
traditional TL431 or TLV431.
8
NCP4326
9
VDD1
CPm
−
FBm
8
CPm
1V25
9
FBm
TLV431
+
GND
GND
Figure 52. Equivalent Schematic of the Shunt Regulator
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NCP4326
The operational amplifier is an open collector type that it
allows to sink the current from the opto−coupler from any
voltage source level.
VCC
D1
Figure 53 illustrates an example of a close loop feedback
connection from the secondary and the primary side.
L1
VOut
+
+
C1
C2
R33
1k
U5
Opto
Prim FB
GND
Primary
Controller
Q1
RFB_comp
CFB_comp
Rup
NCP4326
9
FBm
VDD1
8
−
CPm
Rdown
1V25
+
GND
GND
Figure 53. Primary Feedback Connection
Components Determination
So Vflux_pin should be lower or equal to 400 mV when
the power supply is in full load condition and at low line
input voltage.
Practically in case of universal input voltage range and
with a maximum output power to 16 W, a 10 nF capacitor is
selected and the resistor is adjusted to guaranteed a
maximum voltage on the flux to 400 mV at low line input
voltage. This gives a 22 k resistor.
RC Network on Flux Pin
The flux image can be obtained with a negative output or
with a forward configuration. The winding voltage
integration yields the flux image inside the transformer. This
integration will be done with a basic integrator.
The time constant of this integrator should be significantly
large compare to the maximum primary switching period.
For example the time constant can be 5−10 times larger.
Thus the resistor acts like a constant current source during
the period, so that the voltage across the capacitor rises and
falls linearly.
The internal flux signal (Int_Flux, see Figure 46) is
clamped to 4.5 volts in order to ensure a proper disable
soft−start function when the enable pin voltage is at its
maximum value (5.0 V).
For achieving a proper soft−start without any action from
the 4.5 V internal clamp, the maximum input voltage on flux
pin must be lower or equal to:
Ct Capacitor
This capacitor is used to create the saw tooth for achieving
the pulse width modulation (PWM) for the both secondary
outputs regulated by the NCP4326.
The capacitor value can be determined with the following
equation:
I + C V ´ C + I t , where I = ICt, ΔV =
t
V
(VCT_max1−VCT_min), Δt = primary off time (time during the
capacitor is charged).
The capacitor value is calculated in the worst condition:
• I = ICtmax = 700 A
• ΔV = (VCT_max1−VCT_min) = 4.0 − 1.6 = 2.4 V
• Δt = maximum primary off time in worst case condition
(Full load and low line input).
Vclamp * Voffset that yields 4.5 * 0.5
+ 0.4 V.
OpAmp_gain
10
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28
NCP4326
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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29
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
NCP4326
ON Semiconductor and
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NCP4326/D