MC100E241 5VECL 8-Bit Scannable Register Description The MC100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD and LOAD to be toggled with a single control line without the need for external gating. It also enables switching to scan mode with the single SHIFT control line. The eight inputs D0 − D7 accept parallel input data, while S-IN accepts serial input data when in shift mode. Data is accepted a set-up time before the positive-going edge of CLK; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero. The 100 Series contains temperature compensation. http://onsemi.com PLCC−28 FN SUFFIX CASE 776 Features • • • • • • • • • • • • • SHIFT overrides HOLD/LOAD Control 1000 ps Max. CLK to Q Asynchronous Master Reset Pin-Compatible with E141 PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 1 kV, Machine Model; > 75 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 529 devices Pb−Free Packages are Available* MARKING DIAGRAM* 1 28 MC100E241FNG AWLYYWW A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 3 1 Publication Order Number: MC100E241/D MC100E241 SEL0 NC SEL1 26 CLK 25 24 D7 D6 D5 VCCO Q7 23 22 21 20 19 S-IN 18 Q6 27 17 Q5 MR 28 16 VCC VEE 1 15 NC S-IN 2 14 VCCO D0 3 13 Q4 D1 4 12 Q3 Pinout: 28-Lead PLCC (Top View) D0 D1 − D6 1 1 D Q 0 0 R 1 1 D Q 0 0 R 1 1 D Q 0 0 R Q0 Q1 − Q6 BITS 1−6 5 6 7 8 9 10 11 D7 D2 D3 D4 VCCO Q0 Q1 Q2 HOLD/LOAD SHIFT CLK * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. MR Figure 2. Logic Diagram Figure 1. Pinout Assignment Table 1. PIN DESCRIPTION PIN FUNCTION D0 − D7 ECL Parallel Date Inputs S-IN ECL Serial Data Inputs SEL0 ECL SHIFT Control SEL1 ECL HOLD/LOAD Control CLK ECL Clock MR ECL Master Reset Q0 − Q7 ECL Data Outputs VCC, VCCO Positive Supply VEE Negative Supply NC No Connect Table 2. FUNCTION TABLE MR SEL0 SEL1 Function 1 X X Outputs LOW 0 1 X Shift Data 0 0 1 Hold Data 0 0 0 Load Data X = Don’t Care http://onsemi.com 2 Q7 MC100E241 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm PLCC−28 PLCC−28 63.5 43.5 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W Tsol Wave Solder 265 265 °C VI v VCC VI w VEE Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V, VEE = 0.0 V (Note 1) 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 125 150 125 150 144 173 mA VOH Output HIGH Voltage (Note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV VIH Input HIGH Voltage 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV VIL Input LOW Voltage 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.3 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. Table 5. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 3) 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 125 150 125 150 144 173 mA VOH Output HIGH Voltage −1025 −950 −880 −1025 −950 −880 −1025 −950 −880 mV VOL Output LOW Voltage −1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 0.3 150 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. http://onsemi.com 3 MC100E241 Table 6. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 5) 0°C Symbol fMAX Maximum Toggle Frequency fSHIFT Max. Shift Frequency tPLH Propagation Delay to Output th Typ Max Min 900 700 tPHL ts Min Characteristic 25°C Typ 85°C Max Min 900 900 700 900 700 Typ Max Unit 900 GHz 900 MHz ps CLK 625 750 975 625 750 975 625 750 975 MR 600 725 975 600 725 975 600 725 975 Setup Time ps D 175 25 175 25 175 25 SEL0 (SHIFT) 350 200 350 200 350 200 SEL1 (HOLD/LOAD) 400 250 400 250 400 250 S-IN 125 −100 125 −100 125 −100 D 200 −25 200 −25 200 −25 SEL0 (SHIFT) 100 −200 100 −200 100 −200 SEL1 (HOLD/LOAD) 50 −250 50 −250 50 −250 S-IN 300 100 300 100 300 100 900 600 900 600 900 600 Hold Time ps tRR Reset Recovery Time tPW Minimum Pulse Width ps ps CLK, MR 400 400 400 tSKEW Within-Device Skew (Note 6) 60 60 60 ps tJITTER Random Clock Jitter (RMS) <1 <1 <1 ps tr Rise/Fall Times tf (20 - 80%) ps 300 525 800 300 525 800 300 525 800 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. 100 Series: VEE can vary −0.46 V / +0.8 V. 6. Within-device skew is defined as identical transitions on similar paths through a device. http://onsemi.com 4 MC100E241 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† MC100E241FN PLCC−28 37 Units / Rail MC100E241FNG PLCC−28 (Pb−Free) 37 Units / Rail MC100E241FNR2 PLCC−28 500 / Tape & Reel MC100E241FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 5 MC100E241 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE E −N− 0.007 (0.180) B Y BRK M T L−M 0.007 (0.180) U M N S T L−M S S N S D Z −M− −L− W 28 D X V 1 A 0.007 (0.180) R 0.007 (0.180) C M M T L−M T L−M S S N N S 0.007 (0.180) H N S S G J T L−M S N T L−M N S S K1 0.004 (0.100) −T− SEATING K PLANE F VIEW S G1 M S E S T L−M S VIEW D−D Z 0.010 (0.250) 0.010 (0.250) G1 VIEW S S NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10_ 0.410 0.430 0.040 −−− http://onsemi.com 6 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10_ 10.42 10.92 1.02 −−− 0.007 (0.180) M T L−M S N S MC100E241 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10E241/D