EMLSI EM7164SU16W-45L 1m x 16 bit single transistor ram Datasheet

Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
Document Title
1M x 16 bit Single Transistor RAM
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
Jun. 07 , 2005
Preliminary
0.1
2’nd Draft
Add net die and pad coordinates
Emerging Memory & Logic Solutions Inc.
Aug. 22 , 2005
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-717
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
1M x16 bit Single Transistor RAM
GENERAL DESCRIPTION
The EM7164SU16 is 16,777,216 bits of Single Transistor RAM which uses DRAM type memory cells, but
this device has refresh-free operation and extreme low power consumption technology. Furthermore the
interface is compatible to a low power Asynchronous type SRAM. The EM7164SU16 is organized as
1,048,576 Words x 16 bit.
FEATURES
- Organization :1M x16
- Power Supply Voltage : 2.7 ~ 3.3V
- Separated I/O power(VccQ) & Core power(Vcc)
- Three state outputs
- Byte read/write control by UB/LB
- Support Direct Deep Power Down control by ZZ and Auto TCSR for power saving
PRODUCT FAMILY
Part Number
EM7164SU16W
Operating Temp.
-25oC to 85oC
Power Supply
2.7V to 3.3V
Speed
(tRC)
70ns
Power Dissipation
Standby
(ISB1, Max.)
Operating
(ICC2, Max.)
80uA
FUNCTION BLOCK DIAGRAM
/ZZ
/CS
/UB
/LB
/WE
/OE
CONTROL
LOGIC
A0~A19
ADDRESS
DECODER
DQ0~
DQ15
Self-Refresh
CONTROL
ROW SELECT
COLUMN SELECT
Memory Array
1M X 16
Din/Dout BUFFER
I/O CIRCUIT
2
25mA
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
1M x16 bit Single Transistor RAM
GENERAL WAFER SPECIFICATIONS
1
60
- Process Technology : 0.13um CMOS Deep trench process
- 3 Metal layers including local inter-connection
- Wafer thickness : 725 +/- 25um
- Minimum Pad Pitch : 100um
- Wafer diameter : 8-inch
PAD DESCRIPTION
+
30
y
x
DEVICE CODE
(EM716XSU16)
31 32
Name
(0.0)
3
Function
Name
Function
/CS
Chip select inputs
/LB
Lower byte (DQ0~7)
/OE
Output enable input
/UB
Upper byte (DQ8~15)
/WE
Write enable input
VCC
Power supply
/ZZ
Low Power Control
VCCQ
I/O Power supply
DQ0-15 Data In-out
VSS(Q) Ground
A0-19
NC
Address inputs
No connection
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
ABSOLUTE MAXIMUM RATINGS 1)
Parameter
Symbol
Ratings
Unit
Voltage on Any Pin Relative to Vss
VIN, VOUT
-0.2 to VCCQ+0.3V
V
Voltage on Vcc supply relative to Vss
VCC, VCCQ
-0.22) to 3.6V
V
Power Dissipation
Storage Temperature
Operating Temperature
PD
1.0
W
TSTG
-65 to 150
oC
TA
-25 to 85
oC
1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Undershoot at power-off : -1.0V in case of pulse width < 20ns
FUNCTIONAL DESCRIPTION
CS
ZZ
OE
WE
LB
UB
DQ0~7
DQ8~15
Mode
Power
H
H
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
L
X
X
X
X
High-Z
High-Z
Deselected
Deep Power Down
X
H
X
X
H
H
High-Z
High-Z
Deselected
Stand by
L
H
H
H
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Data Out
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L
H
L
H
L
L
Data Out
Data Out
Word Read
Active
L
H
X
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
H
X
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
H
X
L
L
L
Data In
Data In
Word Write
Active
Note: X means don’t care. (Must be low or high state)
4
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Symbol
Min
Typ
Max
Unit
VCC
2.7
3.0
3.3
V
VCCQ
2.7
3.0
3.3
V
VSS, VSSQ
0
0
0
V
Input high voltage
VIH
0.8 * VCCQ
-
VCCQ + 0.22)
V
Input low voltage
VIL
-
0.2 * VCCQ
V
Supply voltage
Ground
1.
2.
3.
4.
-0.23)
TA= -25 to 85oC, otherwise specified
Overshoot: VCC +1.0 V in case of pulse width < 20ns
Undershoot: -1.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
8
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=VSS to VCCQ , VCC=VCCmax
-1
-
1
uA
Output leakage current
ILO
CS=VIH , /ZZ=VIH , OE=VIH or WE=VIL ,
VIO=VSS to VCCQ , VCC=VCCmax
-1
-
1
uA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA,
CS<0.2V, ZZ=VIH , VIN<0.2V or VIN>VCCQ-0.2V
-
-
3
mA
ICC2
Cycle time = Min, IIO=0mA, 100% duty,
CS=VIL, ZZ=VIH, VIN=VIL or VIH
-
-
25
mA
Output low voltage
VOL
IOL = 0.5mA, VCC=VCCmin
-
-
0.2*VCCQ
V
Output high voltage
VOH
IOH = -0.5mA, VCC=VCCmin
0.8*VCCQ
-
-
V
Standby Current (CMOS)
ISB1
-
-
80
uA
Average operating current
CS,ZZ>VCCQ-0.2V, Other inputs = 0 ~ VCCQ
(Typ. condition : VCC=3.0V @ 25oC)
(Max. condition : VCC=3.3V @ 85oC)
1. Maximum Icc specifications are tested with VCC = VCCmax.
5
LL
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Dout
Input Pulse Level : 0.2V to VCCQ-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : VCCQ/2
CL1)
1)
Output Load (See right) : CL = 30pF
1. Including scope and Jig capacitance
AC CHARACTERISTICS (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = -25C to +85oC)
Symbol
Parameter List
Read
Write
Speed
Min
Max
Unit
Read Cycle Time
tRC
70
40k
ns
Address access time
tAA
-
70
ns
Chip enable to data output
tCO
-
70
ns
Output enable to valid output
tOE
-
25
ns
UB, LB enable to data output
tBA
-
70
ns
Chip enable to low-Z output
tLZ
10
-
ns
UB, LB enable to low-Z output
tBLZ
10
-
ns
Output enable to low-Z output
tOLZ
5
-
ns
Chip disable to high-Z output
tHZ
0
15
ns
UB, LB disable to high-Z output
tBHZ
0
15
ns
Output disable to high-Z output
tOHZ
0
15
ns
Output hold from Address change
tOH
5
-
ns
Write Cycle Time
tWC
70
40k
ns
Chip enable to end of write
tCW
60
-
ns
Address setup time
tAS
0
-
ns
Address valid to end of write
tAW
60
-
ns
UB, LB valid to end of write
tBW
60
-
ns
Write pulse width
tWP
50
-
ns
Write recovery time
tWR
0
-
ns
Write to output high-Z
tWHZ
0
15
ns
Data to write time overlap
tDW
20
-
ns
Data hold from write time
tDH
0
-
ns
End write to output low-Z
tOW
5
-
ns
6
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
TIMING DIAGRAMS
READ CYCLE (1) (Address controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
READ CYCLE (2) (ZZ=WE=VIH)
tRC
Address
tAA
CS
tOH
tCO
tHZ
tBA
LB, UB
tBHZ
tOE
OE
Data Out
High-Z
tOHZ
tOLZ
Data Vaild
tBLZ
tLZ
NOTES (READ CYCLE)
1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. Do not Access device with cycle timing shorter than tRC for continuous periods > 40us.
7
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
WRITE CYCLE (1) (WE controlled, ZZ=OE=VIH)
tWC
Address
tAW
tCW
CS
tBW
LB, UB
WE
tAS
Data In
tWR
tWP
tDW
High-Z
tDH
Data Valid
tWHZ
Data Out
tOW
Data Undefined
WRITE CYCLE (2) (CS controlled, ZZ=OE=VIH)
tWC
Address
tAS
CS
tWR
tCW
tAW
LB, UB
tBW
WE
tWP
tDW
Data In
Data Out
Data Valid
High-Z
8
tDH
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
WRITE CYCLE (3) (UB, LB controlled, ZZ=OE=VIH)
tWC
Address
tWR
tCW
CS
tAW
LB, UB
tAS
tBW
tWP
WE
tDW
Data In
Data Out
tDH
Data Valid
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS, low WE and low UB or LB. A write begins at the last transition
among low CS and low WE with asserting UB or LB low for single byte operation or simultaneously asserting
UB and LB low for word operation. A write ends at the earliest transition among high CS and high WE.
The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from CS going low to end od write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE
going high.
5. Do not Access device with cycle timing shorter than tWC for continuous periods > 40us.
9
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
LOW POWER MODES
~
~~
~
Deep Power Down Mode Entry/Exit
CS
tZZCS
tCSZZ
tZZP
~
~
ZZ
Deep Power Down Entry
tR
Normal
operation
Deep Power Down Exit
NOTES ( DEEP POWER DOWN )
During Deep Power Down mode, all referesh related activity are disabled.
Parameter
Description
Min.
Max.
Units
tZZCS
ZZ low to CS low
0
-
ns
tCSZZ
CS high to ZZ high
0
-
ns
tR
Operation Recovery Time
200
-
us
tZZP
ZZ pulse width
20
-
ns
Low Power Mode Characteristics
Parameter
Symbol
Deep Power Down
Current
IZZ
Test Conditions
ZZ < 0.2V, Other inputs = 0 ~ VCCQ
(Max. condition : VCC=3.3V @ 85oC)
10
Min
Typ
Max
Unit
-
-
10
uA
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
TIMING WAVEFORM OF POWER UP
200us
VCC(Min.)
VCC
CS
Power Up Mode
Normal Operation
NOTE . ( POWER UP )
1. After Vcc reaches Vcc(Min.) , wait 200us with CS high. Then you get into the normal operation.
11
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
11. Power
2. Device Type
10. Speed
3. Density
4. Option
9. Packages
5. Technology
8. Version
6. Operating Voltage
7. Organization
1. Memory Component
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
8. Version
Blank ----------------- Mother die
A ----------------------- First version
B ----------------------- Second version
C ----------------------- Third version
D ----------------------- Fourth version
E ----------------------- Fifth version
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- Package
W --------------------- Wafer
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
2 ----------------------- Multiplexed
3----------------------- Single CS with /ZZ
4----------------------- Single CS with /ZZ
for Direct DPD mode
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ----------------- CMOS
F ------------------------ Full CMOS
S ------------------------ Single Transistor
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free)
L ---------------------- Low Power
S ---------------------- Standard Power
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
O ------------------------- 1.5V
12
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