SA572 Programmable Analog Compandor The SA572 is a dual-channel, high-performance gain control circuit in which either channel may be used for dynamic range compression or expansion. Each channel has a full-wave rectifier to detect the average value of input signal, a linearized, temperaturecompensated variable gain cell (G) and a dynamic time constant buffer. The buffer permits independent control of dynamic attack and recovery time with minimum external components and improved low frequency gain control ripple distortion over previous compandors. The SA572 is intended for noise reduction in high-performance audio systems. It can also be used in a wide range of communication systems and video recording applications. http://onsemi.com MARKING DIAGRAMS 16 16 Features • Independent Control of Attack and Recovery Time • Improved Low Frequency Gain Control Ripple • Complementary Gain Compression and Expansion with • • • • • • • 1 16 External Op Amp Wide Dynamic Range − Greater than 110 dB Temperature-Compensated Gain Control Low Distortion Gain Cell Low Noise − 6.0 V Typical Wide Supply Voltage Range − 6.0 V-22 V System Level Adjustable with External Components Pb−Free Packages are Available* SA572N AWLYYWWG 16 1 PDIP−16 N SUFFIX CASE 648 1 16 SA 572 ALYW G G 16 1 TSSOP−16 DTB SUFFIX CASE 948F Applications • • • • • • • SA572D AWLYYWWG 1 SOIC−16 WB D SUFFIX CASE 751G Dynamic Noise Reduction System Voltage Control Amplifier Stereo Expandor Automatic Level Control High-Level Limiter Low-Level Noise Gate State Variable Filter 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS D, N, DTB Packages* TRACK TRIM A 1 16 RECOV. CAP A 2 15 TRACK TRIM B RECT. IN A 3 14 RECOV. CAP B ATTACK CAP A 4 G OUT A 5 THD TRIM A 6 G IN A 7 GND 8 VCC 13 RECT. IN B 12 ATTACK CAP B 11 G OUT B 10 THD TRIM B 9 G IN B *D package released in large SO (SOL) package only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 2 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Publication Order Number: SA572/D SA572 R1 (7,9) (5,11) 6.8k G (6,10) 500 Ω GAIN CELL (1,15) − − (3,13) + + 270 (16) 10k RECTIFIER Ω BUFFER 10k P.S. (8) (4,12) (2,14) Figure 1. Block Diagram PIN FUNCTION DESCRIPTION Pin Symbol Description 1 TRACK TRIM A Tracking Trim A 2 RECOV. CAP A Recovery Capacitor A 3 RECT. IN A 4 ATTACK CAP A 5 G OUT A 6 THD TRIM A 7 G IN A 8 GND 9 G IN B 10 THD TRIM B 11 G OUT B 12 ATTACK CAP B Rectifier A Input Attack Capacitor A Variable Gain Cell A Output Total Harmonic Distortion Trim A Variable Gain Cell A Input Ground Variable Gain Cell B Input Total Harmonic Distortion Trim B Variable Gain Cell B Output Attack Capacitor B 13 RECT. IN B 14 RECOV. CAP B Rectifier B Input Recovery Capacitor B 15 TRACK TRIM B Tracking Trim B 16 VCC Positive Power Supply http://onsemi.com 2 SA572 MAXIMUM RATINGS Rating Symbol Value Unit VCC 22 VDC Operating Temperature Range TA −40 to +85 °C Operating Junction Temperature TJ 150 °C PD 500 mW RJA 75 105 133 °C/W Supply Voltage Power Dissipation Thermal Resistance, Junction−to−Ambient N Package D Package DTB Package Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. DC ELECTRICAL CHARACTERISTICS Standard test conditions, VCC = 15 V, TA = 25°C; Expandor mode (see Test Circuit). Input signals at unity gain level (0 dB) = 100 mVRMS at 1.0 kHz; V1 = V2; R2 = 3.3 k; R3 = 17.3 k unless otherwise noted. Characteristic Symbol Test Conditions Min Typ Max Unit Supply Voltage VCC − 6.0 − 22 VDC Supply Current ICC No Signal − − 6.3 mA Internal Voltage Reference VR − 2.3 2.5 2.7 VDC THD THD THD 1.0 kHz, CA = 1.0 F 1.0 kHz, CR = 10 F 100 Hz − − − 0.2 0.05 0.25 1.0 − − % % % No Signal Output Noise Input to V1 and V2 grounded (20−20 kHz) − 6.0 25 V DC Level Shift (Untrimmed) Input change from no signal to 100 mVRMS − "20 "50 mV Total Harmonic Distortion (Untrimmed) Total Harmonic Distortion (Trimmed) Total Harmonic Distortion (Trimmed) Unity Gain Level Large-Signal Distortion Tracking Error (Measured relative to value at unity gain) = [VO−VO (unity gain)] dB−V2dB Channel Crosstalk Power Supply Rejection Ratio − −1.5 0 +1.5 dB V1 = V2 = 400 mV − 0.7 3.0 % Rectifier Input V2 = +6.0 dB, V1 = 0 dB V2 = −30 dB, V1 = 0 dB − − "0.2 "0.5 −2.5, +1.6 dB dB 200 mVRMS into channel A, measured output on channel B 60 − − dB 120 Hz − 70 − dB PSRR 100 1F 2.2F (7,9) V1 6.8k G (5,11) −15V 22F 17.3k 82k 5 + 1% R3 − 270pF (2,14) BUFFER (4,12) NE5234 2.2k (6,10) CR = 10F 1k V0 + + 2.2F (8) CA = 1F (1,15) 2.2F V2 3.3k (3,13) R2 1% RECTIFIER +15V (16) 0.1F Figure 2. Test Circuit http://onsemi.com 3 + 22F SA572 Audio Signal Processing IC Combines VCA and Fast Attack/Slow Recovery Level Sensor In high-performance audio gain control applications, it is desirable to independently control the attack and recovery time of the gain control signal. This is true, for example, in compandor applications for noise reduction. In high end systems the input signal is usually split into two or more frequency bands to optimize the dynamic behavior for each band. This reduces low frequency distortion due to control signal ripple, phase distortion, high frequency channel overload and noise modulation. Because of the expense in hardware, multiple band signal processing up to now was limited to professional audio applications. With the introduction of the SA572 this highperformance noise reduction concept becomes feasible for consumer hi fi applications. The SA572 is a dual channel gain control IC. Each channel has a linearized, temperature-compensated gain cell and an improved level sensor. In conjunction with an external low noise op amp for current-to-voltage conversion, the VCA features low distortion, low noise and wide dynamic range. The novel level sensor which provides gain control current for the VCA gives lower gain control ripple and independent control of fast attack, slow recovery dynamic response. An attack capacitor CA with an internal 10 k resistor RA defines the attack time A. The recovery time R of a tone burst is defined by a recovery capacitor CR and an internal 10 k resistor RR. Typical attack time of 4.0 ms for the high-frequency spectrum and 40 ms for the low frequency band can be obtained with 0.1 F and 1.0 F attack capacitors, respectively. Recovery time of 200 ms can be obtained with a 4.7 F recovery capacitor for a 100 Hz signal, the third harmonic distortion is improved by more than 10 dB over the simple RC ripple filter with a single 1.0 F attack and recovery capacitor, while the attack time remains the same. The SA572 is assembled in a standard 16-pin dual in-line plastic package and in oversized SOL package. It operates over a wide supply range from 6.0 V to 22 V. Supply current is less than 6.0 mA. The SA572 is designed for applications from −40°C to +85°C. BASIC APPLICATIONS Description The SA572 consists of two linearized, temperaturecompensated gain cells (G), each with a full-wave rectifier and a buffer amplifier as shown in the block diagram. The two channels share a 2.5 V common bias reference derived from the power supply but otherwise operate independently. Because of inherent low distortion, low noise and the capability to linearize large signals, a wide dynamic range can be obtained. The buffer amplifiers are provided to permit control of attack time and recovery time independent of each other. Partitioned as shown in the block diagram, the IC allows flexibility in the design of system levels that optimize DC shift, ripple distortion, tracking accuracy and noise floor for a wide range of application requirements. VTI n + BE Ǔ ) 12 IO * VTIn IS ǒI )I I Ǔ 1 IN S * V TIn ǒ Ǔ ǒ Ǔ 1I *1I 2 G 2 O IS (eq. 1) I2 * I1 * IIN IS V IN R1 R1 = 6.8 k I1 = 140 A I2 = 280 A where IIN + IO is the differential output current of the gain cell and IG is the gain control current of the gain cell. If all transistors Q1 through Q4 are of the same size, equation 1 can be simplified to: Figure 3 shows the circuit configuration of the gain cell. Bases of the differential pairs Q1-Q2 and Q3-Q4 are both tied to the output and inputs of OPA A1. The negative feedback through Q1 holds the VBE of Q1-Q2 and the VBE of Q3-Q4 equal. The following relationship can be derived from the transistor model equation in the forward active region. Q3Q4 1 I 2 G + V TIn Gain Cell VBE ǒ IO + 2 @ I IN @ I G * 1 ǒI 2 * 2I 1Ǔ @ I G I2 I2 (eq. 2) The first term of equation 2 shows the multiplier relationship of a linearized two quadrant transconductance amplifier. The second term is the gain control feedthrough due to the mismatch of devices. In the design, this has been minimized by large matched devices and careful layout. Offset voltage is caused by the device mismatch and it leads to even harmonic distortion. The offset voltage can be trimmed out by feeding a current source within "25 A into the THD trim pin. Q1Q2 (VBE = VT IIN IC/IS) http://onsemi.com 4 SA572 is only 6.0 V in the audio spectrum (10 Hz-20 kHz). The output current IO must feed the virtual ground input of an operational amplifier with a resistor from output to inverting input. The non-inverting input of the operational amplifier has to be biased at VREF if the output current IO is DC coupled. The residual distortion is third harmonic distortion and is caused by gain control ripple. In a compandor system, available control of fast attack and slow recovery improve ripple distortion significantly. At the unity gain level of 100 mV, the gain cell gives THD (total harmonic distortion) of 0.17% typ. Output noise with no input signals V+ 1 1 I ) I 2 G 2 O I1 140A A1 IO − + Q4 Q3 Q1 Q2 R1 6.8k I2 280A IG VREF THD TRIM VIN Figure 3. Basic Gain Cell Schematic Rectifier V+ The rectifier is a full-wave design as shown in Figure 4. The input voltage is converted to current through the input resistor R2 and turns on either Q5 or Q6 depending on the signal polarity. Deadband of the voltage to current converter is reduced by the loop gain of the gain block A2. If AC coupling is used, the rectifier error comes only from input bias current of gain block A2. The input bias current is typically about 70 nA. Frequency response of the gain block A2 also causes second-order error at high frequency. The collector current of Q6 is mirrored and summed at the collector of Q5 to form the full wave rectified output current IR. The rectifier transfer function is: IR + V IN * V REF R2 VREF R + V IN * V REF + A2 − Q5 D7 Q6 (eq. 3) R2 VIN If VIN is AC-coupled, then the equation will be reduced to: IRAC + I V IN(AVG) R2 The internal bias scheme limits the maximum output current IR to be around 300 A. Within a "1.0 dB error band the input range of the rectifier is about 52 dB. Figure 4. Simplified Rectifier Schematic http://onsemi.com 5 R2 SA572 Buffer Amplifier *t Ga(t) + (Ga INT * Ga FNL) e A ) Ga FNL In audio systems, it is desirable to have fast attack time and slow recovery time for a tone burst input. The fast attack time reduces transient channel overload but also causes low-frequency ripple distortion. The low-frequency ripple distortion can be improved with the slow recovery time. If different attack times are implemented in corresponding frequency spectrums in a split band audio system, high quality performance can be achieved. The buffer amplifier is designed to make this feature available with minimum external components. Referring to Figure 5, the rectifier output current is mirrored into the input and output of the unipolar buffer amplifier A3 through Q8, Q9 and Q10. Diodes D11 and D12 improve tracking accuracy and provide common-mode bias for A3. For a positive-going input signal, the buffer amplifier acts like a voltage-follower. Therefore, the output impedance of A3 makes the contribution of capacitor CR to attack time insignificant. Neglecting diode impedance, the gain Ga(t) for G can be expressed as follows: GaINT = Initial Gain GaFNL = Final Gain A = RA • CA = 10 k • CA where A is the attack time constant and RA is a 10 k internal resistor. Diode D15 opens the feedback loop of A3 for a negative-going signal if the value of capacitor CR is larger than capacitor CA. The recovery time depends only on CR • RR. If the diode impedance is assumed negligible, the dynamic gain GR (t) for G is expressed as follows: *t GR(t) + (G RINT * G RFNL) e R ) GRFNL *t GR(t) + (G RINT * G RFNL) e R ) GRFNL R = RR • CR = 10 k • CR where R is the recovery time constant and RR is a 10 k internal resistor. The gain control current is mirrored to the gain cell through Q14. The low level gain errors due to input bias current of A2 and A3 can be trimmed through the tracking trim pin into A3 with a current source of "3.0 A. V+ Q8 Q9 Q10 IQ = 2IR2 Q17 IR2 I R + X2 Q16 10k V IN R − D15 D13 A3 + 10k IR1 D11 CA Q14 D12 TRACKING TRIM CR Figure 5. Buffer Amplifier Schematic http://onsemi.com 6 X2 Q18 SA572 Basic Expandor buffer A1 may be necessary if the input is voltage driven with large source impedance. The gain cell output current feeds the summing node of the external OPA A2. R3 and A2 convert the gain cell output current to the output voltage. In high-performance applications, A2 has to be low-noise, high-speed and wide band so that the high-performance output of the gain cell will not be degraded. The non-inverting input of A2 can be biased at the low noise internal reference Pin 6 or 10. Resistor R4 is used to bias up the output DC level of A2 for maximum swing. The output DC level of A2 is given by: Figure 6 shows an application of the circuit as a simple expandor. The gain expression of the system is given by: VOUT + V IN ǒ Ǔ 2 2 @ R 3 @ V IN(AVG) I1 R2 @ R1 (eq. 4) (I1 = 140 A) Both the resistors R1 and R2 are tied to internal summing nodes. R1 is a 6.8 k internal resistor. The maximum input current into the gain cell can be as large as 140 A. This corresponds to a voltage level of 140 A•6.8 k = 952 mV peak. The input peak current into the rectifier is limited to 300 A by the internal bias system. Note that the value of R1 can be increased to accommodate higher input level. R2 and R3 are external resistors. It is easy to adjust the ratio of R3/R2 for desirable system voltage and current levels. A small R2 results in higher gain control current and smaller static and dynamic tracking error. However, an impedance ǒ VOUT DC + V REF 1 ) R4 VIN CIN2 A1 CIN1 (7,9) 2.2F + R1 2.2F VREF (eq. 5) R3 VOUT A2 (6,10) R6 1k (4,12) BUFFER CIN3 2.2F R3 R4 17.3k (2,14) R5 100k B (5,11) G 6.8k Ǔ*V VB can be tied to a regulated power supply for a dual supply system and be grounded for a single supply system. CA sets the attack time constant and CR sets the recovery time constant. +VB − R3 R4 R2 3.3k C1 2.2F CA CR 1F 10F (3,13) (8) (16) +VCC Figure 6. Basic Expandor Schematic Basic Compressor RDC1, RDC2, and CDC form a DC feedback for A1. The output DC level of A1 is given by: Figure 7 shows the hook-up of the circuit as a compressor. The IC is put in the feedback loop of the OPA A1. The system gain expression is as follows: VOUT + V IN ǒ Ǔ I1 R2 @ R1 @ 2 R 3 @ V IN(AVG) 1 2 ǒ R *V @ǒ VOUT DC + V REF 1 ) (eq. 6) B DC1 R DC1 ) R DC2 R4 ) RDC2 R4 Ǔ Ǔ (eq. 7) The zener diodes D1 and D2 are used for channel overload protection. (I1 = 140 A) http://onsemi.com 7 SA572 RDC1 R4 RDC2 9.1k 9.1k CDC 10F C2 .1F CIN1 D1 2.2F VIN D2 − R3 17.3k VOUT A1 + C1 1k R5 (6,10) VREF R1 G (7,9) 6.8k CIN2 2.2F (5,11) (2,14) (4,12) CR 10F CIN3 2.2F BUFFER CA 1F 3.3k R2 (3,13) (8) VCC (16) Figure 7. Basic Compressor Schematic Basic Compandor System pre-emphasis, de-emphasis and equalization are easy to incorporate. The IC is a versatile functional block to achieve a high performance audio system. Figure 8 shows the system level diagram for reference. The above basic compressor and expandor can be applied to systems such as tape/disc noise reduction, digital audio, bucket brigade delay lines. Additional system design techniques such as bandlimiting, band splitting, 1 2 VRMS 2 REL LEVEL COMPRESSION IN EXPANDOR OUT dB ABS LEVEL dBM 3.0 V +29.54 +11.76 547.6 mV 400 mV +14.77 +12.0 −3.00 −5.78 100 mV 0.0 −17.78 10 mV −20 −37.78 1 mV −40 −57.78 100 V −60 −77.78 −80 −97.78 10 V Figure 8. SA572 System Level http://onsemi.com 8 SA572 C1 R1 + 2.2 F 3, 13 3.3k RX ATTACK CAP CA + 4, 12 BUFFER 1 F CR 5, 11 C3 VIN + 2.2 F R4 RDC1 100k 9.1k R3 17.3k 2 7, 9 R2 C2 + 10 F + 2.2 F RDC2 + 9.1k CDC 10 F V+ R5 TO THD TRIM PIN OF 572 PINS 6, 10 6.8k G RECOVERY CAP 2, 14 3 1k C5 + 22 F − 1 VOUT DC 5532 + VOUT 2.2 F + V− Figure 9. Automatic Level Control Automatic Level Control (ALC) The output level is calculated using the following equation: In the ALC configuration, the variable gain cell is placed in the feedback loop of the operational amplifier and the rectifier is connected to the input. As the input amplitude increases above the crossover point, the overall system gain decreases proportionally, holding the output amplitude constant. As the input amplitude decreases below the crossover point, the overall system gain increases proportionally, holding the output amplitude at the same constant level. Gain + where: VOUT_LEVEL + where: R1 R2 I1 2 R3 VIN(avg) where: DC1 R1 = 6.8 k (Internal) R2 = 3.3 k R3 = 17.3 k I1 = 140 A Note that for very low input levels, ALC may not be desired and to limit the maximum gain, resistor RX has been added. Gain max. + The output DC level can be set using the following equation: ǒ1 ) R ǒVINVIN(avg)Ǔ VIN + + 1.11 (for sine waves) VIN (avg) 2 Ǹ2 R1 = 6.8 k (Internal) R2 = 3.3 k R3 = 17.3 k I1 = 140 A VOUT DC + R1 R2 I1 2 R3 )RxǓ ǒRV1REF · R2 · IB 2 R3 Rx ^ ((desired max gain) Ǔ ) RDC2 V REF R4 R4 = 100 k RDC1 = RDC2 = 9.1 k VREF = 2.5 V http://onsemi.com 9 26 k) * 10 k SA572 ORDERING INFORMATION Description Package Temperature Range Shipping† SA572D Device 16−Pin Plastic Small Outline Package SO−16 WB −40 to +85°C 47 Units / Rail SA572DG 16−Pin Plastic Small Outline Package (Pb−Free) SO−16 WB −40 to +85°C 47 Units / Rail SA572DR2 16−Pin Plastic Small Outline Package SO−16 WB −40 to +85°C 1000 / Tape & Reel SA572DR2G 16−Pin Plastic Small Outline Package (Pb−Free) SO−16 WB −40 to +85°C 1000 / Tape & Reel SA572DTB 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C 96 Units / Rail SA572DTBG 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C 96 Units / Tube SA572DTBR2 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C 2500 / Tape & Reel SA572DTBR2G 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C 2500 / Tape & Reel SA572NG 16−Pin Plastic Dual In−Line Package PDIP−16 −40 to +85°C 25 Units / Rail SA572NG 16−Pin Plastic Dual In−Line Package (Pb−Free) PDIP−16 −40 to +85°C 25 Units / Rail †For information on / Tape and reel specifications, including part orientation and / Tape sizes, please refer to our / Tape and Reel Packaging Specification Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 10 SA572 PACKAGE DIMENSIONS SOIC−16 WB D SUFFIX CASE 751G−03 ISSUE C A D 9 1 8 h X 45_ E 0.25 8X M H B M 16 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. q 16X M 14X e B B T A B S S L A 0.25 MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ A1 SEATING PLANE C T PDIP−16 CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L S −T− H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 11 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SA572 PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÇÇÇ ÉÉ ÇÇÇ ÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D G H DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 12 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. SA572/D