MCNIX MX28F160C3TTC-70 16m-bit [1m x16] cmos single voltage 3v only flash memory Datasheet

MX28F160C3T/B
16M-BIT [1M x16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Bit Organization: 1,048,576 x 16
• Single power supply operation
- VCC=VCCQ=2.7~3.6V for read, erase and program
operation
- VPP=12V for fast production programming
- Operating temperature:-40° C~85° C
• Fast access time : 70/90/110ns
• Low power consumption
- 9mA typical active read current, f=5MHz
- 18mA typical program current (VPP=1.65~3.6V)
- 21mA typical erase current (VPP=1.65~3.6V)
- 7uA typical standby current under power saving
mode
• Sector architecture
- Sector structure : 4Kword x 2 (boot sectors), 4Kword
x 6 (parameter sectors), 32Kword x 31 (main sectors)
- Top/Bottom Boot
• Auto Erase and Auto Program
- Automatically program and verify data at specified
address
- Auto sector erase at specified sector
• Automatic Suspend Enhance
•
•
•
•
•
•
•
•
- Word write suspend to read
- Sector erase suspend to word write
- Sector erase suspend to read register report
Automatic sector erase, word write and sector lock/
unlock configuration
Status Reply
- Detection of program and erase operation completion.
- Command User Interface (CUI)
- Status Register (SR)
Data Protection Performance
- Include boot sectors and parameter and main sectors
to be locked/unlocked
100,000 minimum erase/program cycles
Common Flash Interface (CFI)
128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User-Programmable
Latch-up protected to 100mA from -1V to VCC+1V
Package type:
- 48-pin TSOP (12mm x 20mm)
- 48-ball CSP (8mm x 6mm)
fast as 70ns, allowing operation of high-speed microprocessors without wait states.
GENERAL DESCRIPTION
The MX28F160C3T/B is a 16-mega bit Flash memory
organized as 1M words of 16 bits. The 1M word of data
is arranged in eight 4Kword boot and parameter sectors,
and thirty-one 32K word main sectors which are individually erasable. MXIC's Flash memories offer the most
cost-effective and reliable read/write non-volatile random
access memory. The MX28F160C3T/B is packaged in
48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard
EPROM programmers.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX28F160C3T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
The standard MX28F160C3T/B offers access time as
P/N:PM0867
REV. 1.2, MAR. 17, 2004
1
MX28F160C3T/B
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cycling. The MX28F160C3T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
tially reduces active current when the device is in static
mode (addresses not switching). In this mode, the typical ICCS current is 7uA (CMOS) at 3.0V VCC.
As CE and RP are at VCC, ICC CMOS standby mode is
enabled. When RP is at GND, the reset mode is enabled
which minimize power consumption and provide data
write protection.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
A reset time (tPHQV) is required from RP switching high
until outputs are valid. Similarly, the device has a wake
time (tPHEL) from RP-high until writes to the CUI are
recognized. With RP at GND, the WSM is reset and the
status register is cleared.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to
the CUI initiates device automation. An internal Write
State Machine (WSM) automatically executes the algorithms and timings necessary for erase, word write and
sector lock/unlock configuration operations.
A sector erase operation erases one of the device's 32Kword sectors typically within 1.0s, 4K-word sectors typically within 0.5s independent of other sectors. Each sector can be independently erased minimum 100,000 times.
Sector erase suspend mode allows system software to
suspend sector erase to read or write data from any other
sector.
Writing memory data is performed in word increments of
the device's 32K-word sectors typically within 0.8s and
4K-word sectors typically within 0.1s. Word program suspend mode enables the system to read data or execute
code from any other memory array location.
MX28F160C3T/B features with individual sectors locking by using a combination of bits thirty-nine sector lockbits and WP, to lock and unlock sectors.
The status register indicates when the WSM's sector
erase, word program or lock configuration operation is
done.
The access time is 70/90/110ns (tELQV) over the operating temperature range (-40° C to +85° C) and VCC supply voltage range of 2.7V~3.6V.
MX28F160C3T/B's power saving mode feature substan-
REV. 1.2, MAR. 17, 2004
P/N:PM0867
2
MX28F160C3T/B
BLOCK DIAGRAM
DQ0-DQ15
Output
Buffer
Input
Buffer
VCC
Identifier
Register
CE
Data
Register
Output
Multiplexer
I/O
Logic
Status
Register
WE
Command
User
Interface
OE
RP
WP
Data
Comparator
A0~A19
Input
Buffer
Y
Decoder
Write
State
Machine
Y-Gating
Program/Erase
Voltage Switch
VPP
VCC
Main Sector 30
32K-Word
Main Sector
x31
Main Sector 29
Main Sector 1
Main Sector 0
X
Decoder
.......
Address
Latch
Boot Sector 0
Boot Sector 1
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
0
1
2
3
4
5
GND
Address
Counter
.......
REV. 1.2, MAR. 17, 2004
P/N:PM0867
3
MX28F160C3T/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RP
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX28F160C3T/B
A16
VCCQ
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48 Ball CSP (8mm x 6mm) Top View, Ball Down for MX28F160C3T/BXA
(Ball Pitch=0.75mm, Ball Width=0.35mm)
A1
A2
A3
A4
A13
A11
A8
VPP
B1
B2
B3
B4
A14
A10
WE
C1
C2
A15
A5
A6
A7
A8
A19
A7
A4
B5
B6
B7
B8
RP
A18
A17
A5
A2
C3
C4
C5
C6
C7
C8
A12
A9
NC
NC
A6
A3
A1
D1
D2
D3
D4
D5
D6
D7
D8
A16
DQ14
DQ5
DQ11
DQ8
CE
A0
E3
E4
E5
E6
E7
E8
DQ6
DQ12
DQ3
DQ9
DQ0
WP
6.0 mm
E1
VCCQ
E2
DQ15
DQ2
GND
F1
F2
F3
F4
F5
F6
F7
F8
GND
DQ7
DQ13
DQ4
VCC
DQ10
DQ1
OE
8.0 mm
REV. 1.2, MAR. 17, 2004
P/N:PM0867
4
MX28F160C3T/B
Table 1. Pin Description
Symbol
A0-A19
DQ0-DQ15
Type
input
input/output
CE
input
RP
input
WE
input
VPP
input/supply
OE
WP
input
input
VCC
VCCQ
GND
supply
input
supply
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
Data inputs/outputs: Inputs array data on the second CE and WE cycle during a program command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
Chip Enable : Activates the device's control logic, input buffers, and sense amplifiers.
CE high de-selects the memory device and reduce power consumption to standby
level. CE is active low.
Reset/Deep Power Down: when RP=VIL, the device is in reset/deep power down mode,
which drives the outputs to High Z, resets the WSM and minimizes current level.
When RP=VIH, the device is normal operation. When RP transitions from VIL to VIH,
the device defaults to the read array mode.
Write Enable: to control write to CUI and array sector. WE=VIL becomes active. The
data and addresses are latched on the rising edge of the second WE pulse.
Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V±5% for faster program and erase in a production environment.
Output enable: gates the device's outputs during a real cycle.
Write Protect: When WP is VIL, the sectors marked Lock Down can't be unlocked
through software. When WP is VIH, the lock down mechanism is disable and sectors
previously locked down are now locked and can be unlocked and locked through software. After WP goes low, any sectors previously marked lock down revert to that state.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers. (VCCQ must be tied to VCC)
Ground voltage: all the GND pin shall not be connected.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
5
MX28F160C3T/B
SECTOR STRUCTURE (TOP)
Sector
Boot Sector 0
Boot Sector 1
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
Sector Size
4K Word
4K Word
4K Word
4K Word
4K Word
4K Word
4K Word
4K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
Address Range (h)
FF000 ~ FFFFF
FE000 ~ FEFFF
FD000 ~ FDFFF
FC000 ~ FCFFF
FB000 ~ FBFFF
FA000 ~ FAFFF
F9000 ~ F9FFF
F8000 ~ F8FFF
F0000 ~ F7FFF
E8000 ~ EFFFF
E0000 ~ E7FFF
D8000 ~ DFFFF
D0000 ~ D7FFF
C8000 ~ CFFFF
C0000 ~ C7FFF
B8000 ~ BFFFF
B0000 ~ B7FFF
A8000 ~ AFFFF
A0000 ~ A7FFF
98000 ~ 9FFFF
90000 ~ 97FFF
88000 ~ 8FFFF
80000 ~ 87FFF
78000 ~ 7FFFF
70000 ~ 77FFF
68000 ~ 6FFFF
60000 ~ 67FFF
58000 ~ 5FFFF
50000 ~ 57FFF
48000 ~ 4FFFF
40000 ~ 47FFF
38000 ~ 3FFFF
30000 ~ 37FFF
28000 ~ 2FFFF
20000 ~ 27FFF
18000 ~ 1FFFF
10000 ~ 17FFF
08000 ~ 0FFFF
00000 ~ 07FFF
REV. 1.2, MAR. 17, 2004
P/N:PM0867
6
MX28F160C3T/B
SECTOR STRUCTURE (BOTTOM)
Sector
Boot Sector 0
Boot Sector 1
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
Sector Size
4K Word
4K Word
4K Word
4K Word
4K Word
4K Word
4K Word
4K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
32K Word
Address Range (h)
00000 ~ 00FFF
01000 ~ 01FFF
02000 ~ 02FFF
03000 ~ 03FFF
04000 ~ 04FFF
05000 ~ 05FFF
06000 ~ 06FFF
07000 ~ 07FFF
08000 ~ 0FFFF
10000 ~ 17FFF
18000 ~ 1FFFF
20000 ~ 27FFF
28000 ~ 2FFFF
30000 ~ 37FFF
38000 ~ 3FFFF
40000 ~ 47FFF
48000 ~ 4FFFF
50000 ~ 57FFF
58000 ~ 5FFFF
60000 ~ 67FFF
68000 ~ 6FFFF
70000 ~ 77FFF
78000 ~ 7FFFF
80000 ~ 87FFF
88000 ~ 8FFFF
90000 ~ 97FFF
98000 ~ 9FFFF
A0000 ~ A7FFF
A8000 ~ AFFFF
B0000 ~ B7FFF
B8000 ~ BFFFF
C0000 ~ C7FFF
C8000 ~ CFFFF
D0000 ~ D7FFF
D8000 ~ DFFFF
E0000 ~ E7FFF
E8000 ~ EFFFF
F0000 ~ F7FFF
F8000 ~ FFFFF
REV. 1.2, MAR. 17, 2004
P/N:PM0867
7
MX28F160C3T/B
2 PRINCIPLES OF OPERATION
3 BUS OPERATION
The product includes an on-chip WSM to manage sector erase, word write and lock-bit configuration functions.
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
After initial device power-up or return from reset mode
(see section on Bus Operations), the device defaults to
read array mode. Manipulation of external memory control pins allow array read, standby and output disable
operations.
3.1 Read
Information can be read from any sector, configuration
codes or status register independent of the VPP voltage. RP can be at VIH.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. All
functions associated with altering memory contents sector erase, word write, sector lock/unlock, status and
identifier codes - are accessed via the CUI and verified
through the status register.
The first task is to write the appropriate read mode command (Read Array, Read Configuration, Read Query or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from reset, the device automatically resets to read array mode. In order to read data,
control pins set for CE, OE, WE, RP and WP must be
driven to active. CE and OE must be active to obtain
data at the outputs. CE is the device selection control.
OE is the data output (DQ0-DQ15) control and active
drives the selected memory data onto the I/O bus, WE
must be VIH, RP must be VIH, WP must be at VIL or
VIH.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the sector erase, word write and
sector lock/unlock. The internal algorithms are regulated
by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Address is latched
at falling edge of CE and data latched at rising edge of
WE. Writing the appropriate command outputs array data,
accesses the identifier codes or outputs status register
data.
3.2 Output Disable
With OE at a logic-high level (VIH), the device outputs
are disabled. Output pins (DQ0-DQ15) are placed in a
high-impedance state.
Interface software that initiates and polls progress of
sector erase, word write and sector lock/unlock can be
stored in any sector. This code is copied to and executed
from system RAM during flash memory updates. After
successful completion, reads are again possible via the
Read Array command. Sector erase suspend allows
system software to suspend a sector erase to read/write
data from/to sectors other than that which is suspend.
Word write suspend allows system software to suspend
a word write to read data from any other flash memory
array location.
3.3 Standby
CE at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. DQ0~DQ15 outputs are placed in a highimpedance state independent of OE. If deselected during sector erase, word write or sector lock/unlock, the
device continues functioning, and consuming active
power until the operation completes.
With the mechanism of sector lock, memory contents
cannot be altered due to noise or unwanted operation.
When RP=VIH and VCC<VLKO (lockout voltage), any
data write alteration can be failure. During read operation, if write VPP voltage is below VPPLK, then hardware level data protection is achieved. With CUI's twostep command sequence sector erase, word write or
sector lock/unlock, software level data protection is
achieved also.
3.4 Reset
As RP=VIL, it initiates the reset mode. The device enters reset/deep power down mode. However, the data
stored in the memory has to be sustained at least 100ns
in the read mode before the device becomes deselected
REV. 1.2, MAR. 17, 2004
P/N:PM0867
8
MX28F160C3T/B
and output high impedance state.
mands require the command and address within the device or sector within the device (Sector Lock) to be
locked. The Clear Sector Lock-Bits command requires
the command and address within the device.
In read modes, RP-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP must be held low for a minimum of
100ns. Time tPHQV is required after return from reset
mode until initial memory access outputs are valid. After this wake-up interval tPHEL or tPHWL, normal operation is restored. The CUI is reset to read array mode
and status register is set to 80H. Sector lock bit is set at
lock status.
The CUI does not occupy an addressable memory location. It is written when WE and CE are active (whichever
goes high first). The address and data needed to execute a command are latched on the rising edge of WE
or CE. Standard microprocessor write timings are used.
During sector erase, word write or sector lock/unlock
modes, RP-low will abort the operation. Memory contents being altered are no longer valid; the data may be
partially erased or written.
In addition, CUI will go into either array read mode or
erase/write interrupted mode. When power is up and the
device reset subsequently, it is necessary to read status register in order to assure the status of the device.
Recognizing status register (SR.7~0) will assure if the
device goes back to normal reset and enters array read
mode.
3.5 Read Configuration Codes
The read configuration codes operation outputs the manufacturer code, device code, sector lock configuration
codes, and the protection register. Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The
sector lock codes identify locked and unlocked sectors.
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection
and clearing of the status register. When VCC=2.7V-3.6V
and VPP within VPP1 or VPP2 range, the CUI additionally controls sector erase, word write and sector lock/
unlock.
The Sector Erase command requires appropriate command data and an address within the sector to be erased.
The Full Chip Erase command requires appropriate command data and an address within the device. The Word
Write command requires the command and address of
the location to be written. Set Sector lock/unlock com-
REV. 1.2, MAR. 17, 2004
P/N:PM0867
9
MX28F160C3T/B
4 COMMAND DEFINITIONS
The flash memory has four read modes: read array, read
configuration, read status, read query, and two write
modes: program, erase. These read modes are accessible independent of the VPP voltage. But write modes
are disable during VPP<VPPLK. Placing VPP on VPP1/
2 enables successful sector erase, word write and sector lock/unlock.
Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.
Table 2. Bus Operation
Mode
Notes
RP
CE
OE
WE
DQ0~DQ15
Read
1,2
VIH
VIL
VIL
VIH
DOUT
Output Disable
2
VIH
VIL
VIH
VIH
High Z
Standby
2
VIH
VIH
X
X
High Z
Reset
2
VIL
X
X
X
High Z
Write
2,3,4,5
VIH
VIL
VIH
VIL
DIN
Notes:
1. Refer to DC Characteristics for VPPLK, VPP1, VPP2 voltage.
2. X can be VIL or VIH for pin and addresses.
3. RP at GND±0.2 to ensure the lowest power consumption.
4. Refer to Table 3 for valid DIN during a write operation.
5. To program or erase the lockable sectors holds WP at VIH.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
10
MX28F160C3T/B
Table 3. Command Definition (1)
Command
Bus
Notes
Cycles
Read Array
Read Configuration
First Bus Cycle
Operation Address
Second Bus Cycle
Data
Required
(1)
(2)
(3)
1
Write
X
FFH
Operation Address
Data
(1)
(2)
(3)
>2
2,4
Write
X
90H
Read
IA
ID
Read Query
2
2,7
Write
X
98H
Read
QA
QD
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
3
Write
X
50H
Sector Erase/Confirm
2
Write
X
20H
Write
SA
D0H
Word Write
2
Write
X
40H/10H
Write
WA
WD
Program/Erase Suspend
1
Write
X
B0H
Program/Erase Resume
1
Write
X
D0H
Sector Lock
2
Write
X
60H
Write
SA
01H
Sector Unlock
2
Write
X
60H
Write
SA
D0H
Lock-Down Sector
2
Write
X
60H
Write
SA
2FH
Protection Program
2
Write
X
C0H
Write
PA
PD
2,5
6
Notes:
1. Bus operation are defined in Table 2 and referred to AC Timing Waveform.
2. X=Any address within device.
IA=ID-Code Address (refer to Table 4).
ID=Data read from identifier code.
SA=Sector Address within the sector being erased.
WA=Address of memory location to be written.
WD=Data to be written at location WA.
PA=Program Address, PD=Program Data
QA=Query Address, QD=Query Data.
3. Data is latched from the rising edge of WE or CE (whichever goes high first)
SRD=Data read from status register, see Table 6 for description of the status register bits.
4. Following the Read Configuration codes command, read operation access manufacturer, device codes, sector
lock/unlock codes, see chapter 4.2.
5. Either 40H or 10H command is recognized by the WSM as word write setup.
6. The sector unlock operation simultaneously clear all sector lock.
7. Read Query Command is read for CFI query information.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
11
MX28F160C3T/B
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has
started a sector erase, word write or sector lock configuration the device will not recognize the Read Array
command until the WSM completes its operation unless
the WSM is suspended via a Sector Erase Suspend or
Word Write Suspend command. If RP=VIL device is in
read Read Array command mode, this read operation no
longer requires VPP. The Read Array command functions independently of the VPP voltage and RP can be
VIH.
CUI writes read status command (70H). The status register may be read to determine when a sector erase,
word write or lock-bit configuration is complete and
whether the operation completed successfully. (refer to
table 6) It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the status register until another valid command is written. The
status register contents are latched on the falling edge
of CE or OE, whichever occurs last. CE or OE must
toggle to VIH before further reads to update the status
register latch. The Read Status Register command functions independently of the VPP voltage. RP can be VIH.
4.4 Clear Status Register Command
4.2 Read Configuration Codes Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear
Status Register command (50H). These bits indicate
various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such
as cumulatively erasing multiple sectors or writing several words in sequence) may be performed. The status
register may be polled to determine if an error occurred
during the sequence.
The configuration code operation is initiated by writing
the Read Configuration Codes command (90H). To return to read array mode, write the Read Array Command
(FFH). Following the command write, read cycles from
addresses shown in Table 4 retrieve the manufacturer,
device, sector lock configuration codes and the protection register(see Table 4 for configuration code values).
To terminate the operation, write another valid command.
Like the Read Array command, the Read Configuration
Codes command functions independently of the VPP
voltage and RP can be VIH. Following the Read Configuration Codes command, the information is shown:
To clear the status register, the Clear Status Register
command (50H) is written on CUI. It functions independently of the applied VPP Voltage. RP can be VIH. This
command is not functional during sector erase or word
write suspend modes.
Table 4: ID Code
Code
Manufacturer Code
Address
Data
(A19-A0)
(DQ15-DQ0)
00000H
00C2H
Device Code(Top/Bottom) 00001H
88C2/88C3H
Sector Lock Configuration XX002H
LocK
- Sector is unlocked
DQ0=0
- Sector is locked
DQ0=1
- Sector is locked-down
DQ1=1
Protection Register Lock
80
PR-LK
Protection Register
81-88
PR
REV. 1.2, MAR. 17, 2004
P/N:PM0867
12
MX28F160C3T/B
should be checked. If word write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode
until it receives another command.
4.5 Sector Erase Command
Erase is executed one sector at a time and initiated by a
two-cycle command. A sector erase setup is first written (20H), followed by a sector erase confirm (D0H). This
command sequence requires appropriate sequencing and
an address within the sector to be erased. Sector preconditioning, erase, and verify are handled internally by
the WSM. After the two-cycle sector erase sequence is
written, the device automatically outputs status register
data when read (see Figure 8). The CPU can detect sector erase completion by analyzing the output data of the
status register bit SR.7.
Reliable word writes can only occur when
VCC=2.7V~3.6V and VPP=VPP1/2. If VPP is not within
acceptable limits, the WSM doesn't execut the program
command. If word write is attempted while VPP<VPPLK,
status register bits SR.3 and SR.4 will be set to "1".
Successful word write requires for boot sector that WP
is VIH the corresponding sector lock-bit be cleared. In
parameter and main sectors case, it must be cleared
the corresponding sector lock-bit. If word write is attempted when the excepting above sector being clocked
conditions, SR.1 and SR.4 will be set to "1". Word write
is not functional.
When the sector erase is complete, status register bit
SR.5 should be checked. If a sector erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued.
4.7 Sector Erase Suspend Command
This two-step command sequence of set-up followed by
execution ensures that sector contents are not accidentally erased. An invalid sector Erase command sequence
will result in both status register bits SR.4 and SR.5
being set to "1". Also, reliable sector erasure can only
occur when 2.7V~3.6V and VPP=VPP1/2. In the absence
of this high voltage, sector contents are protected against
erasure. If sector erase is attempted while VPP<VPPLK
SR.3 and SR.5 will be set to "1". To successfully erase
the boot sector, the corresponding sector lock-bit must
be clear first. In parameter and sectors case, it must be
cleared the corresponding sector lock-bit. If sector erase
is attempted when the excepting above sector being
locked conditions, SR.1 and SR.5 will be set to "1". Sector erase is not functional.
The Sector Erase Suspend command (50H) allows sector-erase interruption to read or word write data in another sector of memory. Once the sector erase process
starts, writing the Sector Erase Suspend command requests that the WSM suspend the sector erase sequence
at a predetermined point in the algorithm. The device
outputs status register data when read after the Sector
Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the sector
erase operation has been suspended (both will be set to
"1"). Specification tWHRH2/tEHRH2 defines the sector
erase suspend latency.
When Sector Erase Suspend command is written to the
CUI, if sector erase was finished, the device would be
placed read array mode. Therefore, after Sector Erase
Suspend command is written to the CUI, Read Status
Register command (70H) has to be written to CUI, then
status register bit SR.6 should be checked if/when the
device is in suspend mode.
4.6 Word Write Command
Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H)
is written, followed by a second write that specifies the
address and data. The WSM then takes over, controlling
the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word write event by analyzing the status register bit SR.7.
At this point, a Read Array command can be written to
read data from sectors other than that which is suspended. A Word Write commands sequence can also be
issued during erase suspend to program data in other
sectors. Using the Word Write Suspend command (see
Section 4.9), a word write operation can also be suspended. During a word write operation with sector erase
suspended, status register bit SR.7 will return to "0".
When word write is complete, status register bit SR.4
REV. 1.2, MAR. 17, 2004
P/N:PM0867
13
MX28F160C3T/B
However, SR.6 will remain "1" to indicate sector erase
suspend status.
is suspended are Read Status Register Read Configuration, Read Query and Word Write Resume. After Word
Write Resume command is written to the flash memory,
the WSM will continue the Word write process. Status
register bits SR.2 and SR.7 will automatically be cleared.
After the Word Write Resume command is written, the
device automatically outputs status register data when
read (see Figure 7). VPP must remain at VPP1/2 while
in word write suspend mode. RP must also remain at
VIH (the same RP level used for word write).
The only other valid commands while sector erase is
suspended are Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume,
Sector Lock, Sector Unlock, Sector Lock-Down and sector erase Resume. After a Sector Erase Resume command is written to the flash memory, the WSM will continue the sector erase process. Status register bits SR.6
and SR.7 will automatically be cleared. After the Erase
Resume command is written, the device automatically
outputs status register data when read (see Figure 9).
VPP must remain at VPP1/2 while sector erase is suspended. RP must also remain at VIH (the same RP level
used for sector erase). Sector cannot resume until word
write operations initiated during sector erase suspend
has completed.
If the time between writing the Word Write Resume command and writing the Word Write Suspend command is
short and both commands are written repeatedly, a longer
time is required than standard word write until the completion of the operation.
If the time between writing the Sector Erase Resume
command and writing the Sector Erase Suspend command is shorter than 15ms and both commands are written repeatedly, a longer time is required than standard
sector erase until the completion of the operation.
4.8 Word Write Suspend Command
The Word Write Suspend command allows word write
interruption to read data in other flash memory locations.
Once the word write process starts, writing the Word
Write Suspend command requests that the WSM suspend the Word write sequence at a predetermined point
in the algorithm. The device continues to output status
register data when read after the Word Write Suspend
command is written. Polling status register bits SR.7 and
SR.2 can determine when the word write operation has
been suspended (both will be set to "1"). Specification
tWHRH1/tEHRH1 defines the word write suspend latency.
When Word Write Suspend command write to the CUI, if
word write was finished, the device places read array
mode. Therefore, after Word Write Suspend command
write to the CUI, Read Status Register command (70H)
has to be written to CUI, then status register bit SR.2
should be checked for if/when the device is in suspend
mode.
At this point, a Read Array command can be written to
read data from locations other than that which is suspended. The only other valid commands while word write
REV. 1.2, MAR. 17, 2004
P/N:PM0867
14
MX28F160C3T/B
4.9 Sector Lock/Unlock /Lockdown Command
4.9.4 Read Sector Lock Status
4.9.1 Sector Locked State
The lock status of every sector can be read through
Read Configuration mode. To enter this mode, first command write 90H to the device. The subsequent reads at
sector address +00002 will output the lock status of this
sector. The lock status can be read from the lowest two
output pins DQ0 and DQ1. DQ0, DQ0 indicates the sector lock/unlock status and set by the lock command and
cleared by the unlock command. When entering lockdown, the lock status is automatically set. DQ1 indicates lock-down status and is set by the lock-down command. It cannot be further cleared by software, only by
device reset or power-down.
The default status of all sectors upon power-up or reset
is locked. Any attempt on program or erase operations
will result in an error on bit SR.1 of a locked sector. The
status of a locked sector can be changed to unlocked or
lock-down using software commands. An unlocked sector can be locked by writing the sector lock command
sequence, 60H followed by 01H.
4.9.2 Sector Unlocked State
An unlocked sector can be programmed or erased. All
unlocked sector return to the locked state when the device is either reset or powered down. The status of an
unlocked sector can be changed to locked or lockeddown using software commands. A locked sector can
be unlocked by writing unlock command sequence, 60H
followed by D0H.
Sector Lock Configuration Table
Lock Status
Sector is unlocked
Sector is locked
Sector is locked-down
Data
DQ0=0
DQ0=1
DQ1=1
4.9.3 Sector Locked-Down State
Sectors which are locked-down are protected from program and erase operation; however, the protection status of these sectors cannot be changed using software
commands alone. Any sector locked or unlocked can be
locked-down by writing the lock-down command sequence, 60H followed by 2FH. When the device is reset
or powered down, the locked-down sectors will revert to
the locked state.
The status of WP will determine the function of sector
lock-down and is summarized is followed:
WP
WP=0
WP=1
Sector Lock-down Description
- sectors are protected from program, erase,
and lock status changes
- the sector lock-down function is disabled
- an individual lock-down sector can be unlocked and relocked via software command.
Once WP goes low, sectors that previously
locked-down returns to lock-down state
regardless of any changes when WP was
high.
In addition, sector lock-down is cleared only when the
device is reset or powered down.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
15
MX28F160C3T/B
sector is being placed in erase suspend, the locking status bits will be changed immediately, but when the erase
is resumed, the erase operation will complete.
4.9.5 Sector Locking while Erase Suspend
The sector lock status can be performed during an erase
suspend by using standard locking command sequences
to unlock, lock, or lock-down a sector.
Locking operation cannot be performed during a program
suspend.
In order to change sector locking during an erase operation, the write erase suspend command (B0H) is placed
first; then check the status register until it is shown that
the actual erase operation has been suspended. Subsequent writing the desired lock command sequence to a
sector and the lock status will be changed. When completing any desired lock, read or program operation, resume the erase operation with the Erase Resume Command (D0H).
4.9.6 Status Register Error Checking
The operation of locking system for this device can be
used the term "state (X,Y,Z)" to specify locking status,
where X=value of WP, Y=bit DQ1 of the sector lock status register, and Z=bit DQ0 of the sector lock status
register. DQ0 indicates if a sector is locked (1) or unlocked (0). DQ1 indicates if a sector has been lockeddown(1) or not (0).
If a sector is locked or locked-down during the same
Table 5. Sector Locking State Transitions
WP
Current State
Erase/Prog.
(X, Y, Z)=
Operation if
Lock Command Input Result (Next State)
(X, Y, Z)=
DQ1
DQ0
Name
Enable ?
Lock
Unlock
Lock-Down
0
0
0
Unlocked
Yes
(001)
Unchanged
(011)
0
0
1
Locked (default)
No
Unchanged
(000)
(011)
0
1
1
Locked-Down
No
Unchanged
Unchanged
Unchanged
1
0
0
Unlocked
Yes
(101)
Unchanged
(111)
1
0
1
Locked
No
Unchanged
(100)
(111)
1
1
0
Lock-Down Disabled
Yes
(111)
Unchanged
(111)
1
1
1
Lock-Down Disabled
No
Unchanged
(110)
Unchanged
Note:
At power-up or device reset, all sectors default to locked state (001) (if WP=0).
Holding WP=0 is the recommended default.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
16
MX28F160C3T/B
Table 6. Status Register Definition
WSMS
SESS
ES
PS
VPPS
PSS
SLS
R
7
6
5
4
3
2
1
0
NOTES:
Check WSM bit first to determine word program or sector Erase completion, before checking Program or Erase
Status bits.
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
When Sector Erase Suspend is issued, WSM halts execution and sets both WSMS and SESS bits to "1". SESS
bit remains set to "1" until an Sector Erase Resume
command is issued.
SR.6 = SECTOR ERASE SUSPEND STATUS (SESS)
1 = Sector ERASE Suspended
0 = Sector Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Programming
0 = Successful Sector Erase or Clear Sector LockBits
When this bit (SR.5) is set to "1", it means WSM is
unable to verify successful sector erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to "1", WSM has attempted but failed
to program a word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The WSM interrogates VPP level only after the Program
or Erase command sequences have been entered and
informs the system if VPP has not been switched on.
SR.3 bit is not guaranteed to report accurate feedback
between VPPLK and VPP1 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend is issued, WSM halts the execution and sets both WSMS and PSS bits to "1". SR.2
remains set to "1" until a Program Resume command is
issued.
SR.1 = SECTOR LOCK STATUS (SLS)
1 =Program/Erase attempted an a locked sector;
operation aborted
0 = No operation to locked sectors
If a program or erase operation is attempted to one of
the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to
read status mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
SR. 0 is reserved for future use and should be masked
out when polling the status register.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
17
MX28F160C3T/B
read cycles from addresses shown in Table 7 will retrieve the specified information. To return to read array
mode, write the Read Array Command (FFH).
5. 128-Bit Protection Register
The 128 bits of protection register are divided into two
64-bit segments. One of the segments is programmed
at MXIC side with unique 64-bit number; where changes
are forbidden. The other segment is left empty for customer to program. Once the customer segment is programmed, it can be locked to prevent further reprogramming.
Two-cycle Protection Program Command is used to program protection register bits. The 64-bit number is programmed 16 bits at a time. First, write C0H Protection
Program Setup command. The next write to the device
will latch in address and data and program the specified
location. The allowable address are also shown in Table
7. Refer to Figure 11 for the Protection Register Programming Flowchart.
5.1 Protection Register Read & Programming
Any attempt to address Protection Program command
onto undefined protection register address space will
result in a Status Register error (SR.4 set to "1"). In
addition, attempting to program to a previously locked
protection register segment will result in a status register error (SR.4=1, SR.1=1).
The protection register is read in the configuration read
mode, which follows the stated Command Bus Definitions.
The device is switched to this read mode by writing the
Read Configuration command (90H). Once in this mode,
Table 7. Word-Wide Protection Register Addressing
Word
Lock
0
1
2
3
4
5
6
7
User
Both
Factory
Factory
Factory
Factory
Customer
Customer
Customer
Customer
A7
1
1
1
1
1
1
1
1
1
A6
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
A2
0
0
0
0
1
1
1
1
0
A1
0
0
1
1
0
0
1
1
0
A0
0
1
0
1
0
1
0
1
0
Notes: 1. Set address bit A19-A15=1 for TOP Boot device.
2. Set address bit A19-A15=0 for Bottom Boot device.
3. The address not specified in above are don't care.
Table 8. Protection Register Memory Map
5.2 Protection Register Locking
The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-Lock
location to 0. Bit 0 of this location is programmed to 0 at
MXIC to protect the unique device number. This bit is
set using the protection program command to program
"FFFD" to PR-LOCK location. After these bits have been
programmed, no further changes can be made to the
value stored in the protection register. Protection Program command to a locked section will result in a status
register error (Program Error bit SR.4 and Lock Error bit
SR.1 will be set to 1). Protection register lockout state is
not reversible.
Protection Register
Bit Address
88H~85H
84H~81H
80H(Bit0 & Bit1)
Purpose
4 words User Program
Register
4 words Factory Program
Register
Protection Register Lock
REV. 1.2, MAR. 17, 2004
P/N:PM0867
18
MX28F160C3T/B
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operation Conditions" may
affect device reliability.
6 ELECTRICAL SPECIFICATIONS
6.1 ABSOLUTE MAXIMUM RATINGS
Operating Temperature
During Read, Sector Erase, Word
Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC
Voltage on Any Pin (except VCC and
VPP) with respect to GND . . . . . . . . .-0.5 V to +3.7V(1)
VPP Supply Voltage (for Sector Erase and Word Write)
with respect to GND . . . . . . . . . .-0.5V to +13.5V(1,2,4)
VCC and VCCQ Supply Voltage
with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +3.6V(1)
Output Short Circuit Voltage . . . . . . . . . . . . .100mA(3)
1. Minimum DC voltage is -0.5V on input/output pins.
During transitions, this level may undershoot to -2.0V
for periods <20ns. Maximum DC voltage on input/output pins to VCC+0.5V which during transition; may
overshoot to VCC+2.0V for periods <20ns.
2. Maximum DC voltage on VPP may overshoot to
+14.0V for periods <20ns.
3. Output shorted for no more than one second. No more
than one output shorted at a time.
4. VPP voltage is normally 1.65V~3.6V. Connection to
supply of 11.4V~12.6V can only be done for 1000
cycles on the main sectors and 2500 cycles on the
parameter sectors during program/erase. VPP may
be connected to 12V for a total of 80 hours maximum.
WARNING: Stressing the device beyond the "Absolute
6.2 Operating Conditions (Temperature and VCC Operating Conditions)
Symbol
Parameter
Min.
Max.
TA
Unit
Notes
Operating Temperature
-40
+85
o
VCC1
VCC Supply Voltage
2.7
3.6
V
1
VCCQ
I/O Supply Voltage
2.7
3.6
V
1
VPP1
Supply Voltage
1.65
3.6
V
1
VPP2
Supply Voltage
11.4
12.6
V
1,2
Cycling
Sector Erase Cycling
C
100,000
2
NOTE:
1.VCC and VCCQ must share the same supply when they are in the VCC1 range.
2.Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main
sectors and 2500 cycles on the parameter sectors. VPP may be connected to 12V for a total of 80 hours maximum.
6.2.1 Capacitance (1) (TA=+25oC, f=1MHz)
Symbol
Parameter
Typ.
Max.
Unit
CIN
COUT
Test Condition
Input Capacitance
6
8
pF
VIN=0.0V
Output Capacitance
10
12
pF
VOUT=0.0V
NOTE:
1.Sampled, not 100% tested.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
19
MX28F160C3T/B
6.2.2 AC Input/Output Test Conditions
VCCQ
TEST POINTS
Input VCCQ/2
VCCQ/2 Output
0.0
Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0".
Figure 1. Transient Input/Output Reference Waveform
Figure 2. SWITCHING TEST CIRCUITS
TEST SPECIFICATIONS
Test Condition
70 90 110
Output Load
1 TTL gate
Output Load Capacitance, CL 30 100 100
(including jig capacitance)
Input Rise and Fall Times
5
Input Pulse Levels
0.0-3.0
Input timing measurement
1.5
reference levels
Output timing measurement
1.5
reference levels
2.7K ohm
DEVICE UNDER
TEST
3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
Unit
pF
ns
V
V
V
REV. 1.2, MAR. 17, 2004
P/N:PM0867
20
MX28F160C3T/B
6.2.3 AC Characteristic -- Read Only Operation (1)
-70
Notes
Min.
-90
Max.
Sym.
Parameter
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE to Output Delay
tGLQV
OE to Output Delay
tPHQV
RP to Output Delay
tELQX
CE to Output in Low Z
3
0
0
0
ns
tGLQX
OE to Output in Low Z
3
0
0
0
ns
tEHQZ
CE to Output in High Z
3
20
20
20
ns
tGHQZ
OE to Output in High Z
3
20
20
20
ns
tOH
Output Hold from Address,
3
70
Min.
-110
Max.
90
Min.
Max.
110
Unit
ns
70
90
110
ns
2
70
90
110
ns
2
20
30
30
ns
150
150
150
ns
0
0
0
ns
CE, or OE Change,
Whichever Occurs First
Notes:
1. See AC Waveform: Read Operations at Figure 3.
2. OE may be delayed up to tELQV-tGLQV after the falling edge of CE without impact on tELQV.
3. Sampled, but not 100% tested.
4. See test Configuration.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
21
MX28F160C3T/B
Figure 3. READ-ONLY OPERATION AC WAVEFORM
Addresses(A)
Device and
Address Selection
VIH
Data
Valid
Standby
Address Stable
VIL
tAVAV
CE (E)
VIH
VIL
tEHQZ
OE (G)
VIH
VIL
tGHQZ
WE (W)
VIH
tGLQV
VIL
tOH
tGLQX
tELQV
DATA VOH
(D/Q) VOL
tELQX
High Z
Valid Output
High Z
tAVQV
RP (P)
VIH
tPHQV
VIL
REV. 1.2, MAR. 17, 2004
P/N:PM0867
22
MX28F160C3T/B
6.2.5 AC Characteristic -- Write Operation
Note
-70
-90
-110
Min.
Min.
Min.
Unit
150
150
150
ns
0
0
0
ns
Sym.
Parameter
tPHWL/tPHEL
RP High Recovery to WE(CE) Going Low
tELWL/tWLEL
CE(WE) Setup to WE(CE) Going Low
tWLWH/tELEH
WE(CE) Pulse Width
4
45
60
70
ns
tDVWH/tDVEH
Data Setup to WE(CE) Going High
2
40
50
60
ns
tAVWH/tAVEH
Address Setup to WE(CE) Going High
2
50
60
70
ns
0
0
0
ns
tWHEH/tEHWH CE(WE) Hold Time from WE(CE) High
tWHDX/tEHDX
Data Hold Time from WE(CE) High
2
0
0
0
ns
tWHAX/tEHAX
Address Hold Time from WE(CE) High
2
0
0
0
ns
tWHWL/tEHEL
WE(CE) Pulse Width High
4
25
30
30
ns
tVPWH/tVPEH
VPP Setup to WE(CE) Going High
3
200
200
200
ns
tQVVL
VPP Hold from Valid SRD
3
0
0
0
ns
tBHWH/tBHEH
WP Setup to WE(CE)Going High
3
0
0
0
ns
tQVBL
WP Hold from Valid SRD
3
0
0
0
ns
tWHGL
WE High to OE Going Low
3
30
30
30
ns
Notes:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. Refer to Table 5 for valid AIN or DIN.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CE or WE going low (whichever goes low last) to CE or WE going high
(whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. Similarly, Write pulse width high (tWPH)
is defined from CE or WE going high (whichever goes high first) to CE or WE going low (whichever goes low first).
Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
5. See Test Configuration.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
23
MX28F160C3T/B
Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM
A
Address (A)
B
C
AIN
AIN
D
E
F
VIH
VIL
tAVWH
(tAVEH)
tWHAX
(tEHAX)
(Note 1)
VIH
CE(WE)[E(W)]
VIL
tELWL
(tWLEL)
tWHEH
(tEHWH)
VIH
OE(G)
tWHWL
(tEHEL)
VIL
tWHGL
(Note 1)
Disable VIH
WE,(CE)[W(E)]
Enable VIL
tELEH
(tWLWH)
VIH High Z
DATA[D/Q]
tDVWH
(tEVEH)
tWHDX
(tEHDX)
DIN
DIN
VIL
Valid
SRD
DIN
tPHWL
(tPHEL)
VOH
RP[P]
VOL
tQVBL
tBHWH
(tBHEH)
VIH
WP
VIL
tVPWH
(tVPEH)
tQVVL
VPPH2
VPP[V] VPPH1
VPPLK
VIL
Notes:
1. CE must be toggled low when reading Status Register Data. WE must be inactive (high) when reading Status
Register Data.
A.VCC Power-Up and Standby.
B.Write Program or Erase Setup Command.
C.Write Valid Address and Data (for Program) or Erase Confirm Command.
D.Automated Program or Erase Delay.
E.Read Status Register Data (SRD): reflects completed program/erase operation.
F.Write Read Array Command.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
24
MX28F160C3T/B
6.2.5 Erase and Program Timing (1)
Vpp
Symbol
Parameter
tBWPB
4-KW Parameter Sector
1.65V-3.6V
11.4V-12.6V
Note
Typ(1)
Max
Typ(1)
Max
Unit
2,3
0.10
0.30
0.03
0.12
s
2,3
0.8
2.4
0.24
1
s
Word Program Time
2,3
12
200
8
185
us
tWHQV2/
4-KW Parameter Sector
2,3
0.5
4
0.4
4.0
s
tEHQV2
Erase Time
tWHQV3/
32-KW Main Sector
2,3
1
5
0.6
5
s
tEHQV3
Erase Time
tWHRH1/
Program Suspend Latency
3
15
20
15
20
us
Erase Suspend Latency
3
15
20
15
20
us
Word Program Time
tBWMB
32-KW Main Sector
Word Program Time
tWHQV1/
tEHQV1
tEHRH1
tWHRH2/
tEHRH2
Notes:
1. Typical values measured at TA=+25° C and nominal voltage.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
25
MX28F160C3T/B
Figure 5. RESET WAVEFORM
VIH
RP (P)
tPHQV
tPHWL
tPHEL
VIL
tPLPH
(A) Reset during Read Mode
tPLRH
tPHQV
tPHWL
tPHEL
Abort
Complete
VIH
RP (P)
VIL
tPLPH
(B) Reset during Program or Sector Erase, tPLPH < tPLRH
Abort
Complete
tPLRH
Deep
PowerDown
tPHQV
tPHWL
tPHEL
VIH
RP (P)
VIL
tPLPH
(C) Reset Program or Sector Erase, tPLPH > tPLRH
AC Characteristic -- Under Reset Operation
Sym.
Parameter
VCC=2.7V~3.6V
Min.
tPLPH
RP Low to Reset during Read
Unit
Notes
ns
1,3
Max.
100
(If RP is tied to VCC, this specification is not applicable)
tPLRH1
RP Low to Reset during Sector Erase
22
us
1,4
tPLRH2
RP Low to Reset during Program
12
us
1,4
Notes:
1. See Section 3.4 for a full description of these conditions.
2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.
3. If RP is asserted while a sector erase or word program operation is not executing, the reset will complete within
100ns.
4. Sampled, but not 100% tested.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
26
MX28F160C3T/B
6.2.6 DC Characteristics
VCC
2.7V-3.6V
VCCQ
2.7V-3.6V
Note Typ.
Max.
1,2
±1
Sym.
Parameter
ILI
Input Load Current
ILO
Output Leakage
Current
VCC Standby Current
1,2
0.2
± 10
uA
1
7
15
uA
ICCD
VCC Power-Down
Current
1,2
7
15
uA
ICCR
VCC Read Current
1,2,3
9
18
mA
IPPD
1
0.2
5
uA
IPPR
VPP Deep PowerDown Current
VPP Read Current
1,4
ICCW+
IPPW
ICCE+
IPPE
ICCES
or
ICCWS
VIL
VIH
VOL
VCC+VPP Program
Current
VCC+VPP Erase
Current
VCC Program
or Erase Suspend
Current
Input Low Voltage
Input High Voltage
Output Low Voltage
2
50
18
10
21
16
7
±15
200
55
30
45
45
15
uA
uA
mA
mA
mA
mA
uA
-0.4
2.0
-0.1
VCC*0.22V
VCCQ+0.3V
0.1
V
V
V
VOH
Output High Voltage
VPPLK
VPP1
VPP2
VLKO
VPP Lock-Out Voltage
VPP during Program/
Erase Operations
VCC Prog/Erase
Lock Voltage
VCCQ Prog/Erase
Lock Voltage
ICCS
VLKO2
1,4
1,4
1,4
VCCQ
-0.1V
6
6
6
1.65
11.4
1.5
Unit
uA
V
1.0
3.6
12.6
1.2
V
V
V
V
Test Conditions
VCC=VCC Max. ; VCCQ=VCCQ Max.
VIN=VCCQ or GND
VCC=VCC Max. ; VCCQ=VCCQ Max.
VIN=VCCQ or GND
VCC=VCC Max. ; CE=RP=VCCQ
or during Program/Erase Suspend
WP=VCCQ or GND
VCC=VCC Max ; VCCQ=VCCQ Max
VIN=VCCQ or GND
RP=GND±0.2V
VCC=VCC Max ; VCCQ=VCCQ Max
OE=VIH, CE=VIL, f=5MHz, IOUT=0mA
Inputs=VIL or VIH
RP=GND±0.2V
VPP < VCC
VPP < VCC
VPP > VCC
VPP=VPP1, Program in Progress
VPP=VPP2(12V), Program in Progress
VPP=VPP1, Erase in Progress
VPP=VPP2(12V), Erase in Progress
CE=VCC,
Program or Erase Suspend in Progress
VCC=VCC Min, VCC=VCCQ Min
IOL=100uA
VCC=VCC Min, VCC=VCCQ Min
IOH=-100uA
Complete Write Protection
V
REV. 1.2, MAR. 17, 2004
P/N:PM0867
27
MX28F160C3T/B
Notes:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA=+25° C.
2. The test conditions VCC Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum or minimum VCC or
VCCQ voltage listed at the top of each column.
3. Power Savings (Mode) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
4. Sampled, but not 100% tested.
5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is
sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and
ICCR.
6. Erase and Program are inhibited when VPP<VPPLK.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
28
MX28F160C3T/B
Figure 6. Automated Word Programming Flowchart
Bus
Command
Operation
Write
Program
Setup
Write
Program
Start
Write 40H
Data=40H
Data=Data to Program
Addr=Location to Program
Read
Status Register Data Toggle
CE or OE to Update Status
Register Data
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent programming operations.
SR full status check can be done after each program
or after a sequence of program operations.
Write FFH after the last program operation to reset
device to read array mode.
Program Address/Data
Read Status Register
SR.7=1 ?
Comments
No
Yes
Full Status
Check if Desired
Program Ccomplete
Bus
Command
Operation
Standby
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
1
Check SR.3
1=VPP Low Detect
Standby
Check SR.4
1=VPP Program Error
Standby
Check SR.1
1=Attempted Program to
Locked Sector-Program
Aborted
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write
State Machine.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command, in cases where multiple
bytes are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
VPP Range Error
0
SR.4=
1
Programming Error
0
SR.1=
1
Comments
Attempted Program to
Locked Sector- Aborted
0
Program Successful
REV. 1.2, MAR. 17, 2004
P/N:PM0867
29
MX28F160C3T/B
Figure 7. Program Suspend/Resume Flowchart
Bus
Command
Operation
Write
Program
Suspend
Write
Read Status
Start
Write B0H
Write 70H
Read
Read
Status Register
SR.7=
0
Standby
1
Stanby
SR.2=
0
Program Completed
Write
1
Read Array
Write FFH
Read
Read Array Data
Write
Done Reading
Program
Resume
Comments
Data=B0H
Addr=X
Data=70H
Addr=X
Status Register Data Toggle
CE or OE to Update Status
Register Data
Addr=X
Check SR.7
1=WSM Ready
0=WSM Busy
Check SR.2
1=Program Suspended
0=Program Completed
Data=FFH
Addr=X
Read array data from
sector other than the one
being programmed.
Data=D0H
Addr=X
No
Yes
Write D0H
Write FFH
Program Write Resumed
Read Array Data
REV. 1.2, MAR. 17, 2004
P/N:PM0867
30
MX28F160C3T/B
Figure 8. Automated Sector Erase Flowchart
Bus
Command Comments
Operation
Write
Erase Setup Data=20H
Addr=Within Sector to Be
Erased
Write
Erase
Data=D0H
Confirm
Addr=Within Sector to Be
Erased
Read
Status Register Data Toggle
CE or OE to Update Status
Register Data
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent sector erasures.
Full status check can be done after each sector erase
or after a sequence of sector erasures.
Write FFH after the last write operation to reset device
to read array mode.
Start
Write 20H
Write D0H and
Sector Address
Read
Status Register
Suspend
Erase Loop
No
SR.7=
Yes
0
Suspend Erase
1
Full Status Check if Desired
Sector Erase Complete
FULL STATUS CHECK PROCEDURE
Bus
Command
Operation
Standby
Read Status Register
Data(See Above)
SR.3=
1
Check SR.3
1=VPP Low Detect
Standby
Check SR.4, 5
Both 1=Command
Sequence Error
Standby
Check SR.5
1=Sector Erase Error
Standby
Check SR.1
1=Attempted Erase of
Locked Sector- Erase
Aborted
SR.1 and SR.3 MUST be cleared, if set during an erase
attempt, before further attempts are allowed by the
Write State Machine.
SR.1,3,4,5 are only cleared by the Clear Status Register Command, in cases where multiple bytes are
erased before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
VPP Range Error
0
SR.4,5=
1
Command Sequence Error
0
SR.5=
1
Sector Erase Error
0
SR.1=
1
Comments
Attempted Erase of Locked
Sector - Aborted
0
Sector Erase Successful
REV. 1.2, MAR. 17, 2004
P/N:PM0867
31
MX28F160C3T/B
Figure 9. Erase Suspend/Resume Flowchart
Bus
Command
Operation
Write
Erase
Suspend
Write
Read Status
Start
Write B0H
Write 70H
Read
Read
Status Register
SR.7=
Standby
0
1
Stanby
SR.6=
0
Erase Completed
Write
1
Read Array
Write FFH
Read
Read Array Data
Write
Done Reading
Erase
Resume
Comments
Data=B0H
Addr=X
Data=70H
Addr=X
Status Register Data Toggle
CE or OE to Update Status
Register Data
Addr=X
Check SR.7
1=WSM Ready
0=WSM Busy
Check SR.6
1=Erase Suspended
0=Erase Completed
Data=FFH
Addr=X
Read array data from
sector other than the one
being erased.
Data=D0H
Addr=X
No
Yes
Write D0H
Write FFH
Erase Write Resumed
Read Array Data
REV. 1.2, MAR. 17, 2004
P/N:PM0867
32
MX28F160C3T/B
Figure 10. Locking Operations Flowchart
Bus
Command
Comments
Operation
Write
Config. Setup Data=60H
Addr=X
Write
Lock, unlock Data=01H (Sector Lock)
or Lockdown
D0H(Sector Unlock)
2FH(Sector Lockdown)
Addr=Within sector to lock
Write
Read Status Data=70H
(Optional) Register
Addr=X
Read
Status Register Register
(Optional)
Addr=X
Stanby
Check Status Register
(Optional)
80H=no error
30H=Lock Command
Sequence Error
Write
Read
Data=90H
(Optional) Configuration Addr=X
Read
Sector Lock Sector Lock Status Data
(Optional)
Status
Addr=Second addr of
sector
Stanby
Confirm Locking Change
on DQ1, DQ0 (See Sector
Locking State Table for
valid combinations.)
Start
Write 60H
(Configuration Setup)
Write
01H, D0H, or 2FH
Write 70H
(Read Status Register)
Lock Command
Sequence Error
Read Status Register
SR.4, SR.5=
1,1
0,0
Write 90H
(Read Configuration)
Read Sector Lock Status
Locking Change
Confirmed ?
No
Yes
Locking Change
Complete
REV. 1.2, MAR. 17, 2004
P/N:PM0867
33
MX28F160C3T/B
Figure 11. Protection Register Programming Flowchart
Bus
Command
Operation
Write
Protection
Program
Setup
Write
Protection
Program
Read
Start
Write C0H
(Protection Reg. Program Setup)
Data=C0H
Data=Data to Program
Addr=Location to Program
Status Register Data Toggle
CE or OE to Update Status
Register Data
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Protection Program operations can only be addressed
within the protection register address space. Addresses
outside the defined space will return an error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program
or after a sequence of program operations.
Write FFH after the last operation to reset device to
read array mode.
Write Protect. Register
Address/Data
Read Status Register
SR.7=1 ?
Comments
No
Yes
Full Status
Check if Desired
Program Ccomplete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3, SR.4=
SR.1, SR.4=
SR.1, SR.4=
Bus
Command
Operation
Standby
1,1
SR.1, SR.3, SR.4
0
1
1 VPP Low
Standby
0
0
1 Prot. Reg.
Prog. Error
Stanby
1
0
1 Register
Locked:
Aborted
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write
State Machine.
SR.1,3,4 are only cleared by the Clear Status Register Command, in cases of multiple protection register
program operations before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
VPP Range Error
0,1
Protection Register
programming Error
1,1
Attempted Program to
Locked Register Aborted
Comments
Program Successful
REV. 1.2, MAR. 17, 2004
P/N:PM0867
34
MX28F160C3T/B
7 VPP Program and Erase Voltage
MX28F160C3T/B product provides in-system programming and erase in the 1.65V~3.6V of VPP range. In addition, VPP pin on 12V provides fast production programming.
7.1 VPP Fast manufacturing Programming
When VPP is between 1.65V and 3.6V, all program and
erase current is drawn through the VCC pin. If VPP is
driven by a logic signal, VIH=1.65V. That is, VPP must
remain above 1.65V to perform in-system flash update/
modifications. When VPP is connected to a 12V power
supply, the device draws program and erase current directly from the VPP pin.
7.2 Protection Under VPP<VPPLK
VPP can off additional hardware write protection. The
VPP programming voltage can be kept low for the absolute hardware protection of all sector in the flash device.
As VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding
status register bit (SR.3) to be set.
REV. 1.2, MAR. 17, 2004
P/N:PM0867
35
MX28F160C3T/B
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Program Suspend, Standby mode, and Read ID mode;
however, it is ignored otherwise.
8. QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX28F160C3T/B is capable of operating in the CFI mode.
This mode allows the host system to determine the
manufacturer of the device such as operating parameters and configuration. Two commands are required in
CFI mode. Query command of CFI mode is placed first,
then the Reset command exits CFI mode. These are
described in Table 3.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, Program Suspend
or read ID mode. The command is valid only when the
device is in the CFI mode.
Table 9-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Address h
Data h
10
0051
11
0052
12
0059
13
0003
14
0000
15
0035
16
0000
17
0000
18
0000
19
0000
1A
0000
Address h
Data h
VCC supply, minimum (2.7V)
1B
0027
VCC supply, maximum (3.6V)
1C
0036
VPP supply, minimum (11.4V)
1D
00B4
VPP supply, maximum (12.6V)
1E
00C6
Typical timeout for single word write (2N us)
1F
0005
Typical timeout for maximum size buffer write (2N us)
20
0000
Typical timeout for individual sector erase (2N ms)
21
000A
Typical timeout for full chip erase (2N ms) (not supported)
22
0000
Maximum timeout for single word write times (2N X Typ)
23
0004
Maximum timeout for maximum size buffer write times (2N X Typ)
24
0000
Maximum timeout for individual sector erase times (2N X Typ)
25
0003
Maximum timeout for full chip erase times (not supported)
26
0000
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
Table 9-2. CFI Mode: System Interface Data Values
Description
REV. 1.2, MAR. 17, 2004
P/N:PM0867
36
MX28F160C3T/B
Table 9-3. CFI Mode: Device Geometry Data Values
Description
Device size (2n bytes)
Flash device interface code (asynchronous x16)
Maximum number of bytes in write buffer=2n (not supported)
Number of erase sector regions within device (one or more continuous
same-size erase sectors at one sector region)
Address h
27
28
29
2A
2B
2C
Erase Sector Region 1 information
[2E,2D] = number of same-size sectors in region 1-1
[30, 2F] = region erase sector size in multiples of 256-bytes
2D
2E
2F
30
Erase Sector Region 2 information
[32,31] = number of same-size sectors in region 2-1
[34,33] = region erase sector size in multiples of 256-bytes
31
32
33
34
Data h
0015
0001
0000
0000
0000
0002
T B
1E 07
00 00
00 20
01 00
T B
07 1E
00 00
20 00
00 01
REV. 1.2, MAR. 17, 2004
P/N:PM0867
37
MX28F160C3T/B
Table 9-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Query-unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
Optional Feature & Command Support
bit 0 Chip Erase Supported (1=yes, 0=no)
bit 1 Suspend Erase Supported (1=yes, 0=no)
bit 2 Suspend Program Supported (1=yes, 0=no)
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bit 5 Instant individual sector locking supported (1=yes, 0=no)
bit 6 Protection bits supported (1=yes, 0=no)
bit 7 Page mode read supported (1=yes, 0=no)
bit 8 Synchronous read support (1=yes, 0=no)
bits 9-31 revered for future use; undefined bits are "0"
Supported functions after suspend
bit 0 Program supported after erase suspend (1=yes, 0=no)
bit 1-7 Reserved for other supported options; undefined bits are "0"
Sector Lock Status
Define which bits in the sector status Register section of the Query are
implemented.
bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no)
bit 1 sector Lock Status Register Lock-Down bit (bit 1) active; (1=yes, 0=no)
Bits 2-15 reserved for future use. Undefined bits are "0".
VCC Logic Supply Optimum Program/Erase Voltage (highest performance)
bits 7-4 BCD value in volts
bits 3-0 BCD value in 100mV
VPP Supply Optimum Program/Erase Voltage
bits 7-4 HEX value in volts
bits 3-0 BCD value in 100mV
Address h
35
36
37
38
39
3A
3B
3C
3D
Data h
0050
0052
0049
0031
0030
66
00
00
00
3E
01
3F
40
03
00
41
33
42
C0
REV. 1.2, MAR. 17, 2004
P/N:PM0867
38
MX28F160C3T/B
ORDER INFORMATION
PART NO.
ACCESS TIME
OPERATING
STANDBY
PACKAGE
(ns)
Read Current MAX.(mA)
Current MAX.(uA)
MX28F160C3TTC-70
70
18
15
48 Pin TSOP
MX28F160C3BTC-70
70
18
15
48 Pin TSOP
MX28F160C3TTC-90
90
18
15
48 Pin TSOP
MX28F160C3BTC-90
90
18
15
48 Pin TSOP
MX28F160C3TTC-11
110
18
15
48 Pin TSOP
MX28F160C3BTC-11
110
18
15
48 Pin TSOP
MX28F160C3TTI-70
70
18
15
48 Pin TSOP
MX28F160C3BTI-70
70
18
15
48 Pin TSOP
MX28F160C3TTI-90
90
18
15
48 Pin TSOP
MX28F160C3BTI-90
90
18
15
48 Pin TSOP
MX28F160C3TTI-11
110
18
15
48 Pin TSOP
MX28F160C3BTI-11
110
18
15
48 Pin TSOP
MX28F160C3TXAC-70
70
18
15
48 Ball CSP
MX28F160C3BXAC-70
70
18
15
48 Ball CSP
MX28F160C3TXAC-90
90
18
15
48 Ball CSP
MX28F160C3BXAC-90
90
18
15
48 Ball CSP
MX28F160C3TXAC-11
110
18
15
48 Ball CSP
MX28F160C3BXAC-11
110
18
15
48 Ball CSP
MX28F160C3TXAI-70
70
18
15
48 Ball CSP
MX28F160C3BXAI-70
70
18
15
48 Ball CSP
MX28F160C3TXAI-90
90
18
15
48 Ball CSP
MX28F160C3BXAI-90
90
18
15
48 Ball CSP
MX28F160C3TXAI-11
110
18
15
48 Ball CSP
MX28F160C3BXAI-11
110
18
15
48 Ball CSP
MX28F160C3TTC-70G
70
18
15
48 Pin TSOP
MX28F160C3BTC-70G
70
18
15
48 Pin TSOP
MX28F160C3TTC-90G
90
18
15
48 Pin TSOP
MX28F160C3BTC-90G
90
18
15
48 Pin TSOP
MX28F160C3TTC-11G
110
18
15
48 Pin TSOP
MX28F160C3BTC-11G
110
18
15
48 Pin TSOP
MX28F160C3TTI-70G
70
18
15
48 Pin TSOP
MX28F160C3BTI-70G
70
18
15
48 Pin TSOP
MX28F160C3TTI-90G
90
18
15
48 Pin TSOP
MX28F160C3BTI-90G
90
18
15
48 Pin TSOP
REV. 1.2, MAR. 17, 2004
P/N:PM0867
39
MX28F160C3T/B
PART NO.
ACCESS TIME
OPERATING
STANDBY
PACKAGE
(ns)
Read Current MAX.(mA)
Current MAX.(uA)
MX28F160C3TTI-11G
110
18
15
48 Pin TSOP
MX28F160C3BTI-11G
110
18
15
48 Pin TSOP
MX28F160C3TXAC-70G
70
18
15
48 Ball CSP
MX28F160C3BXAC-70G
70
18
15
48 Ball CSP
MX28F160C3TXAC-90G
90
18
15
48 Ball CSP
MX28F160C3BXAC-90G
90
18
15
48 Ball CSP
MX28F160C3TXAC-11G
110
18
15
48 Ball CSP
MX28F160C3BXAC-11G
110
18
15
48 Ball CSP
MX28F160C3TXAI-70G
70
18
15
48 Ball CSP
MX28F160C3BXAI-70G
70
18
15
48 Ball CSP
MX28F160C3TXAI-90G
90
18
15
48 Ball CSP
MX28F160C3BXAI-90G
90
18
15
48 Ball CSP
MX28F160C3TXAI-11G
110
18
15
48 Ball CSP
MX28F160C3BXAI-11G
110
18
15
48 Ball CSP
REV. 1.2, MAR. 17, 2004
P/N:PM0867
40
MX28F160C3T/B
PACKAGE INFORMATION
REV. 1.2, MAR. 17, 2004
P/N:PM0867
41
MX28F160C3T/B
REV. 1.2, MAR. 17, 2004
P/N:PM0867
42
MX28F160C3T/B
REVISION HISTORY
Revision No. Description
1.0
1. To modify "Advanced Information" to "Preliminary"
1. To modify Package Information
1.1
1. To added address definition notes for Top/Bottom boot device of
Protection Register Section
1.2
1. Removed "Preliminary" wording
Page
P1
P41,42
P18
Date
NOV/27/2002
P1
MAR/17/2004
MAY/05/2003
REV. 1.2, MAR. 17, 2004
P/N:PM0867
43
MX28F160C3T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
Similar pages