MC74ACT640 Octal 3−State Inverting Transciever The MC74ACT640 octal bus transceiver is designed for asynchronous two-way communication between data buses. The device transmits data from bus A to bus B when T/R = HIGH, or from bus B to bus A when T/R = LOW. The enable input can be used to disable the device so the buses are effectively isolated. http://onsemi.com Features • • • • PDIP−20 N SUFFIX CASE 738 Bidirectional Data Path A and B Outputs Sink 24 mA/Source −24 mA TTL Compatible Inputs Pb−Free Packages are Available* 1 VCC OE B0 B1 B2 B3 B4 B5 B6 B7 20 19 18 17 16 15 14 13 12 11 SOIC−20W DW SUFFIX CASE 751D 1 SOEIAJ−20 M SUFFIX CASE 967 1 1 2 3 4 5 6 7 T/R A0 A1 A2 A3 A4 A5 8 9 10 A6 A7 GND ORDERING INFORMATION Figure 1. Pinout: 20−Lead Packages Conductors (Top View) Package Shipping † MC74ACT640N PDIP−20 18 Units/Rail MC74ACT640NG PDIP−20 (Pb−Free) 18 Units/Rail Device PIN ASSIGNMENT PIN FUNCTION A0−A7 Side A Inputs or 3-State Outputs OE Output Enable Input MC74ACT640DW SOIC−20 38 Units/Rail T/R Transmit/Receive Input MC74ACT640DWG Side B Inputs or 3-State Outputs SOIC−20 (Pb−Free) 38 Units/Rail B0−B7 MC74ACT640DWR2 SOIC−20 1000 / Tape & Reel MC74ACT640DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel TRUTH TABLE OE T/R Applied Inputs Valid Direction I/P→O/P H X X X X L H H A to B L L H L A to B H L L H B to A L L L L B to A H Output MC74ACT640MELG SOEIAJ−20 2000 / Tape & (Pb−Free) Reel DEVICE MARKING INFORMATION *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. December, 2006 − Rev. 3 SOEIAJ−20 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial © Semiconductor Components Industries, LLC, 2006 MC74ACT640MEL 1 See general marking information in the device marking section on page 4 of this data sheet. Publication Order Number: MC74ACT640/D MC74ACT640 MAXIMUM RATINGS Symbol VCC Parameter Value Unit *0.5 to )7.0 V *0.5 v VI v VCC )0.5 V *0.5 v VO v VCC )0.5 V DC Supply Voltage VI DC Input Voltage VO DC Output Voltage (Note 1) IIK DC Input Diode Current $20 mA IOK DC Output Diode Current $50 mA IO DC Output Sink/Source Current $50 mA ICC DC Supply Current per Output Pin $50 mA IGND DC Ground Current per Output Pin $50 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead temperature, 1 mm from Case for 10 Seconds TJ Junction temperature under Bias qJA Thermal resistance PD Power Dissipation in Still Air at 85_C MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup _C _C PDIP SOIC 67 96 _C/W PDIP SOIC 750 500 mW Level 1 Oxygen Index: 30% − 35% ESD Withstand Voltage Latchup Performance 260 )150 UL 94 V−0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) > 2000 > 200 > 1000 V Above VCC and Below GND at 85_C (Note 5) $100 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Input Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Typ Max Unit 4.5 5.5 V 0 VCC V −40 25 +85 °C 0 0 10 8.0 10 8.0 ns/V Junction Temperature (PDIP) 140 °C IOH Output Current − High −24 mA IOL Output Current − Low 24 mA TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Note 7) TJ VCC = 4.5 V VCC = 5.5 V 6. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level. 7. Vin from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times. http://onsemi.com 2 MC74ACT640 DC CHARACTERISTICS Symbol Parameter TA = −405C to +855C TA = +255C VCC (V) Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V V IOUT = −50 mA 3.86 4.86 3.76 4.76 V V *VIN = VIL or VIH IOH 0.1 0.1 0.1 0.1 V V IOUT = 50 mA 4.5 5.5 0.36 0.36 0.44 0.44 V V *VIN = VIL or VIH IOH Maximum Input Leakage Current 5.5 ±0.1 ±1.0 mA VI = VCC, GND Additional Max. ICC/Input 5.5 1.5 mA VI = VCC − 2.1 V Maximum 3−State Current 5.5 ±0.5 ±5.0 mA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND IOLD IOHD †Minimum Dynamic Output Current 5.5 5.5 75 −75 mA mA VOLD = 1.65 V Max ICC Maximum Quiescent Supply Current 5.5 80 mA VIN = VCC or GND 4.5 5.5 VOL IIN DICCT IOZ Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 0.6 8.0 −24 mA −24 mA −24 mA −24 mA *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS tr = tf = 3.0 ns (For Figures and Waveforms, See Figures 2 and 3.) VCC* (V) TA = +255C CL = 50 pF TA = −405C to +855C CL = 50 pF Min Max Min Max Unit tPLH Propagation Delay An to Bn or Bn to An 5.0 1.5 8.0 1.0 8.5 ns tPHL Propagation Delay An to Bn or Bn to An 5.0 1.5 8.0 1.0 9.0 ns tPZH Output Enable Time OE to An or Bn 5.0 1.5 10.0 1.0 11.0 ns tPZL Output Enable Time OE to An or Bn 5.0 1.5 10.0 1.0 11.0 ns tPHZ Output Disable Time T/R or OE to An or Bn 5.0 1.5 10.0 1.0 11.0 ns tPLZ Output Disable Time T/R or OE to An or Bn 5.0 1.5 10.0 1.0 11.0 ns Symbol Parameter *Voltage Range 5.0 V is 5.0 V ±0.5 V CAPACITANCE Symbol Value Typ Unit Test Conditions CIN Input Capacitance Parameter 4.5 pF VCC = 5.0 V CI/O Input/Output Capacitance 15 pF VCC = 5.0 V CPD Power Dissipation Capacitance 45 pF VCC = 5.0 V http://onsemi.com 3 MC74ACT640 SWITCHING WAVEFORMS 3.0 V T/R tr INPUT A or B 3.0 V 90% 50% 10% tPHL 3.0 V GND tTHL 50% OE tPLH GND tPZL tPLZ 90% 50% 10% OUTPUT A or B GND tf HIGH IMPEDANCE 50% A OR B 10% VOL 90% VOH tPZH tPHZ tTLH 50% A OR B Figure 2. HIGH IMPEDANCE Figure 3. 450 W INPUT OUTPUT DEVICE UNDER TEST 50 W SCOPE TEST POINT CL* *Includes all probe and jig capacitance Figure 4. Test Circuit MARKING DIAGRAMS PDIP−20 SOIC−20W 20 SOEIAJ−20 20 20 ACT640 AWLYYWWG MC74ACT640N AWLYYWWG 74ACT640 AWLYWWG 1 1 1 A WL YY, Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package http://onsemi.com 4 MC74ACT640 PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. −A− 20 11 1 10 B L C −T− K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 M SOIC−20W DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 18X e A1 SEATING PLANE C T http://onsemi.com 5 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74ACT640 PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX CASE 967−01 ISSUE A 20 LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.81 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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