Mitel MT9085 Cmos pac - parallel access circuit Datasheet

CMOS MT9085
PAC - Parallel Access Circuit

Features
ISSUE 3
•
Configurable for parallel-to-serial or
serial-to-parallel conversion of 1024 channels
•
Interfaces to Mitel’s MT9080 Switch Matrix
Module (SMX). Generates all framing signals
required in 1K or 2K switching applications
•
Serial data rates of 2.048 Mbit/s or 4.096 Mbit/s
•
Mitel ST-BUS compatible serial inputs/outputs
January 1993
Ordering Information
MT9085AP
68 Pin PLCC
-40°C to 70°C
Description
Applications
•
Interfacing the MT9080 Switch Matrix Module to
an ST-BUS system
•
Rate conversion between 4 Mbit/s and 2 Mbit/s
serial streams
•
Interfacing a parallel system bus to devices
utilizing serial I/O
The MT9085 Parallel Access Circuit (PAC) provides
an interface between an 8 bit, parallel time division
multiplexed bus and a serial time division
multiplexed bus. A single PAC device will accept
data clocked out on the parallel bus of the Mitel
MT9080 (SMX) and output it on 32/16 time division
multiplexed serial bus streams. A second device can
be configured to perform the conversion from the
serial format into an SMX compatible parallel format.
The time division, serial multiplexed streams may
operate at 2.048 Mbit/s or at 4.096 Mbit/s. The PAC
generates all framing signals required by the SMX
for 1024 and 2048 channel configurations.
S0
S1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S30
S31
P0
•
•
P7
C4i
F0i
C16i
Shift
Registers
Timing
Generation
Address
Decoder
C16
C4
C2o
C4o
F0o
DFPo
DFPo
CFPo
LOAD
C16
C4
Parallel/Serial
Mode
Control
VSS
OE
MCA
MCB
CKD
2/4S
VDD
Figure 1 - Functional Block Diagram
2-125
CMOS
61
62
63
64
65
66
67
1
68
2
3
4
5
6
7
9
8
S7
S6
S5
S4
S3
S2
S1
S0
VSS
VDD
P7
P6
P5
P4
P3
P2
P1
MT9085
DFPo
VDD
17
53
VDD
VSS
18
52
VSS
S14
19
51
C16i
S15
20
50
F0i
S16
21
49
F0o
S17
48
S18
22
23
47
DFPo
CFPo
S19
24
46
IC
S20
25
45
IC
S21
26
44
MCA
VSS
S22
S23
S24
S25
S26
S27
VSS
VDD
S28
S29
S30
S31
CKD
C4i
OE
2/4S
43
54
42
C4o
S13
41
55
40
C2o
15
16
39
56
38
14
37
NC
S11
S12
36
57
35
13
34
VSS
S10
33
58
32
12
31
MCB
S9
30
P0
59
29
60
11
28
10
S8
27
VSS
Figure 2 - Pin Connections
2-126
CMOS
MT9085
Pin Description
Pin #
Name
1
VSS
2-9
S0-S7
10
VSS
11-16
Description
Ground.
Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial
bus streams; inputs in serial to parallel mode (MCA=0), and outputs in parallel to serial mode
(MCA=1). Data rate on the serial streams can be selected to be 2.048 Mbit/s (2/4S=0) or 4.096
Mbit/s (2/4S=1). Refer to Figures 3, 4 and 5 for functional timing information.
Ground.
S8-S13 Serial Input/Outputs. See description for pins 2 - 9 above.
17
VDD
Supply Input. +5V.
18
VSS
Ground.
19-20 S14-S15 Serial Input/Outputs. See description for pins 2 - 9 above.
21-26 S16-S21 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial
bus streams which are configured as inputs in serial to parallel mode (MCA =0), and outputs in
parallel to serial mode (MCA=1). Data is clocked at 2.048 Mbit/s (2/4S = 0). These input/
outputs are inactive when the device is configured for 4.096 Mbit/s operation (2/4S=1).
27
VSS
Ground.
28-33 S22-S27 Serial Input/Outputs. See description for pins 21-26 above.
34
VSS
Ground.
35
VDD
Supply Input +5V.
36-39 S28-S31 Serial Input/Outputs. See description for pins 21-26 above.
40
CKD
Clock Delay (Input). Control input which configures internal device timing.
CKD=0 Internal master counter is reset at the system frame boundary established by the
frame pulse (F0i).
CKD=1 Internal master counter is reset one C16 clock period after system frame boundary.
All data input/output will be delayed by one C16 clock period.
Timing for data input/output and for OE is affected by the level asserted on CKD. The relative
phase between the frame boundary established by F0i and output signals F0o, C2o, C4o,
DFPo, DFPo and CFPo is also affected by the state of the CKD input. See descriptions
pertaining to each specific pin for more information.
41
C4i
4.096MHz Clock Input. The 4.096 MHz clock signal must be phase locked to the 16.384 MHz.
clock. The falling edge of C4i is used to clock in the frame pulse (F0i).
42
OE
Output Enable (Input). When low, output data bus (serial or parallel) is actively driven.
When set high, the output bus drivers are disabled. In serial to parallel mode, the outputs are
disabled immediately after OE is taken High. See Figures 6 and 21 for timing information
pertaining to parallel to serial mode.
43
2/4S
2.048/4.096 Mbit/s Select (Input). Selects the data rate for the time division, multiplexed
serial streams. When tied low, the data rate is 2.048 Mbit/s. When tied high, the data rate is
4.096 Mbit/s.
44
MCA
Mode Control-A (Input). The device will perform a serial to parallel conversion when this
input is tied low. When the input is tied high, the device operates in the parallel to serial mode.
45
IC
Internal Connection. Must be tied to VSS for normal device operation.
46
IC
Internal Connection. Should be left unconnected.
47
CFPo
Connect Memory Frame Pulse (Output). Framing signal with a nominal 8 kHz frequency;
goes low 71 (CKD=0) or 68 (CKD=1) C16 clock cycles before the frame boundary established
by F0i. The signal is used by the connection memory in a typical 1k or 2k switch configuration.
See Figure 15 for timing information.
2-127
MT9085
CMOS
Pin Description (continued)
Pin #
Name
Description
48
DFPo
Data Memory Frame Pulse (Output). Framing signal with nominal 4 kHz frequency; changes
state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i.
This signal is a complement of DFPo. See Figure 15 for timing information. The signal is used
by SMXs (MT9080s) making up the Data Memory in a typical 1k or 2k switch configuration.
49
F0o
Framing Type 0 Signal (Output). 8 kHz framing signal output by the PAC to indicate the
frame boundary synchronized to C16. This framing signal is aligned with C4o and is output by
the PAC for use by other devices in a typical switch configuration. Refer to Figures 4 and 5 for
functional timing information.
50
F0i
Framing Type 0 Signal (TTL compatible input). This input signal establishes the frame
boundary for the serial input/output streams. The first falling edge of C4i following the falling
edge of F0i establishes the frame boundaries. Refer to Figure 13 for timing information.
51
C16i
16 MHz Clock Input. The 16.384 MHz clock signal input at this pin must be phase-locked to
the 4.096 MHz clock input at C4i. See Figure 13 for timing information.
52
VSS
Ground.
53
VDD
Supply Input. +5V.
54
DFPo
Data Memory Frame Pulse (Output). 4 kHz framing signal; changes state 64 (CKD=0) or 65
(CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a
complement of DFPo. See Figure 15. The signal is used by SMXs (MT9080s) making up the
Data Memory in a typical 2k switch configuration.
55
C4o
4.096 MHz Clock Output. This is a 4.096 MHz clock signal derived from the 16 MHz master
clock input at C16. The falling edge of C4o occurs in the middle of the regenerated frame
pulse output at F0o. Refer to Figures 4 and 5 for functional timing information.
56
C2o
2.048 MHz Clock Output. This is a 2.048 MHz clock signal derived from the 16 MHz master
clock input. The rising edge of this clock signal occurs in the middle of the regenerated frame
pulse output at F0o. Refer to Figures 4 and 5 for functional timing information.
57
NC
No Connection.
58
VSS
Ground.
59
MCB
Mode Control-B (Input). This control input performs two different functions, depending on the
state of MCA pin.
In parallel to serial mode (MCA=1), MCB defines which clock edge latches in the data.
MCB=0
Data on the parallel bus is latched into the device with the every second falling
edge of C16. See Figure 6.
MCB=1
Data on the parallel bus is latched into the device with every alternate positive
clock edge.
In serial to parallel mode (MCA=0), the MCB pin controls the state of the parallel bus driver as
follows:
MCB=0
The output drivers are enabled for only half the timeslot. The data is clocked
out on the first falling edge within the timeslot and disabled on the next falling
edge. See Figure 7.
MCB=1
The parallel data bus output drivers are enabled for the duration of the channel
timeslot (two C16 Clock Periods). The data is clocked out on the first positive
edge within a timeslot and disabled on the last edge.
60-67
P0-P7
Parallel Input/Output Data Bus. This 8 bit data bus is an output in serial to parallel mode
(MCA=0), and an input in parallel to serial mode (MCA=1). Data is clocked in and out of the
port by the C16 clock. The state of the CKD pin determines the relative phase of the critical
clock edges with respect to the frame pulse. All inputs/outputs have internal pullups. Refer to
Figures 6 and 7 for functional timing information.
68
VDD
2-128
Supply. +5V.
CMOS
MT9085
512 C4 Cycles
C4
F0
S0-S31
2/4S = 0
S0-S15
2/4S = 1
0
1
0
1
2
31
3
0
63
0
Figure 3 - Serial Input/Output Functional Timing
Frame Boundary Established by F0i
C16i
C4o
C2o
F0o
Serial I/O
2 Mbit/s
Serial I/O
4 Mbit/S
Ch. 31 Bit 1
Ch. 31 Bit 0
Ch. 63 Bit 2
Ch. 63 Bit 1
Ch. 63 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 0 Bit 6
Ch. 0 Bit 5
Figure 4 - Channel and Frame Alignment (CKD = 0)
Frame Boundary Established by F0i
C16i
C4o
C2o
F0o
Serial I/O
2 Mbit/s
Serial I/O
4 Mbit/S
Ch. 31 Bit 1
Ch. 31 Bit 0
Ch. 63 Bit 2
Ch. 63 Bit 1
Ch. 63 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 0 Bit 6
Ch. 0 Bit 5
Figure 5 - Channel and Frame Alignment (CKD = 1)
2-129
MT9085
CMOS
Frame Boundary established by F0i
64 Cycles
C16i
CKD=0
Serial
Output
S0-S31
Ch. 31, Bit 0
Ch. 0, Bit 7
Ch. 1, Bit 7
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
Parallel AAA
AAA
AAA
AAA
AAAAAAAAAAA
AAAA
AAA
AAAC S AAAA
AAAAAAAA
AAA C S AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAAAAA
AAAAAAAAAAA
AAAAAAA
Input AAA
1 0 AAAAAAAAAAA C1S1 AAAAAAAAAAA C1S2 AAAAAAAAAAA C1S3
AAA 0 31AAAA
AAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
MCB=0 AAA
OE
Parallel
Input
MCB=1
C1S1
C1S2
C1S3
AAAAAAAAAAA
AAAAAAAAAAA
AAA C S
AAAAAAA
C2S0 AAAA
AAAA
2 1
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
C1S4
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
C2S1
AAAAAA
AAAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAA
AAAA
AAAA
AAAAAA
AAC S AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAAAAA
AAAAAAAA
AAAA
AA
0 31AAAAAAAAAAAA C1S0 AAAAAAAAAAA C1S1 AAAAAAAAAAA C1S2AAAAAAAAAAAAC1S3
AAAAAA
AAAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAAA
AAAAAA
AAAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAA
C2S0 AAAA
AAAA
AAA C 2
AAAAAAAA
AAA
AAAAAAAA
AAAAAAA
OE
C1S1
C1S2
C1S3
C1S4
C 2S1
CKD=1
Serial
Output
S0-S31
Parallel
Input
MCB=0
OE
Parallel
Input
MCB=1
Ch. 31, Bit 0
Ch. 0, Bit 7
AAAAAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAA
AA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAA
AAA C1S0AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAA
AAAAAAA
C0S31 AAAA
C1S1 AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAA C1S2
AAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAA
AAAAAAA
C1S1
C1S2
C1S3
AAAAAAAAAAA
AAAA
AAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAA
AAA
AAA
C1S3 AAAA
AAAA
AAAA
AAA
AAAA
AAA
AAAAAAAAAAA
AAAAAAA
C1 S 2
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAAAAAA
C2S0AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
C2S1
C1S4
AAAA
AAAA
AAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAA
AAA C S AAAA
AAAAAAAA
AAAAAAAA
AAAA C S AAAA
AAAAAAAA
AAAAAAA
AAA C S
AAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA C0S31 AAAAAAAA
AAAAAAA
AAA 1 0AAAAAAAA
AAAAAAAA
AAAA 1 1 AAAAAAAA
AAAAAAA
AAA 1 2
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAA
C1S1
OE
Ch. 1, Bit 7
C1S3
AAAA
AAAAAAA
AAAAAAA
AAAA
AAAAAAAA
AAAAAAA
AAA C S AAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAA
AAA 1 3 AAAAAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAAAAAA
AAAA
AAAAAAAA
AAAA
AAAA C S AAAA
AAAAAAAA
AAAA
AAAA 2 0 AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
C1S4
C2S1
Notes:
C XSY - on the parallel inputs indicates data closed in with the edge shown will be clocked out on Serial Stream Y, Channel X.
Arrows in the row marked OE indicate the clock edge which latches in the state of the OE pin. CXSY written below the arrow indicates the
serial output channel affected by the OE signal. For example, the level on OE clocked in with edge marked C1S1 will enable or disable the
serial output drivers for stream 1 during channel 1.
Figure 6 - Functional Data I/O Timing in Parallel to Serial Mode (MCA = 1)
2-130
CMOS
MT9085
Frame Boundary established by F0i
C16
Serial
Input
S0-S31
Parallel
Output
MCB=0
CKD=0
Ch.31
Bit 0
AAAAAAA
AAA
AAAAAAAA
AAA
AAA
AAAAAAAAAAA
AAAA
AAA
AAAAAAAAAAA
AAA
AAAAAAA
AAAA
AAA
AAAAAAAA
AAA
AAA
AAAAAAAAAAA
AAA
AAA
AAA
Parallel AAAAAAAA
AAAA
Output AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
MCB=0 AAAA
AAAA
AAAA
CKD=1 AAAAAAAA
Parallel
Output
MCB=1
CKD=0
Parallel
Output
MCB=1
CKD=1
Ch.0
Bit 6
Ch. 0, Bit 7
C31S0
AAAAAAAAAAAA
AAA
AAAAAAAAAAAA
AAA
AAA
AAAAAAAAAAAA
AAA
AAAAAAAAAAAA
A
AAA
AAAA
AAAAAAAA
AAAAAAA
AA
AAA
AAA
AAAAAAAAAAA
AAA
AAA
AAA
AAA
AAAA
AAAAAA
AAAA
AAAA
AA
AAA
AAAA
AAAAAAAA
AA
C30S31 AAA
AAAAAAAA
AAAAAAAA
AA
AAA
AAAA
AAAA
AA
AAA
AAAA
AAAAAAAA
AA
AAA
AAAA
AAA
AAAAAAAAAAAA
AAAA
AA
C30S31
C31S0
C 31S0
C30S31
C31S1
AAAAA
AAAAAAA
AAAAAAAAAAA
AA
AAA
AAAAAAAAAAAAAA
AAA
AAAAAAAAAAAAAAA
A
AAAAAAA
AAAA
AAAAAAAAAAA
AA
AAA
AAAAAAAAAAAAAA
AAA
AAA
AAA
AAAAAAA
AAAA
AAAAAAAA
AAAAAA
AA
AAA
AAAA
AA
AAAAAAA
AAAAAAAA
AAAAAAAA
AA
AAAAAAA
AAAA
AA
AAA
AAAA
AAAAAAAA
AA
AAA
AAAA
AAAA
AAAAAAAAAAAAA
AAAA
C31S1
AAAAAAA
AA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAAAAAAAA
AAA
A
AAAAAAAAAAAAAA
A
AAAAAAA
AA
AAAAAAAA
AAAAAAA
AAA
AAA
AAAAAAAAAAAAAA
A
AAA
AAA
AAAAAAA
AAAA
AAAAAAAA
AAAAAA
AA
AAA
AAAA
AA
AAAAAAA
AAAAAAAA
AAAAAAAA
AA
AAAAAAA
AAAA
AA
AAA
AAAA
AAAAAAAA
AA
AAA
AAAA
AAAA
AAAAAAAAAAAAA
AAAA
C31S1
C31S0
C31S2
C31S2
C31S2
C31S1
C31S3
AAAAAAAAAAA
A
AAA
AAAAAAAAAAA
A
AAA
A
AAA
AAAAAAAAAAA
A
AAA
AAAAAAAAAAA
A
AAA
AAAA
AAAA
AAAAAAAAAAA
A
AAA
A
AAA
AAAAAAAAAAA
AAA
AAA
AAA
AAAAAAA
AA
AAAAAAAA
AAAAAAAA
AA
AAA
AAAA
AA
AAAAAAA
AAAAAAAA
AAAAAAAA
AA
AAAAAAA
AAAA
AA
AAA
AAAA
AAAAAAAA
AA
AAA
AAAA
AAAA
AAAAAAAAAAAAA
AAAA
C31S3
AAA
AAA
AAA
AAA
AAA
AAA
AAA
C31S3
C31S2
C31S3
Note: CxSY - indicates data being output is sourced from Serial Stream Y, Channel X
Figure 7 - Functional Data I/O Timing in Serial to Parallel Mode (MCA = 0)
2-131
MT9085
CMOS
Functional Description
Contiguous channels clocked into the device are
output on the serial streams in an interleaved
manner on each of the serial outputs. For example
when the device is configured for 2.048 Mbit/s data
rate, the first 32 parallel channels clocked into the
device will be clocked out during channel 0 on serial
streams 0 to 31. Channel 1 on serial streams 0 to 31
will contain data from the next 32 timeslots. On any
single serial stream, consecutive output channels
are sourced from every 32nd parallel input channel
(see Figures 6 and 8).
When the device is
configured for 4.096 Mbit/s serial output operation,
contiguous channels on the serial streams are
sourced from every 16th parallel input channel.
The MT9085 Parallel Access Circuit (PAC) is a 68
pin monolithic device. It interfaces a parallel 8 bit,
time division, multiplexed bus to 32 or 16 time
division multiplexed serial streams. The device can
be configured to perform either parallel to serial
conversion or serial to parallel conversion. A single
PAC device can handle 1024 channels. The data on
the parallel bus is in a format suitable for interfacing
with the Mitel MT9080 Switch Matrix Module (SMX).
The data rate on the serial streams can be selected
to be 2.048 or 4.096 Mbit/s.
The serial input/output format conforms to the
ST-BUS requirements when the data rate is 2.048
Mbit/s (see Figure 3).
The ST-BUS is a
time-division, multiplexed serial bus with 32, eight bit
channels per frame.
Frame boundaries are
delinated by the frame pulse. Data on the serial
streams is clocked in and out with the C16i clock.
Data on the eight bit parallel bus is clocked into the
device with the C16 clock. The level asserted on the
MCB input specifies whether the data is clocked into
the device on the falling edge or the rising edge of
C16. The relative phase of the critical edge with
respect to the system frame boundary is defined by
the level asserted on the CKD pin as illustrated in
Figure 16. The flexibility in input timing permits the
PAC to be easily interfaced to the SMX in 1024 and
2048 switching applications.
Refer to the
applications section of this data sheet for more
details.
When the device is configured for 4.096 Mbit/s data
rate operation, the first 16 (S0-S15) of the 32 serial
streams are used.
Each of the 16 time-division
multiplexed serial streams is made up of 64
channels. Data is clocked in or out with the C16i
clock.
The MT9085 can be configured to perform parallel to
serial conversion by tying the MCA input high.
The delay through the PAC is approximately one
ST-BUS channel time when the device is operated in
2.048 Mbit/s mode, i.e., any specific channel clocked
into the device will be clocked out one ST-BUS
channel later. In the 4.096 Mbit/s mode, the delay is
equal to eight C4 clock cycles.
Data on the eight bit parallel bus (P0-P7) is clocked
into the device with the C16i clock. It is clocked out
on the serial streams at either 2.048 Mbit/s (2/4S =0)
or at 4.096 Mbit/s (2/4S=1). See Figures 16, 17 and
19 for timing information.
Serial output channel timeslots can be tri-stated by
setting OE high during a specific parallel channel
timeslot. The timing for OE is described in Figures 6
and 21. Note that the level asserted on MCB affects
the operation of OE.
Parallel To Serial Conversion
Parallel to Serial Conversion
CH. 2
CH. 1
CH. 0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Bit #
TS64
TS32
TS0
TS65
TS33
•
•
•
•
TS95
TS TS
0
1
0 0
TS TS TS
31 32 33
0 0 0
1
1
1
1
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
P2
2
2
2
2
2
2
2
P3
3
3
3
3
3
3
3
P4
4
4
4
4
4
4
4
TS63
TS31
S31
P5
5
5
5
5
5
5
5
P6
6
6
6
6
6
6
6
P7
7
7
7
7
7
7
7
Figure 8 - PAC Operation at 2.048 Mbit/s
•
•
•
•
P1
•
•
•
•
P0
TS1
S0
S1
Serial to Parallel Conversion
2-132
TS TS
63 64
0 0
•
•
•
•
PAC
CMOS
MT9085
Serial to Parallel Conversion
The MT9085 can be configured to perform serial to
parallel conversion by tying the MCA pin low. A
single PAC will accept 1024 channels on the 32 or 16
serial streams and output the data onto the parallel
bus as illustrated in Figure 8.
The data on the serial input streams can be clocked
in at 2.048 Mbit/s or at 4.096 Mbit/s by setting the
appropriate level on the 2/4S pin. See Figures 16
and 17 for timing details.
Data is clocked out on the parallel bus with the C16
clock (see Figure 18 for timing details). The parallel
output bus will be actively driven for two C16 clock
periods when MCB is tied high. Data is output with
every second rising clock edge. Setting MCB low
will enable the output drivers for only one C16 clock
period in any specific parallel channel timeslot. The
actual phase relationship between the system frame
boundary and the parallel output timeslots is affected
by the level asserted on the CKD input (see Figure
7). The flexibility in output timing permits the PAC to
be easily interfaced to the SMX in 1024 and 2048
channel configurations. Refer to the applications
section of this data sheet for more information.
The delay through the PAC is approximately one
ST-BUS channel when the device is configured for
2.048 Mbit/s serial rate. In the 4.096 Mbit/s mode,
the delay is equal to approximately eight C4 clock
cycles.
Timing and Framing Signals
The PAC requires two clock signals. A 16.384 MHz
master clock (C16) is used to clock data in and out of
the device on the parallel bus. A 4.096 MHz clock
(C4i), phase locked to C16i, clocks in the frame
pulse. The positive C16i edge immediately after the
C4i falling edge which clocks in F0i defines the
internal frame boundary. The two separate clock
inputs permit synchronization of the MT9085 to
system timing in which the frame pulse is derived
from a 4.096 MHz clock.
The PAC generates all framing signals necessary to
construct a 1024 channel or a 2048 channel switch
matrix using the SMX. The DFPo signal is used as
a framing signal for the SMXs operated as the Data
Memory. The CFPo is used to synchronize Connect
Memory timing in a typical 1K or 2K switch
application (refer to the application section in this
data sheet for more information). The timing of both
DFPo and CFPo signals is affected by the level
asserted on the CKD input as shown in Figure 15.
The PAC outputs ST-BUS timing signals, F0o, C2o
and C4o derived from C16i. The phase relationship
between the frame boundary established by F0i and
F0o is illustrated in Figures 4 and 5.
Applications
1024 Channel Digital Time-Space Switch
A 1024 channel serial time-space digital switch
design is illustrated in Figure 9.
The main switching function is accomplished using
two MT9080s (SMXs). One SMX is operated in the
Data Memory mode and the second serves as the
Connection Memory. Refer to the SMX data sheet
for more information on this configuration. The serial
to parallel conversion function is provided by a PAC
configured for 2.048 Mbit/s operation (2/4S = 0). The
MCB input in this PAC is tied high to ensure data
output by the PAC meets SMX input setup and hold
requirement. PAC #2 performs the parallel to serial
function; MCA is set high. The MCB input in this
device is set low to allow data to be clocked in with
the falling edge of C16.
The main timing source generates a 16.384MHz
clock phase locked to a 4.096MHz clock. The
framing signal input to PAC#1 at F0i should meet the
requirements specified in Figure 13 of this data
sheet. In some applications where a master 16.384
MHz oscillator is used for system timing, the C4i and
F0i clocks could be derived directly from it. In
applications where a 4.096 MHz clock signal is
available, the 16.384 MHz clock can be generated
using a phase-lock loop.
Framing signals for both the SMXs are generated by
PAC #1. DFPo is connected to FP input of the Data
Memory. CFPo is connected to the FP input of the
Connection Memory.
PAC #2 is configured to
perform parallel to serial conversion.
The DFPo and CFPo signals ensure that all timing
requirements necessary to interface the SMXs with
the PACs are met while input and output serial
frames are aligned.
The maximum delay through the switch is
approximately one frame plus two serial channels
when SMX#1 is operated in Data Memory Mode-1.
When the SMX is operated in Data Memory Mode-2,
the maximum delay is two frames. In this case, the
channels are double buffered; frame integrity is
maintained for all switching configurations.
2-133
MT9085
CMOS
number Hex 0082. In order to program the matrix for
switching, the input channel address is written to the
Connection Memory address corresonding to the
serial output channel. The bits controlling features
such as OE, ME, and Mz should be set or reset
accordingly at the same time. For example. if
channel 4 on stream 2 is to be switched to channel
10 on stream 1, the following binary word is written
to Connection Memory address corresponding to the
output channel (Hex 0141):
In the example configuration shown in Figure 9 the
OE pin of PAC #2 is connected to D10 on the
Connection Memory. Setting bit 10 high in the
Connection Memory location corresponding to a
serial channel timeslot will result in the output driver
for the specific stream being disabled during that
serial channel timeslot. D11 is connected to the ME
input of SMX1 and D12 is connected to a mode
select pin (Mz). Consequently, the levels on these
outputs can be set high or low by writing to the
appropriate memory location corresponding to the
selected output channel. The mapping of the control
functions on to Connection Memory data bits is
illustrated in Figure 10.
X X X 0
0 0 0 0 1 0 0 0 0 0 1 0
Stream Address
The data on the PAC serial streams is byte
interleaved as described in the Functional
Description section in this data sheet. The SMX
channel number corresponding to the channel on the
serial streams can be determined directly by
specifying the serial channel and stream number in
binary as shown in Figure 11. For example, serial
channel 4, stream 2 corresponds to SMX channel
Channel Address
Output Enable
Message Enable
DM-1/DM-2
Unused
Timing
Source
From Timing Source
C16
F0 C4 C16
C4
F0
F0i C4i C16i
PAC#1
S/P
S0
S31
•
•
•
•
S0
•
•
•
•
S31
F0i C4i C16i
SMX #1
DM - 1/2
P0-P7
8
D0-D7o
D0-D7i
C16
CK
FP
Mz
DFPo
CFPo
2/4S
My
•
•
•
•
S0
S31
CS
DS
OE CKD MCA MCB
ODE
S0
•
•
•
•
S31
2/4S
P0-P7
Mx
DATA
MEMORY
R/W
+5
PAC#2
P/S
8
OE CKD MCA
MCB
A0-A9 ME
+5
+5
10
D12
D0-D9 D11
D10
SMX #2
CM - 1
+5
+5
Mz
CD
D0-D15
R/W
CS
DS
CK
DTA
C16
CONNECTION
MEMORY
A0-A15
FP
ODE
Mx
My
NOTE:
MPU Interface
Connect all inputs not shown to VSS
Figure 9 - 1024 Channel Switch Matrix Using the PAC and SMX
2-134
MT9085
CMOS
15
14
13
12
11
10
9
8
Not
Used
7
6
5
4
3
Serial Channel
Number
2
1
0
Stream
Address
OE - Output Enable
ME - Message Enable
Mode Control - DM-1 or DM-2
Figure 10 - Mapping of Data Memory and PAC Control Functions on Connection Memory Data Bits
4
Unused
3
2
1
0
Channel
Address
4
3
2
1
0
Stream
Address
Ex. Serial Stream 4, Channel 3 Corresponds to SMX Channel Number 100 (Hex 0064)
Figure 11 - Decoding SMX Channel Number from Serial Stream & Channel Address
1024 Switch Configuration
2048 Channel Digital Space-Time Switch
Application
A 2048 channel serial time-space digital switch
design is illustrated in Figure 12.
The main switching function is accomplished using
three MT9080s (SMXs). Two SMXs function as the
data memory, while the third is operated in Connect
Memory mode. Refer to the SMX data sheet for
more information on this configuration. The Serial to
parallel conversion for 2048 channels is handled by
two PACs. PAC #1a and PAC #1b.
Both are
configured for 2.048 Mbit/s operation (2/4S=0). The
MCB input is tied low in both devices. The parallel
data bus on each of the devices will be actively
driven for one C16 clock period. The CKD input is
set low in one of the devices and set high in the
other. This will cause the output timing of the two
PACs to be off set by one C16 clock period.
Consequently, the parallel output of one device will
be disabled while the other is active.
The parallel to serial conversion is also
accomplished with two PACs.
Data from the
common SMX parallel bus is clocked into each PAC
in alternate clock periods.
The timing source generates a 16.384 MHz clock
phase locked to a 4.096 MHz clock. The framing
signal input to PAC #1a at F0i should meet the
requirements specified in this data sheet. In some
applications where a master 16.384 MHz oscillator is
used for system timing, the C4i and F0i clocks could
be derived directly from it.
The DFPo and DFPo generated by PAC #1a are
used to switch the mode of operation of the Data
Memory SMXs between Counter and External
modes and also serve as the frame pulse for the two
SMXs. Because DFPo and DFPo are complementary
signals, one of the two SMXs is operated in the
Counter mode while the second one is operated in
the External mode. The states of the other control
inputs, R/W and ODE, are changed accordingly.
The SMX configured as the Connection Memory, is
fed a frame pulse from PAC #1b. The phase
alignment of CFPo with respect to DFPo ensures
that timing requirements for proper operation of the
SMXs are met. Refer to the SMX data sheet for
more information on the timing requirements.
The maximum delay through the switch is two
frames. Channels are double buffered and frame
integrity
is
maintained
for
all
switching
configurations.
For more information, see Mitel’s Application Note
MSAN-135, “Design of Large Digital Switching
Matrices using the SMX/PAC“ (in this data book)
and Application Sheet MSAS-62 “16.384 MHz Clock
Generation for SMX/PAC“ (available from Mitel).
2-135
MT9085
CMOS
Timing
Source
M4
From Timing Source
C16
C4
MF
F0 C4 C16
F0
F0i C4i C16i
SMX #1
CNT/EXT
PAC#1a
S/P
S0
•
•
•
S31 •
S0
•
•
•
•
S31
8
D0-D7i
P0-P7
C16
D0-D7o
CK
D0-D7i
C16
+5
Mx
My
FP
Mz
2/4S
R/W
CS
R/W
OE CKD MCA MCB
DS
A0ODE A10 ME
DFPo
D0-D7o
CK
FP
Mz
DFPo
F0i C4i C16i
PAC#2a
P/S
SMX #2
CNT/EXT
Mx
8
S0
•
•
•
•
S31
2/4S
P0-P7
+5
My
CS
DS
A0ODE A10 ME
•
•
•
•
S0
S31
OE CKD MCA MCB
+5
F0 C4 C16
F0i C4i C16i
F0 C4 C16
D12 D0-D10 D11
F0i C4i C16i
PAC#1b
S/P
S0
•
•
S31 ••
S0
•
•
•
•
S31
SMX #3
CM - 2
8
P0-P7
FP
CFPo
P0-P7
ODE
Mx
+5
My
+5
CONNECTION
MEMORY
PAC#2b
P/S
8
OE CKD MCA MCB
CD
D0-D15
R/W
CS
DS
CK
DTA
C16
OE CKD MCA MCB
A0-A15
Mz
2/4S
+5
+5
MPU Interface
NOTE:
Connect all inputs not shown to VSS
Figure 12 - 2048 Channel Switch Matrix Using the PAC and SMX
2-136
S0
•
•
•
•
S31
2/4S
•
•
•
•
S0
S31
MT9085
CMOS
Absolute Maximum Ratings* - Voltages are with respect to Ground (VSS) unless otherwise stated.
Parameter
Symbol
Min
Max
Units
-0.3
7
V
1
VDD-VSS
2
Voltage on Digital Inputs
VI
VSS-0.3
VDD+0.3
V
3
Voltage on Digital Outputs
VO
VSS-0.3
VDD+0.3
V
4
Current at Digital Outputs
IO
40
mA
5
Storage Temperature
TS
125
°C
2
W
-40
6 Package Power Dissipation
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Operating Temperature
TOP
-40
70
°C
2
Positive Supply
VDD
4.5
5.5
V
3
Input Voltage
VI
0
VDD
V
Test Conditions
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
50
mA
Test Conditions
Outputs unloaded
1
Supply Current
IDD
2
Input High Voltage - all pins
except C4i, F0i, S0-S31
VIH
0.7VDD
Input Low Voltage - all pins
except C4i, F0i, S0-S31
VIL
0
Input High Voltage - C4i, F0i,
S0-S31
VIH
2.0
5
Input Low Voltage - C4i, F0i,
S0-S31
VIL
0.8
V
6
Input Leakage Current
IIL
±10
µA
7
Output Low Current S0-S31
IOL
8
mA
VOL=0.4V
Output Low Current all outputs
except S0-S31
IOL
8
mA
VOL=0.3VDD
Output High Current S0-S31
IOH
8
mA
VOH=2.4V
Output High Current all outputs
except S0-S3
IOH
8
mA
VOH=0.7VDD
High Impedance Leakage
IOZ
10
µA
Input Pin Capacitance
Ci
10
pF
3
4
I
N
P
U
T
S
8
9
10
11
12
O
U
T
P
U
T
S
V
0.3VDD
V
V
13
Output Pin Capacitance
Co
10
pF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VDD=5.0V ±10 %
2-137
MT9085
CMOS
AC Electrical Characteristics†- Input Frame Pulse and Clock Timing (See Figure 13) Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
C16 Clock Period
tC16P
60
61
62
ns
2
C4 Clock Period
tC4P
219
244
269
ns
3
C16 Pulse Width Low
tC16L
25
ns
4
C16 Pulse Width High
tC16H
25
ns
5
C4 Setup Time
tC4S
-10
25
ns
6
Frame Pulse Setup Time
tFPS
5
200
ns
7
Frame Pulse Hold Time
tFPH
5
Test Conditions
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
ST-BUS Frame Boundary
tC16H
tC16P
tC16L
C16i
tC4S
C4i
tC4P
F0i
tFPS
tFPH
Figure 13 - ST-BUS Frame Pulse and Clock Timing
AC Electrical Characteristics† - Output Clocks and Frame Pulse Timing (See Figure 14) Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Frame Pulse Delay
tFPD
0
31
ns
CL=85pF
2
C4 Clock Delay
tC4D
0
28
ns
CL=85pF
3
C2 Clock Delay
tC2D
0
ns
CL=85pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
C16i
tFPD
tFPD
F0o
tC4D
tC4D
tC4D
C4o
tC2D
C2o
Figure 14 - F0o, C4o and C2o Output Clock Timing
2-138
MT9085
CMOS
AC Electrical Characteristics† - Data Memory and Connect Memory Frame Pulse (See
Figure 15) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Data - Memory Frame Pulse
Delay
tDFPo
0
37
ns
CL=85 pF
2
Connection - Memory Frame
Pulse Delay
tCFPo
0
30
ns
CL=85 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
ST-BUS Frame Boundary
Established by F0i
ST-BUS Frame Boundary
Established by F0i
64 C16
Cycles
64 C16
Cycles
71 C16 Cycles
C16i
CKD=0
DFPo
tDFPo
tDFPo
tDFPo
tDFPo
DFPo
tCFPD
tCFPD
CFPo
68 C16
Cycles
CKD=1
DFPo
tDFPo
tDFPo
tDFPo
tDFPo
DFPo
tCFPo
tCFPo
CFPo
Figure 15 - DFPo and CFPo Output Timing
2-139
MT9085
CMOS
AC Electrical Characteristics† - Serial Input and Output Timing in 2 MHz Mode (2/4S=0)
(See Figure 16) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Serial Input Setup Time
tSS
0
ns
2
Serial Input Hold Time
tSH
24
ns
3
Serial Output Delay
Active to Active
High Impedance to Active
Active to High Impedance
tSD
47
47
44
ns
ns
ns
Test Conditions
CL=150pF
CL=150pF
CL=150pF
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Serial Bit Cell
C4i
C16i
tSH
tSS
S0i-S7i
(CKD=0)
S0i-S7i
(CKD=1)
tSS
tSH
S0o-S7o
(CKD=0)
tSD
tSD
S0o-S7o
(CKD=1)
tSD
Note:
1)
The phase relationship of C4i and C16i depends on the user’s timing source (see Fig. 13 for device related contstraints).
2) Timing measurements for inputs are referenced to/from a low voltage of 0.8V and a high voltage of 2.0V.
Measurements for outputs are referenced to/from a low voltage of 0.4V to a high voltage of 2.4V
Figure 16 - Serial Input and Output Timing in 2 Mbit/s Mode (2/4S=0)
2-140
CMOS
MT9085
AC Electrical Characteristics† - Serial Input and Output Timing in 4 MHz Mode (2/4S=1)
(See Figure 17) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Serial Input Setup Time
tSS
0
ns
2
Serial Input Hold Time
tSH
24
ns
3
Serial Output Delay
Active to Active
High Impedance to Active
Active to High Impedance
tSD
47
47
44
Test Conditions
ns
ns
ns
CL=150pF
CL=150pF
CL=150pF
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Serial Bit Cell
C4i
C16i
tSH
tSS
tSH
tSS
S0i-S7i
(CKD=0)
tSS
tSH
tSS
tSH
S0i-S7i
(CKD=1)
tSD
tSD
S0o-S7o
(CKD=0)
tSD
tSD
S0o-S7o
(CKD=1)
Note:
1)
The phase relationship of C4i and C16i depends on the user’s timing source (see Fig. 13 for device related contstraints).
2)
Timing measurements for inputs are referenced to/from a low voltage of 0.8V and a high voltage of 2.0V.
Measurements for outputs are referenced to/from a low voltage of 0.4V to a high voltage of 2.4V
Figure 17 - Serial Input and Output Timing in 4 Mbit/s Mode (2/4S=1)
2-141
MT9085
CMOS
AC Electrical Characteristics† - Parallel Output Timing (See Figure 18) - Voltages are with respect
to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Parallel Output Delay
tPD
28
ns
C L=85pF
2
Parallel Output Delay
High Impedance to Active
tPZA
28
ns
C L=85pF
3
Parallel Output Delay
Active to High Impedance
tPAZ
28
ns
C L=85pF
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
C16i
P0 to P7
MCB=1
tPD
tPD
90%
P0 to P7
MCB=0
NOTE:
10%
tPAZ
tPZA
tPZA
See Figure 7 for functional timing information
Figure 18 - Parallel Output Timing
AC Electrical Characteristics† - Parallel Input Timing (See Figure 19) - Voltages are with respect to
Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Parallel Input Setup Time
tPS
0
ns
2
Parallel Input Hold Time
tPH
5
ns
Test Conditions
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
C16i
tPH
tPH
tPS
tPS
P0 to P7
MCB=1
tPH
tPS
tPS
P0 to P7
MCB=0
NOTE:
See Figure 6 for functional timing information
Figure 19 - Parallel Input Timing
2-142
tPH
CMOS
MT9085
AC Electrical Characteristics† - Output Enable Timing, Serial to Parallel Mode (See
Figure 20) - Voltages are with respect to Ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Parallel Output Delay
Active to High Impedance
tPAZ
23
ns
CL=85pF
2
Parallel Output Delay
High Impedance to Active
tPZA
25
ns
CL=85pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
OE
90%
P0 to P8
Output
10%
tPZA
tPAZ
Figure 20 - OE Timing in Serial to Parallel Mode
AC Electrical Characteristics† - Output Enable (OE) Timing, in Parallel to Serial Mode
(See Figure 21) - Voltages are with respect to Ground (VSS ) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
1
OE Setup Time
tOES
2
ns
2
OE Hold Time
tOEH
10
ns
Test Conditions
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Frame Boundary
Established by F0i
C16i
tOES
tOES
OE
CKD=0
tOEH
tOEH
tOES
tOES
OE
CKD=1
tOEH
tOEH
Figure 21 - OE Timing in Parallel to Serial Mode
2-143
MT9085
NOTES:
2-144
CMOS
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