ONSEMI 74VCX16374DTR

74VCX16374
Low−Voltage 1.8/2.5/3.3V
16−Bit D−Type Flip−Flop
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74VCX16374 is an advanced performance, non−inverting
16−bit D−type flip−flop. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCX16374 is byte controlled, with each byte functioning identically,
but independently. Each byte has separate Output Enable and
Clock Pulse inputs. These control pins can be tied together for a full
16−bit operation.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.
The 74VCX16374 consists of 16 edge−triggered flip−flops with
individual D−type inputs and 3.6 V−tolerant 3−state outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flip−flops
within the respective byte. The flip−flops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the
contents of the flip−flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flip−flops.
• Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.0 ns max for 3.0 V to 3.6 V
•
•
•
•
•
•
MARKING DIAGRAM
48
48
VCX16374
1
AWLYYWW
TSSOP−48
DT SUFFIX
CASE 1201
A
WL
YY
WW
3.9 ns max for 2.3 V to 2.7 V
7.8 ns max for 1.65 V to 1.95 V
Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
±6 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±250 mA @ 125°C
ESD Performance: Human Body Model >2000 V
Machine Model >200 V
All Devices in Package TSSOP are Inherently Pb−Free*
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN NAMES
Pins
Features
•
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Function
OEn
CPn
D0−D15
O0−O15
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
ORDERING INFORMATION
Package
Shipping †
74VCX16374DT
TSSOP
(Pb−Free)
39 / Rail
74VCX16374DTR
TSSOP
(Pb−Free)
2500 / Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
74VCX16374/D
74VCX16374
OE1 1
48 CP1
OE1
O0 2
47 D0
CP1
O1 3
46 D1
GND 4
45 GND
O2 5
44 D2
O3 6
43 D3
VCC 7
42 VCC
O4 8
41 D4
O5 9
40 D5
GND 10
39 GND
O6 11
38 D6
O7 12
37 D7
O8 13
36 D8
O9 14
35 D9
GND 15
34 GND
O10 16
33 D10
O11 17
32 D11
VCC 18
O12 19
31 VCC
30 D12
O13 20
29 D13
GND 21
28 GND
O14 22
27 D14
O15 23
26 D15
OE2 24
25 CP2
D0
D1
D2
D3
D4
D5
D6
D7
1
OE2
48
CP2
47
46
44
43
41
40
38
37
nCP
2
Q
D
nCP
3
Q
D
nCP
5
Q
D
nCP
6
Q
D
nCP
8
Q
D
nCP
9
Q
D
nCP
11
Q
D
nCP
12
Q
D
Figure 1. 48−Lead Pinout
(Top View)
O0
D8
O1
D9
O2
D10
O3
D11
O4
D12
O5
D13
O6
D14
O7
D15
24
25
36
35
33
32
30
29
27
26
Figure 2. Logic Diagram
1
OE1 48
CP1
25
CP2 24
OE2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
EN1
EN2
EN3
EN4
1
1∇
1
2∇
1
3∇
1
4∇
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Figure 3. IEC Logic Diagram
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2
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
nCP
D
nCP
D
nCP
D
nCP
D
nCP
D
nCP
D
nCP
D
nCP
D
Q
Q
Q
Q
Q
Q
Q
Q
13
14
16
17
19
20
22
23
O8
O9
O10
O11
O12
O13
O14
O15
74VCX16374
TRUTH TABLE
Inputs
Outputs
Inputs
Outputs
CP1
OE1
D0:7
O0:7
CP2
OE2
D8:15
O8:15
↑
L
H
H
↑
L
H
H
↑
L
L
L
↑
L
L
L
X
L
X
O0
X
L
X
O0
X
H
X
Z
X
H
X
Z
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
↑ = Low−to−High Transition
X = High or Low Voltage Level and Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs
O0 = No Change
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VI
Value
Condition
Unit
−0.5 to +4.6
V
DC Input Voltage
−0.5 ≤ VI ≤ +4.6
V
VO
DC Output Voltage
−0.5 ≤ VO ≤ +4.6
Output in 3−State
−0.5 ≤ VO ≤ VCC + 0.5
Note 1; Outputs Active
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
V
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Operating
Data Retention Only
Min
Typ
Max
Unit
1.65
1.2
3.3
3.3
3.6
3.6
V
−0.3
3.6
V
0
0
VCC
3.6
V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH
HIGH Level Output Current, VCC = 3.0 V − 3.6 V
−24
mA
IOL
LOW Level Output Current, VCC = 3.0 V − 3.6 V
24
mA
IOH
HIGH Level Output Current, VCC = 2.3 V − 2.7 V
−18
mA
IOL
LOW Level Output Current, VCC = 2.3 V − 2.7 V
18
mA
IOH
HIGH Level Output Current, VCC = 1.65 V − 1.95 V
−6
mA
IOL
LOW Level Output Current, VCC = 1.65 V − 1.95 V
6
mA
TA
Operating Free−Air Temperature
Dt/DV
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
(Active State)
(3−State)
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3
−40
+85
°C
0
10
ns/V
74VCX16374
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol
VIH
VIL
VOH
VOL
Condition
Min
1.65 V ≤ VCC < 2.3 V
0.65 x VCC
2.3 V ≤ VCC ≤ 2.7 V
1.6
2.7 V < VCC ≤ 3.6 V
2.0
Characteristic
HIGH Level Input Voltage (Note 2)
LOW Level Input Voltage (Note 2)
HIGH Level Output Voltage
LOW Level Output Voltage
Max
V
1.65 V ≤ VCC < 2.3 V
0.35 x VCC
2.3 V ≤ VCC ≤ 2.7 V
0.7
2.7 V < VCC ≤ 3.6 V
0.8
1.65 V ≤ VCC ≤ 3.6 V; IOH = −100 mA
VCC − 0.2
VCC = 1.65 V; IOH = −6 mA
1.25
VCC = 2.3 V; IOH = −6 mA
2.0
VCC = 2.3 V; IOH = −12 mA
1.8
VCC = 2.3 V; IOH = −18 mA
1.7
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
Unit
V
V
1.65 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
0.2
VCC = 1.65 V; IOL = 6 mA
0.3
VCC = 2.3 V; IOL = 12 mA
0.4
VCC = 2.3 V; IOL = 18 mA
0.6
VCC = 2.7 V; IOL = 12 mA
0.4
VCC = 3.0 V; IOL = 18 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
V
II
Input Leakage Current
1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 3.6 V
±5.0
mA
IOZ
3−State Output Current
1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 3.6 V;
VI = VIH or VIL
±10
mA
IOFF
Power−Off Leakage Current
VCC = 0 V; VI or VO = 3.6 V
10
mA
ICC
Quiescent Supply Current (Note 3)
1.65 V ≤ VCC ≤ 3.6 V; VI = GND or VCC
20
mA
1.65 V ≤ VCC ≤ 3.6 V; 3.6 V ≤ VI, VO ≤ 3.6 V
±20
mA
DICC
Increase in ICC per Input
2.7 V < VCC ≤ 3.6 V; VIH = VCC − 0.6 V
750
mA
2. These values of VI are used to test DC electrical characteristics only.
3. Outputs disabled or 3−state only.
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4
74VCX16374
AC CHARACTERISTICS (Note 4; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V
Symbol
Parameter
Waveform
Min
Max
VCC = 2.3 V to 2.7 V
Min
Max
200
VCC = 1.65 V to 1.95 V
Min
Max
100
Unit
fmax
Clock Pulse Frequency
1
250
tPLH
tPHL
Propagation Delay
CP−to−On
1
0.8
0.8
3.0
3.0
1.0
1.0
3.9
3.9
1.5
1.5
7.8
7.8
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
0.8
0.8
3.5
3.5
1.0
1.0
4.6
4.6
1.5
1.5
9.2
9.2
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
0.8
0.8
3.5
3.5
1.0
1.0
3.8
3.8
1.5
1.5
6.8
6.8
ns
ts
Setup Time, High or Low
Dn−to−CP
3
1.5
1.5
2.5
ns
th
Hold Time, High or Low
Dn−to−CP
3
1.0
1.0
1.0
ns
tw
CP Pulse Width, High
3
1.5
1.5
4.0
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 5)
0.5
0.5
0.5
0.5
MHz
0.75
0.75
ns
4. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 W)
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V
Waveform
Min
fmax
Clock Pulse Frequency
4
150
tPLH
tPHL
Propagation Delay
CP−to−On
4
1.0
1.0
4.2
4.2
4.9
4.9
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
5
1.0
1.0
4.8
4.8
5.9
5.9
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
5
1.0
1.0
4.3
4.3
4.7
4.7
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 6)
0.5
0.5
0.5
0.5
ns
Symbol
Parameter
Max
VCC = 2.7 V
Min
Max
150
Unit
MHz
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
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5
74VCX16374
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
VOLP
VOLV
VOHV
Condition
Typ
Unit
VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V
0.25
V
VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V
0.6
VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V
0.8
VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V
−0.25
VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V
−0.6
VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V
−0.8
VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V
1.5
VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V
1.9
VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V
2.2
Characteristic
Dynamic LOW Peak Voltage
(Note 7)
Dynamic LOW Valley Voltage
(Note 7)
Dynamic HIGH Valley Voltage
(Note 8)
V
V
7. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
8. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the HIGH state.
CAPACITIVE CHARACTERISTICS
Symbol
Condition
Typical
Unit
CIN
Input Capacitance
Parameter
Note 9
6
pF
COUT
Output Capacitance
Note 9
7
pF
CPD
Power Dissipation Capacitance
Note 9, 10 MHz
20
pF
9. VCC = 1.8 V, 2.5 V or 3.3 V; VI = 0 V or VCC.
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6
74VCX16374
VIH
Dn
Vm
Vm
VIH
CPn
th
VIH
Vm
Vm
tPHZ
tPZH
Vm
On
tPZL
VOH
Vm
VOH
Vy
≈0V
0V
fmax
tPLH, tPHL
On
Vm
0V
0V
ts
Vm
OEn
tPLZ
≈ VCC
Vm
On
Vx
VOL
VOL
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
VIH
CPn
Vm
Vm
tw
0V
VIH
tw
CPn
Vm
Vm
WAVEFORM 3 − PULSE WIDTH
tR = tF = 2.0 ns (or fast as required) from 10% to 90%
0V
Figure 5. AC Waveforms
Table 1. AC WAVEFORMS
VCC
Symbol
3.3 V ± 0.3 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
VIH
2.7 V
VCC
VCC
Vm
1.5 V
VCC/2
VCC/2
Vx
VOL + 0.3 V
VOL + 0.15 V
VOL + 0.15 V
Vy
VOH − 0.3 V
VOH − 0.15 V
VOH − 0.15 V
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7
74VCX16374
VCC
PULSE
GENERATOR
RL
DUT
RT
CL
RL
Figure 6. Test Circuit
Table 2. TEST CIRCUIT
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6 V at VCC = 3.3 ± 0.3 V;
VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V
tPZH, tPHZ
GND
CL = 30 pF or equivalent (Includes jig and probe capacitance)
RL = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50 W)
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8
6 V or VCC × 2
OPEN
GND
74VCX16374
VIH
VIH
Dn
Vm
CPn
th
Vm
On
Vm
VOH
Vy
≈0V
0V
fmax
tPLH, tPHL
On
tPHZ
tPZH
VIH
Vm
Vm
0V
0V
ts
Vm
OEn
Vm
tPZL
VOH
tPLZ
Vm
On
Vm
≈ VCC
Vx
VOL
VOL
WAVEFORM 4 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
WAVEFORM 5 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 7. AC Waveforms
VIH
CPn
Vm
Vm
tw
0V
VIH
tw
Vm
Vm
CPn
0V
WAVEFORM 6 − PULSE WIDTH
tR = tF = 2.0 ns (or fast as required) from 10% to 90%
Figure 8. AC Waveforms
Table 3. AC WAVEFORMS
VCC
Symbol
3.3 V ± 0.3 V
2.7 V
VIH
2.7 V
2.7 V
Vm
1.5 V
1.5 V
Vx
VOL + 0.3 V
VOL + 0.3 V
Vy
VOH − 0.3 V
VOH − 0.3 V
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9
74VCX16374
VCC
PULSE
GENERATOR
RL
DUT
RT
CL
RL
Figure 9. Test Circuit
Table 4. TEST CIRCUIT
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6 V at VCC = 3.3 ± 0.3 V;
VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V
tPZH, tPHZ
GND
CL = 50 pF or equivalent (Includes jig and probe capacitance)
RL = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50W)
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10
6 V or VCC × 2
OPEN
GND
74VCX16374
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 1201−01
ISSUE A
48X
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K REF
0.12 (0.005)
M
T U
S
V
S
T U
S
J J1
25
0.254 (0.010)
M
48
SECTION N−N
B
−U−
L
N
1
24
A
−V−
PIN 1
IDENT.
N
F
DETAIL E
D
0.076 (0.003)
−T− SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
C
M
0.25 (0.010)
−W−
G
H
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
12.40
12.60
6.00
6.20
−−−
1.10
0.05
0.15
0.50
0.75
0.50 BSC
0.37
−−−
0.09
0.20
0.09
0.16
0.17
0.27
0.17
0.23
7.95
8.25
0_
8_
INCHES
MIN
MAX
0.488
0.496
0.236
0.244
−−− 0.043
0.002
0.006
0.020
0.030
0.0197 BSC
0.015
−−−
0.004
0.008
0.004
0.006
0.007
0.011
0.007
0.009
0.313
0.325
0_
8_
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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