CS8161 12 V, 5.0 V Low Dropout Dual Regulator with ENABLE The CS8161 is a 12 V/5.0 V dual output linear regulator. The 12 V ±5.0% output sources 400 mA and the 5.0 V ±2.0% output sources 200 mA. The on board ENABLE function controls the regulator’s two outputs. When the ENABLE pin is low, the regulator is placed in SLEEP mode. Both outputs are disabled and the regulator draws only 200 nA of quiescent current. The primary output, VOUT1 is protected against overvoltage conditions. Both outputs are protected against short circuit and thermal runaway conditions. The CS8161 is packaged in a 5 lead TO−220 with copper tab. The copper tab can be connected to a heat sink if necessary. Features http://onsemi.com TO−220 FIVE LEAD T SUFFIX CASE 314D 1 TO−220 FIVE LEAD TVA SUFFIX CASE 314K 1 • Two Regulated Outputs − 12 V ±5.0%; 400 mA − 5.0 V ±2.0%; 200 mA • Very Low SLEEP Mode Current Drain 200 nA • Fault Protection − Reverse Battery (−15 V) − 74 V Load Dump − −100 V Reverse Transient − Short Circuit − Thermal Shutdown • Pb−Free Packages are Available* 5 1 TO−220 FIVE LEAD THA SUFFIX CASE 314A 5 PIN CONNECTIONS Tab = GND Pin 1. VIN 2. VOUT1 3. GND 4. ENABLE 5. VOUT2 1 DEVICE MARKING INFORMATION See general marking information in the device marking section on page 9 of this data sheet. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 7 1 Publication Order Number: CS8161/D CS8161 VOUT2 VIN Anti−saturation and Current Limit ENABLE + − Pre−Regulator + − VOUT1 Overvoltage Shutdown Anti−saturation and Current Limit Bandgap Reference + − GND Thermal Shutdown Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS Rating Value Unit −15 to 26 74 V V Internally Limited − Junction Temperature Range −40 to +150 °C Storage Temperature Range −65 to +150 °C 260 peak 230 peak °C °C 2.0 kV Input Voltage: Operating Range Overvoltage Protection Internal Power Dissipation Lead Temperature Soldering Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) ESD (Human Body Model) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 second maximum. 2. 60 second maximum above 183°C http://onsemi.com 2 CS8161 ELECTRICAL CHARACTERISTICS for VOUT: (6.0 V ≤ VIN ≤ 26 V; IOUT1 = 5.0 mA; IOUT2 = 5.0 mA; −40°C ≤ TJ ≤ +150°C; −40°C ≤ TA ≤ +125°C; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit 11.4 12.0 12.6 V PRIMARY OUTPUT STAGE (VOUT1) Output Voltage, VOUT1 13 V ≤ VIN ≤ 26 V, IOUT1 ≤ 400 mA Dropout Voltage IOUT1 = 400 mA − 0.35 0.6 V Line Regulation 13 V ≤ VIN ≤ 20 V, 5.0 mA ≤ IOUT < 400 mA − − 80 mV Load Regulation 5.0 mA ≤ IOUT1 ≤ 400 mA, VIN = 14 V − − 80 mV Quiescent Current IOUT1 ≤ 100 mA, No Load on VOUT2 IOUT1 ≤ 400 mA, No Load on VOUT2 − − 8.0 50 12 75 mA mA Ripple Rejection f = 120 Hz, IOUT = 300 mA, VIN = 15.0 VDC, 2.0 VRMS 42 − − dB 0.40 − 1.0 A Current Limit − Reverse Polarity Input Voltage, DC VOUT1 ≥ −0.6 V, 10 W Load − −30 −18 V Reverse Polarity Input Voltage, Transient 1.0% Duty Cycle, t = 100 ms, VOUT ≥ −6.0 V, 10 W Load − −80 −50 V Overvoltage Shutdown − 28 34 45 V Short Circuit Current − − − 700 mA 4.90 − 5.10 V SECONDARY OUTPUT (VOUT2) Output Voltage, (VOUT2) 6.0 V ≤ VIN ≤ 26 V, IOUT2 ≤ 200 mA Dropout Voltage IOUT2 ≤ 200 mA − 0.35 0.60 V Line Regulation 6.0 V ≤ VIN ≤ 26 V, 1.0 mA ≤ IOUT ≤ 200 mA − − 50 mV Load Regulation 1.0 mA ≤ IOUT2 ≤ 200 mA; VIN =14 V − − 50 mV Quiescent Current IOUT2 = 50 mA IOUT2 = 200 mA − − 5.0 20 10 35 mA mA Ripple Rejection f = 120 Hz; IOUT = 10 mA, VIN = 15 V, 2.0 VRMS 42 − − dB Current Limit − 200 − 600 mA Short Circuit Current − − − 400 mA ENABLE FUNCTION (ENABLE) Input ENABLE Threshold VOUT1 Off VOUT1 On − 2.00 1.30 1.30 0.80 − V V Input ENABLE Current VENABLE = 5.5 V VENABLE < 0.8 V 80 −10 − − 500 10 mA mA VENABLE < 0.4 V − 0.2 50 mA 150 − 210 °C − − 60 mA OTHER FEATURES Sleep Mode Thermal Shutdown Quiescent Current in Dropout − IOUT1 = 100 mA, IOUT2 = 50 mA PACKAGE PIN DESCRIPTION PACKAGE LEAD # 5 Lead TO−220 LEAD SYMBOL 1 VIN 2 VOUT1 3 GND 4 ENABLE 5 VOUT2 FUNCTION Supply voltage, usually direct from battery. Regulated output 12 V, 400 mA (typ). Ground connection. CMOS compatible input lead; switches outputs on and off. When ENABLE is high VOUT1 and VOUT2 are active. Regulated output 5.0 V, 200 mA (typ). http://onsemi.com 3 CS8161 TYPICAL PERFORMANCE CHARACTERISTICS 12.150 12.110 10 VIN = 14 V IOUT1 = 5.0 A 0 Line Regulation (mV) 12.070 Volt 1 12.030 11.990 11.950 11.910 11.870 125°C −20 −25 −35 −40°C −40 0 20 40 60 80 100 120 140 160 0 50 100 150 200 250 300 350 400 450 500 Temperature (°C) Output Current (mA) Figure 2. Output Voltage vs. Temperature for VOUT1 Figure 3. Line Regulation vs. Output Current for VOUT1 100 −40°C VIN = 14 V 10 25°C −15 11.790 −40 −20 VIN = 14 V No Load on VOUT2 90 0 Quiescent Current (mA) 5 Load Regulation (mV) −10 −30 11.750 25°C 5 10 15 20 25 125°C 30 80 125°C 70 −40°C 60 50 40 25°C 30 20 10 35 40 0 600 550 50 100 150 200 250 0 300 350 400 450 500 50 100 150 200 250 300 350 400 450 500 Output Current (mA) Figure 4. Load Regulation vs. Output Current for VOUT1 Figure 5. Quiescent Current vs. Output Current for VOUT1 VIN = 11 V 500 450 400 350 25°C 125°C 300 250 200 150 100 −40°C 50 0 0 0 Output Current (mA) Quiescent Current (mA) Dropout Voltage (mV) −5 11.830 15 VIN = 13−26V 5 50 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 100 150 200 250 300 350 400 450 500 VIN = 11 V No Load on VOUT2 −40°C 25°C 125°C 0 50 100 150 200 250 300 350 400 450 500 Output Current (mA) Output Current (mA) Figure 6. Dropout Voltage vs. Output Voltage for VOUT1 Figure 7. Quiescent Current vs. Output Current @ Dropout for VOUT1 http://onsemi.com 4 CS8161 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 5.025 5.020 3 VIN = 11 V IOUT = 5.0 mA 1 Load Regulation (mV) Output Voltage 5.015 5.010 5.005 5.000 4.995 4.990 −1 −40°C 125°C −2 −3 −4 −5 −6 4.980 −7 25°C −8 −40 −20 0 20 40 60 80 100 120 140 160 0 25 50 75 100 125 150 175 200 225 250 Temperature (°C) Output Current (mA) Figure 8. Output Voltage vs. Temperature for VOUT2 Figure 9. Line Regulation vs. Output Current for VOUT2 50 VIN = 14 V −40°C VIN = 14 V No Load on VOUT1 45 Quiescent Current (mA) 8 6 4 2 0 −2 −4 −6 −8 −10 −12 −14 −16 −18 25°C 125°C 40 −40°C 35 30 125°C 25 20 25°C 15 10 5 0 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 25 50 75 0 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 Output Current (mA) Output Current (mA) Figure 10. Load Regulation vs. Output Current for VOUT2 Figure 11. Quiescent Current vs. Output Current for VOUT2 VIN = 4.0 V No Load on VOUT1 125°C Quiescent Current (mA) Load Regulation (mV) 0 4.985 4.975 Dropout Voltage (mV) VIN = 6.0−26V 2 −40°C 25°C 60 55 50 45 VIN = 4.0 V −40°C 40 35 125°C 25°C 30 25 20 15 10 5 0 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 Output Current (mA) Output Current (mA) Figure 12. Dropout Voltage vs. Output Current for VOUT2 Figure 13. Quiescent Current vs. Output Current @ Dropout for VOUT2 http://onsemi.com 5 CS8161 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 1.305 (1.8500 V, 253.9 nA.) VIN = 14 V 100 80 IENABLE ENABLE Voltage 1.300 1.295 60 40 1.290 20 1.285 0 −40 −20 0 20 40 60 80 100 120 140 0 1 2 3 4 Temperature (°C) VENABLE (V) Figure 14. Enable Threshold Voltage vs. Temperature Figure 15. ENABLE Current vs. ENABLE Voltage 5 5 IENABLE 4 3 2 1 0 0 5 10 15 20 25 VENABLE Figure 16. 12 mA ENABLE Current vs. ENABLE Voltage DEFINITION OF TERMS Dropout Voltage − The input−output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage − The DC voltage applied to the input terminals with respect to ground. Input Output Differential − The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Line Regulation − The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation − The change in output voltage for a change in load current at constant chip temperature. Long Term Stability − Output voltage stability under accelerated life−test conditions after 1000 hours with maximum rated voltage and junction temperature. Output Noise Voltage − The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current − The part of the positive input current that does not contribute to the positive load current, i.e., the regulator ground lead current. Ripple Rejection − The ratio of the peak−to−peak input ripple voltage to the peak−to−peak output ripple voltage. Temperature Stability of VOUT − The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. http://onsemi.com 6 CS8161 60 V VIN 14 V ENABLE 2.0 V 0.8 V 34 V 26 V 14V 3.0 V 12 V 12 V 12 V 12 V 12 V 2.4 V VOUT1 0V 0V 0V 5.0 V 5.0 V VOUT2 0V 5.0 V 2.4 V 0V 0V 0V Turn On Load Dump Low VIN Line Noise, Etc. VOUT1 Short Circuit VOUT2 Short Circuit VOUT1 Thermal Shutdown Turn Off Figure 17. Typical Circuit Waveform APPLICATION DIAGRAM C1* 0.1 mF Display VIN CS8161 VOUT1 + C2* 22 mF + C3* 22 mF ENABLE GND VOUT2 Tuner * C1 required if regulator is located far from power supply filter. ** C2, C3 required for stability, value may be increased. Capacitor must operate at minimum temperature expected. Figure 18. Application Diagram APPLICATION NOTES Since both outputs are controlled by the same ENABLE, the CS8161 is ideal for applications where a sleep mode is required. Using the CS8161, a section of circuitry such as a display and nonessential 5.0 V circuits can be shut down under microprocessor control to conserve energy. The example in the Applications Diagram (Figure 18) shows an automotive radio application where the display is powered by the 12 V on VOUT1 and the Tuner IC is powered by the 5.0 V on VOUT2. Neither output is required unless both the ignition and the Radio On/Off switch are on. characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the cheapest solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. Stability Considerations The output or compensation capacitor (Application diagram C2 and C3) helps determine three main http://onsemi.com 7 CS8161 temperatures. The ESR of the capacitors should be less than 50% of the maximum allowable ESR found in step 3 above. Once the value for C2 is determined, repeat the steps to determine the appropriate value for C3. The values for the output capacitors C2 and C3 shown in the test and applications circuit should work for most applications, however it is not necessarily the best solution. To determine acceptable values for C2 and C3 for a particular application, start with tantalum capacitors of the recommended value on each output and work towards less expensive alternative parts for each output in turn. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs on the oscilloscope. A decade box connected in series with the capacitor C2 will simulate the higher ESR of an aluminum capacitor.(Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible) Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor C2 is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. (A smaller capacitor will usually cost less and occupy less board space.) If the capacitor oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real work environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low Calculating Power Dissipation in a Dual Output Linear Regulator The maximum power dissipation for a dual output regulator (Figure 19) is PD(max) + NJVIN(max) * VOUT1(min)NjIOUT1(max) ) NJVIN(max) * VOUT2(min)NjIOUT2(max) ) VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: RqJA + 150°C * TA PD (2) The value of RqJA can be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN Smart Regulator Control Features IOUT1 VOUT1 IOUT2 VOUT2 IQ Figure 19. Dual Output Regulator With Key Performance Parameters Labeled. http://onsemi.com 8 CS8161 Heat Sinks where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heatsink thermal resistance, and RqSA = the heatsink−to−ambient thermal resistance. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: RqJA + RqJC ) RqCS ) RqSA RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. (3) MARKING DIAGRAMS TO−220 5−LEAD CS 8161 AWLYWWG A WL YY WW G CS 8161 AWLYWWG CS8161 AWLYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 1 1 1 ORDERING INFORMATION* Device Package CS8161YT5 TO−220 STRAIGHT CS8161YT5G TO−220 STRAIGHT (Pb−Free) CS8161YTVA5 TO−220 VERTICAL CS8161YTVA5G TO−220 VERTICAL (Pb−Free) CS8161YTHA5 TO−220 HORIZONTAL CS8161YTHA5G TO−220 HORIZONTAL (Pb−Free) *Consult your local sales representative for SO−16L package option. http://onsemi.com 9 Shipping 50 Units / Rail CS8161 PACKAGE DIMENSIONS TO−220 CASE 314D−04 ISSUE F −T− B −Q− C DETAIL A−A B1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. SEATING PLANE E A U DIM A B B1 C D E G H J K L Q U L 1234 5 K J H G D 5 PL 0.356 (0.014) M T Q M B INCHES MIN MAX 0.572 0.613 0.390 0.415 0.375 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.977 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 9.525 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 24.810 26.543 8.128 9.271 3.556 3.886 2.667 2.972 B1 DETAIL A−A TO−220 TVA SUFFIX CASE 314K−01 ISSUE O −T− SEATING PLANE C B −Q− E W A U F L 1 2 3 4 K 5 M D 0.356 (0.014) M J 5 PL T Q M G S R http://onsemi.com 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G J K L M Q R S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5° MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5° CS8161 PACKAGE DIMENSIONS TO−220 THA SUFFIX CASE 314A−03 ISSUE E −T− B −P− Q C E OPTIONAL CHAMFER A U F L G 5X K 5X J S D 0.014 (0.356) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. SEATING PLANE M T P M DIM A B C D E F G J K L Q S U INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827 PACKAGE THERMAL DATA Parameter TO−220 FIVE LEAD Unit RqJC Typical 2.0 °C/W RqJA Typical 50 °C/W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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