Intersil EL1882C Sync separator w/50% slice, agc Datasheet

EL1882C
®
Data Sheet
January 1996, Rev A
FN7019
Sync Separator w/50% Slice, AGC
Features
The EL1882C video sync separator is
manufactured using Elantec's high
performance analog CMOS process.
This device extracts sync timing information from both
standard and non-standard video input. It provides
composite sync, vertical sync, burst/back porch timing and
odd/even field detection. 50% sync tip slicing provides
precise sync edge detection when the video input level is
between 0.5VP-P and 2VP-P (sync tip amplitude 143mV to
572mV). A single external resistor sets all internal timing to
adjust for various video standards. The composite sync
output follows video in sync pulses, and a vertical sync
pulse is output on the rising edge of the first vertical serration
following the vertical pre-equalizing string. For non-standard
vertical inputs, a default vertical pulse is output when the
vertical signal stays low for longer than the vertical sync
default delay time. The odd/even output indicates field
polarity detected during the vertical blanking interval. The
EL1882C is plug-in compatible with the industry standard
LM1881 and can be substituted for that part in 5V
applications with improved 50% slicing and lower required
supply current.
• NTSC, PAL, SECAM, non-standard video sync separation
• Precision 50% slicing of video input levels from 0.5VP-P to
2VP-P
• Low supply current - 1.5mA typ.
• Single +5V supply
• Composite, vertical sync output
• Odd/Even field output
• Burst/Back porch output
• Plug-in compatible with industry standard LM1881 in 5V
applications
• Available in 8-pin DIP and SO package
Applications
• Video special effects
• Video test equipment
• Video distribution
• Displays
• Imaging
Ordering Information
• Video data capture
PART NO.
TEMP. RANGE
PACKAGE
PKG. NO.
EL1882CN
-40°C to +85°C
8-pin DIP
MDP0031
EL1882CS
-40°C to +85°C
8-lead SO
MDP0027
• Video triggers
Demo Board
A dedicated demo board is not available. However, this
device can be placed on the EL4584/5 demo board.
Pinout
EL1882C
(8-PIN PDIP, SO)
TOP VIEW
COMPOSITE SYNC OUT 1
COMPOSITE VIDEO IN
2
VERTICAL SYNC OUT 3
GND
1
4
8 VDD 5V
7 ODD/EVEN OUTPUT
6 RSET
5 BURST/BACK
PORCH OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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EL1882C
Absolute Maximum Ratings (TA = 25°C)
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
MPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
VDD = 5V, TA = 25°C, RSET = 680kΩ, unless otherwise specified.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
IDD, Quiescent
VDD = 5V
0.75
1.5
3.0
mA
Clamp Voltage
Pin 2, Unloaded
1.35
1.5
1.65
V
Clamp Discharge Current
Pin 2 = 2V
3.2
12
16
µA
Clamp Charge Current
Pin 2 = 1V
-2.0
-1.5
-0.8
mA
RSET Pin Reference Voltage
Pin 6
1.20
1.31
1.40
V
VOL Output Low Voltage
IOL = 1.6mA
0.4
0.8
V
VOH Output High Voltage
IOH = -40µA
4
4.8
IOH = -1.6mA
2.4
3.5
MIN
TYP
MAX
UNIT
V
Dynamic Specifications
PARAMETER
DESCRIPTION
Comp Sync Prop Delay, tCS
See Figure 2
10
25
40
ns
Vertical Sync Width, tVS
Normal or Default Trigger, 50%-50%
190
270
350
µs
Vertical Sync Default Delay, tVSD
See Figure 3
35
65
85
µs
Burst/Back Porch Delay, tBD
See Figure 2
250
450
650
ns
Burst/Back Porch Width, tB
See Figure 2
2.5
3.6
4.5
µs
Input Dynamic Range
Video Input Amplitude to Maintain 50% Slice Spec
0.5
2
VP-P
Slice Level
VSLICE/VCLAMP
40
60
%
2
50
EL1882C
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
Composite Sync Out
Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge.
2
Composite Video In
AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase).
3
Vertical Sync Out
Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period.
4
GND
Supply ground.
5
Burst/Back Porch Output
Burst/back porch output; low during burst portion of composite video.
6
RSET (Note 1)
An external resistor to ground sets all internal timing; a 681k 1% resistor will provide correct timing for
NTSC signals.
7
Odd/Even Output
Odd/even field output; high during odd fields, low during even fields; transitions occur at start of vert
sync pulse.
8
VDD 5V
Positive supply (5V).
NOTE:
1. RSET must be a 1% resistor.
3
EL1882C
Typical Performance Curves
Supply Current, Quiescent
RSET = 681k
IDD vs VDD
RSET = 681k
VCLAMP Voltage
RSET = 681k
Clamp Discharge Current
RSET = 681k
VRSET
RSET = 681k
Clamp Charge Current
RSET = 681k
4
EL1882C
Typical Performance Curves
(Continued)
RSET vs Horizontal Frequency
Burst/Back Porch Width vs RSET
VDD = 5V, T = 25°C
Vertical Sync Width vs RSET
VDD = 5V, T = 25°C
5
Burst/Back Porch Delay vs RSET
VDD = 5V, T = 25°C
Vertical Default Delay vs RSET
VDD = 5V, T = 25°C
EL1882C
Typical Performance Curves
(Continued)
Composite Sync Prop Delay
RSET = 681k, VDD = 5V
Burst/Back Porch Width,
RSET = 681k
Burst/Back Porch Delay Time,
RSET = 681k
Vertical Sync Pulse Width
RSET = 681k
Vertical Sync Default Delay Time,
RSET = 681k
Composite Sync vs Delay Time
RSET = 681k
Composite Sync to
Odd/Even Delay Time
RSET = 681k
6
EL1882C
Timing Diagrams
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a
propagation delay.
d. Odd-even output is low for even field, and high for odd field.
e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note
that for serration pulses during vertical, the back porch starts on the rising edge of the serration
pulse (with propagation delay).
* Signal 1a drawing reproduced with permission from EIA.
FIGURE 1. STANDARD (NTSC INPUT) TIMING
7
EL1882C
Expanded Timing Diagrams
FIGURE 2. STANDARD VERTICAL TIMING
FIGURE 3. NON-STANDARD VERTICAL TIMING
8
EL1882C
FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL
Applications Information
Video In
A simplified block diagram is shown in Figure 6.
An AC coupled video signal is input to Video In pin 2 via C1,
nominally 0.1µF. Clamp charge current will prevent the
signal on pin 2 from going any more negative than Sync Tip
Ref, about 1.5V. This charge current is nominally about
1mA. A clamp discharge current of about 10µA is always
attempting to discharge C1 to Sync Tip Ref, thus charge is
lost between sync pulses that must be replaced during sync
pulses. The droop voltage that will occur can be calculated
from IT = CV, where V is the droop voltage, I is the discharge
current, T is the time between sync pulses (sync period sync tip width), and C is C1.
An NTSC video signal has a horizontal frequency of
15.73kHz, and a sync tip width of 4.7µs. This gives a period
of 63.6µs and a time T = 58.9µs. The droop voltage will then
be V = 5.9mV. This is less than 2% of a nominal sync tip
amplitude of 286mV. The charge represented by this droop
is replaced in a time given by T=CV/I, where I = clamp
charge current = 1mA. Here T = 590ns, about 12% of the
sync pulse width of 4.7µs. It is important to choose C1 large
enough so that the droop voltage does not approach the
50% switching threshold of the internal comparator.
9
AGC and Composite Sync
The clamped video signal then passes to the AGC, which
will maintain the blanking level of its output (sensed during
burst) at the blanking reference level. The AGC should
therefore present a constant amplitude signal to the
comparator, if the input is within the AGC's dynamic range. A
50% slicing reference is compared with the AGC's output at
the comp circuit. Comp's output is level shifted and buffered
to TTL levels, and sent out as Comp Sync on pin 1.
Burst
A low-going Burst pulse follows each rising edge of sync,
and lasts approximately 3.5µs for an RSET of 681kΩ. This
signal is used internally to gate the AGC feedback for
determining blanking level.
Vertical Sync
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the EL1882C on the first rising edge during the vertical
serration phase. In the absence of vertical serration pulses,
a vertical sync pulse will be forced out after the vertical sync
EL1882C
default delay time, approximately 60µs after the last falling
edge of the vertical equalizing phase for RSET = 681kΩ.
Odd/Even
Because a typical television picture is composed of two
interlaced fields, there is an odd field that includes all the
odd lines, and an even field that consists of the even lines.
This odd/even field information is decoded by the EL1882C
during the end of picture information and the beginning of
vertical information. The odd/even circuit includes a T-flipflop that is reset during full horizontal lines, but not during
half lines or vertical equalization pulses. The T-flip-flop is
clocked during each falling edge of these half hperiod
pulses. Even fields will toggle until a low state is clocked to
the odd/even pin 7 at the beginning of vertical sync, and odd
fields will cause a high state to be clocked to the odd/even
pin at the start of the next vertical sync pulse. Odd/even can
be ignored if using non-interlaced video, as there is no
change in timing from one field to the next.
RSET
An external RSET resistor, connected from RSET pin 6 to
ground, produces a reference current that is used internally
as the timing reference for vertical sync width, vertical sync
default delay, burst gate delay and burst width. Decreasing
the value of RSET increases the reference current, which in
turn decreases reference times and pulse widths. A higher
frequency video input necessitates a lower RSET value.
Chroma Filter
When the EL1882 is used in composite color systems, a
chroma filter is required at the video input. This is so
because the color burst signal extends to the 50% point of
the sync pulse (-20 IRE). Since the EL1882 slices at the
50% level, a chroma filter is required to attenuate the color
burst signal to a point above the 50% level. Without this filter
false sync triggering may occur during color burst. An
example chroma filter is shown in Figure 5. It can be
implemented very simply and inexpensively with a series
resistor of 620Ω and a parallel capacitor of 500pF, which
gives a single pole roll-off frequency of about 500kHz. This
sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz
(PAL) color burst signal, yet passes the approximately
15kHz sync signals without appreciable attenuation. A
chroma filter will increase the propagation delay from
composite sync to outputs.
FIGURE 5.
10
EL1882C
Simplified Block Diagram
*NOTE: RSET MUST BE A 1% RESISTOR.
FIGURE 6.
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