SYNCHRONOUS PRESETTABLE BINARY COUNTER The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74AC163/ 74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. • • • • • N SUFFIX CASE 648-08 PLASTIC Synchronous Counting and Loading High-Speed Synchronous Expansion Typical Count Rate of 125 MHz Outputs Source/Sink 24 mA ′ACT161 and ′ACT163 Have TTL Compatible Inputs VCC 16 TC Q0 14 Q1 13 Q2 12 Q3 11 CET PE 15 10 9 1 2 3 4 5 6 7 8 *R CP P0 P1 P2 P3 CEP GND D SUFFIX CASE 751B-05 PLASTIC LOGIC SYMBOL PE P0 P1 P2 P3 CEP CET TC CP *R Q0 Q1 Q2 Q3 PIN NAMES CEP CET CP MR SR P0–P3 PE Q 0 –Q 3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (′161) Asynchronous Master Reset Input (′163) Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output *MR for ′161 *SR for ′163 FACT DATA 5-1 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 FUNCTIONAL DESCRIPTION The MC74AC161/74ACT161 and MC74AC163/74ACT163 count modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the ′161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (′161), synchronous reset (′163), parallel load, count-up and hold. Five control inputs — Master Reset (MR, ′161), Synchronous Reset (SR, ′163), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (′161) or SR (′163) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The MC74AC161/74ACT161 and MC74AC163/74ACT163 use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the MC74AC568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable = CEP•CET•PE TC = Q0•Q1•Q2•Q3•CET STATE DIAGRAM MODE SELECT TABLE *SR PE CET CEP L H H H H X L H H H X X H L X X X H X L Action on the Rising Clock Edge ( ) 0 Reset (Clear) Load (Pn → Qn) Count (Increment) No Change (Hold) No Change (Hold) *For ′163 only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 LOGIC DIAGRAM P0 P1 P2 P3 PE ′161 ′163 CEP CET CP ′163 ONLY TC CP ′161 ONLY CP D CD Q0 CP Q D Q Q0 DETAIL A DETAIL A DETAIL A Q1 Q2 Q3 DETAIL A MR ′161 SR ′163 Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FACT DATA 5-2 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 MAXIMUM RATINGS* Symbol Parameter Value Unit –0.5 to +7.0 V V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH IOL Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 VCC VCC @ 3.0 V 150 VCC @ 4.5 V 40 VCC @ 5.5 V 25 VCC @ 4.5 V 10 VCC @ 5.5 V 8.0 Unit V V ns/V ns/V 140 °C 85 °C Output Current — High –24 mA Output Current — Low 24 mA –40 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. FACT DATA 5-3 25 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = –40°C to +85°C Typ VIH VIL VOH 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC – 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC – 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 5.5 ±0.1 Maximum Low Level Output Voltage Maximum Input Leakage Current IOLD †Minimum Dynamic Output Current ICC Guaranteed Limits 3.0 4.5 5.5 IIN IOHD Conditions Minimum High Level Input Voltage 3.0 4.5 5.5 VOL Unit Maximum Quiescent Supply Current 3.0 4.5 5.5 0.002 0.001 0.001 IOUT = –50 µA V *VIN = VIL or VIH –12 mA IOH –24 mA –24 mA IOUT = 50 µA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1.0 µA VI = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. FACT DATA 5-4 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74AC161 74AC161 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Unit Fig. No. MHz 3-3 Max fmax Maximum Count Frequency 3.3 5.0 70 110 111 167 60 95 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 2.0 1.5 7.0 5.0 12.0 9.0 1.5 1.0 13.5 9.5 ns 3-6 tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 1.5 1.5 7.0 5.0 12.0 9.5 1.5 1.5 13.0 10.0 ns 3-6 tPLH Propagation Delay CP to TC 3.3 5.0 3.0 2.0 9.0 6.0 15.0 10.5 2.5 1.5 16.5 11.5 ns 3-6 tPHL Propagation Delay CP to TC 3.3 5.0 3.5 2.0 8.5 6.5 14.0 11.0 2.5 2.0 15.5 11.5 ns 3-6 tPLH Propagation Delay CET to TC 3.3 5.0 2.0 1.5 5.5 3.5 9.5 6.5 1.5 1.0 11.0 7.5 ns 3-6 tPHL Propagation Delay CET to TC 3.3 5.0 2.5 2.0 6.5 5.0 11.0 8.5 2.0 1.5 12.5 9.5 ns 3-6 tPHL Propagation Delay MR to Qn 3.3 5.0 2.0 1.5 6.0 5.5 12.0 9.5 1.5 1.5 13.5 10.0 ns 3-6 tPHL Propagation Delay MR to TC 3.3 5.0 3.5 2.5 10.0 8.5 15.0 13.0 3.0 2.5 17.5 13.5 ns 3-6 Unit Fig. No. MHz 3-3 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74AC163 74AC163 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Max fmax Maximum Count Frequency 3.3 5.0 70 110 95 140 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 2.0 1.5 7.5 5.5 12.5 9.0 1.5 1.0 13.5 9.5 ns 3-6 tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 1.5 1.5 8.5 6.0 12.0 9.5 1.5 1.5 13.0 10.0 ns 3-6 tPLH Propagation Delay CP to TC 3.3 5.0 3.0 2.0 9.5 7.0 15.0 10.5 2.5 1.5 16.5 11.5 ns 3-6 tPHL Propagation Delay CP to TC 3.3 5.0 3.5 2.0 11.0 8.0 14.0 11.0 2.5 2.0 15.5 11.5 ns 3-6 tPLH Propagation Delay CET to TC 3.3 5.0 2.0 1.5 7.5 5.5 9.5 6.5 1.5 1.0 11.0 7.5 ns 3-6 tPHL Propagation Delay CET to TC 3.3 5.0 2.5 2.0 8.5 6.0 11.0 8.5 2.0 1.5 12.5 9.5 ns 3-6 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-5 60 95 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74AC161 74AC161 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 3.3 5.0 6.0 3.5 13.5 8.5 16.0 10.5 ns 3-9 th Hold Time, HIGH or LOW Pn to CP 3.3 5.0 –7.0 –4.0 –1.0 0 –0.5 0 ns 3-9 ts Setup Time, HIGH or LOW PE to CP 3.3 5.0 6.5 4.0 11.5 7.5 14.0 8.5 ns 3-9 th Hold Time, HIGH or LOW PE to CP 3.3 5.0 –6.0 –3.5 0 0.5 0 1.0 ns 3-9 ts Setup Time, HIGH or LOW CEP or CET to CP 3.3 5.0 3.0 2.0 6.0 4.5 7.0 5.0 ns 3-9 th Hold Time, HIGH or LOW CEP or CET to CP 3.3 5.0 –3.5 –2.0 0 0 0 0.5 ns 3-9 tw Clock Pulse Width (Load) HIGH or LOW 3.3 5.0 2.0 2.0 3.5 2.5 4.0 3.0 ns 3-6 tw Clock Pulse Width (Count) HIGH or LOW 3.3 5.0 2.0 2.0 4.0 3.0 4.5 3.5 ns 3-6 tw MR Pulse Width, LOW 3.3 5.0 3.0 2.5 5.5 4.5 7.5 6.0 ns 3-6 trec Recovery TIme MR to CP 3.3 5.0 –2.0 –1.0 –0.5 0 0 0.5 ns 3-9 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-6 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74AC163 74AC163 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 3.3 5.0 5.5 4.0 13.5 8.5 16.0 10.5 ns 3-9 th Hold Time, HIGH or LOW Pn to CP 3.3 5.0 –7.0 –5.0 –1.0 0 –0.5 0 ns 3-9 ts Setup Time, HIGH or LOW SR to CP 3.3 5.0 5.5 4.0 14 9.5 16.5 11.0 ns 3-9 th Hold Time, HIGH or LOW SR to CP 3.3 5.0 –7.5 –5.5 –1.0 –0.5 –0.5 0 ns 3-9 ts Setup Time, HIGH or LOW PE to CP 3.3 5.0 5.5 4.0 11.5 7.5 14.0 8.5 ns 3-9 th Hold Time, HIGH or LOW PE to CP 3.3 5.0 –7.5 –5.0 –1.0 –0.5 –0.5 0 ns 3-9 ts Setup Time, HIGH or LOW CEP or CET to CP 3.3 5.0 3.5 2.5 6.0 4.5 7.0 5.0 ns 3-9 th Hold Time, HIGH or LOW CEP or CET to CP 3.3 5.0 –4.5 –3.0 0 0 0 0.5 ns 3-9 tw Clock Pulse Width (Load) HIGH or LOW 3.3 5.0 3.0 2.0 3.5 2.5 4.0 3.0 ns 3-6 tw Clock Pulse Width (Count) HIGH or LOW 3.3 5.0 3.0 2.0 4.0 3.0 4.5 3.5 ns 3-6 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-7 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = –40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC – 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC – 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 3.86 4.86 3.76 4.76 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC – 2.1 V 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 V V IOUT = –50 µA *VIN = VIL or VIH –24 mA IOH –24 mA IOUT = 50 µA IIN Maximum Input Leakage Current 5.5 ∆ICCT Additional Max. ICC/Input 5.5 IOLD †Minimum Dynamic Output Current 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current 0.6 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. FACT DATA 5-8 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74ACT161 74ACT161 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Unit Fig. No. MHz 3-3 Max fmax Maximum Count Frequency 5.0 115 125 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 8.0 9.5 1.5 10.5 ns 3-6 tPHL Propagation Delay CP or Qn (PE Input HIGH or LOW) 5.0 1.5 8.0 10.5 1.5 11.5 ns 3-6 tPLH Propagation Delay CP to TC 5.0 2.0 11.0 11.0 1.5 12.5 ns 3-6 tPHL Propagation Delay CP to TC 5.0 1.5 11.0 12.5 1.5 13.5 ns 3-6 tPLH Propagation Delay CET to TC 5.0 1.5 7.5 8.5 1.5 10.0 ns 3-6 tPHL Propagation Delay CET to TC 5.0 1.5 8.0 9.5 1.5 10.5 ns 3-6 tPHL Propagation Delay MR to Qn 5.0 1.5 8.0 10.0 1.5 11.0 ns 3-6 tPHL Propagation Delay MR to TC 5.0 2.5 10.0 13.5 2.0 14.5 ns 3-6 Unit Fig. No. MHz 3-3 100 * Voltage Range 5.0 V is 5.0 V ±0.5 V. AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74ACT163 74ACT163 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Max fmax Maximum Count Frequency 5.0 120 140 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.5 10.0 1.5 11.0 ns 3-6 tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 6.0 11.0 1.5 12.0 ns 3-6 tPLH Propagation Delay CP to TC 5.0 2.5 7.0 11.5 2.0 13.5 ns 3-6 tPHL Propagation Delay CP to TC 5.0 3.0 8.0 13.5 2.0 15.0 ns 3-6 tPLH Propagation Delay CET to TC 5.0 2.0 5.5 9.0 1.5 10.5 ns 3-6 tPHL Propagation Delay CET to TC 5.0 2.0 6.0 10.0 2.0 11.0 ns 3-6 * Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-9 105 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74ACT161 74ACT161 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 5.0 7.0 9.5 11.5 ns 3-9 th Hold Time, HIGH or LOW Pn to CP 5.0 –3.0 0 0 ns 3-9 ts Setup Time, HIGH or LOW PE to CP 5.0 6.0 8.5 9.5 ns 3-9 th Hold Time, HIGH or LOW PE to CP 5.0 –3.5 – 0.5 – 0.5 ns 3-9 ts Setup Time, HIGH or LOW CEP or CET to CP 5.0 4.0 5.5 6.5 ns 3-9 th Hold Time, HIGH or LOW CEP or CET to CP 5.0 –2.0 0 0 ns 3-9 tw Clock Pulse Width (Load) HIGH or LOW 5.0 2.0 3.0 3.5 ns 3-6 tw Clock Pulse Width (Count) HIGH or LOW 5.0 2.0 3.0 3.5 ns 3-6 tw MR Pulse Width, LOW 5.0 3.0 3.0 7.5 ns 3-6 trec Recovery Time MR to CP 5.0 0 0 0.5 ns 3-9 * Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-10 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT163 74ACT163 TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 5.0 4.0 10.0 12.0 ns 3-9 th Hold Time, HIGH or LOW Pn to CP 5.0 –5.0 0.5 0.5 ns 3-9 ts Setup Time, HIGH or LOW SR to CP 5.0 4.0 10.0 11.5 ns 3-9 th Hold Time, HIGH or LOW SR to CP 5.0 –5.5 –0.5 –0.5 ns 3-9 ts Setup Time, HIGH or LOW PE to CP 5.0 4.0 8.5 10.5 ns 3-9 th Hold Time, HIGH or LOW PE to CP 5.0 –5.5 –0.5 0 ns 3-9 ts Setup Time, HIGH or LOW CEP or CET to CP 5.0 2.5 5.5 6.5 ns 3-9 th Hold Time, HIGH or LOW CEP or CET to CP 5.0 –3.0 0 0.5 ns 3-9 tw Clock Pulse Width HIGH or LOW 5.0 2.0 3.5 3.5 ns 3-6 tw Clock Pulse Width (Count) HIGH or LOW 5.0 2.0 3.5 3.5 ns 3-6 * Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 45 pF VCC = 5.0 V FACT DATA 5-11 MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 OUTLINE DIMENSIONS N SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ FACT DATA 5-12 *MC74AC161/D* MC74AC161/D