TI BQ2204ASNG4 X4 sram nonvolatile controller unit Datasheet

bq2204A
X4 SRAM Nonvolatile Controller Unit
General Description
Features
ä Power monitoring and switching
for 3-volt battery-backup applications
ä Write-protect control
ä 2-input decoder for control of up
to 4 banks of SRAM
ä 3-volt primary cell inputs
ä Les s t han 10ns chip- e nable
propagation delay
ä 5% or 10% supply operation
The CMOS bq2204A SRAM Nonvolatile Controller Unit provides all
necessary functions for converting
up to four banks of standard CMOS
SRAM into nonvolatile read/write
memory.
A precision comparator monitors the 5V
VCC input for an out-of-tolerance condition. When out-of-tolerance is detected,
the four conditioned chip-enable outputs
are forced inactive to write-protect up to
four banks of SRAM.
Pin Connections
During a power failure, the external
SRAMs are switched from the VCC
supply to one of two 3V backup supplies. On a subsequent power-up, the
SRAMs are write-protected until a
power-valid condition exists.
During power-valid operation, a
two-input decoder transparently selects one of up to four banks of
SRAM.
Pin Names
VOUT
Supply output
BC1–BC2
3 volt primary backup cell inputs
THS
Threshold select input
VOUT
1
16
VCC
BC2
2
15
BC1
NC
3
14
CE
CE
chip-enable active low input
A
4
13
CECON1
5
12
CECON2
CECON1–
CECON4
Conditioned chip-enable outputs
B
NC
6
11
CECON3
A–B
Decoder inputs
THS
7
10
CECON4
NC
No connect
VSS
8
9
VCC
+5 volt supply input
VSS
Ground
NC
16-Pin Narrow DIP or SOIC
PN220401.eps
Functional Description
If THS is tied to VCC, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to VSS or VCC for proper operation.
Up to four banks of CMOS static RAM can be batterybacked using the VOUT and conditioned chip-enable output pins from the bq2204A. As VCC slews down during
a power failure, the conditioned chip-enable outputs
CECON1 through CECON4 are forced inactive independent of the chip-enable input CE.
If a memory access is in process to any of the four external
banks of SRAM during power-fail detection, that memory
cycle continues to completion before the memory is writeprotected. If the memory cycle is not terminated within
time tWPT, all four chip-enable outputs are unconditionally
driven high, write-protecting the controlled SRAMs.
This activity unconditionally write-protects the external
SRAM as VCC falls below an out-of-tolerance threshold
VPFD. VPFD is selected by the threshold select input pin,
THS. If THS is tied to VSS, the power-fail detection occurs
at 4.62V typical for 5% supply operation.
Dec. 1992 B
1
bq2204A
During power-valid operation, the CE input is passed
through to one of the four CECON outputs with a propagation delay of less than 10ns. The CE input is output
on one of the four CECON output pins depending on the
level of the decode inputs at A and B as shown in the
Truth Table.
As the supply continues to fall past VPFD, an internal
switching device forces VOUT to one of the two external
backup energy sources. CECON1 through CECON4 are
held high by the VOUT energy source.
During power-up, VOUT is switched back to the 5V supply as VCC rises above the backup cell input voltage
sourcing VOUT. Outputs CECON1 through CECON4 are
held inactive for time tCER (120ms maximum) after the
power supply has reached VPFD, independent of the CE
input, to allow for processor stabilization.
The A and B inputs are usually tied to high-order address pins so that a large nonvolatile memory can be designed using lower-density memory devices. Nonvolatility
and decoding are achieved by hardware hookup as shown
in Figure 1.
5V
VCC
VOUT
bq2204A
A
B
From Address
Decoder
3V
Primary
Cell
CECON1
CE
CECON2
BC2
CECON3
THS
CECON4
VSS
BC1
VCC
VCC
VCC
VCC
CMOS
SRAM
CMOS
SRAM
CMOS
SRAM
CMOS
SRAM
CE
CE
CE
CE
3V
Primary
Cell
FG220401.eps
Figure 1. Hardware Hookup (5% Supply Operation)
Dec. 1992 B
2
bq2204A
Energy Cell Inputs—BC1, BC2
Two backup energy source inputs are provided on the
bq2204A. The BC1 and BC2 inputs accept a 3V primary
battery (non-rechargeable), typically some type of lithium chemistry. If no primary cell is to be used on either
BC1 or BC2, the unused input should be tied to VSS.
VPFD
VCC falling below VPFD starts the comparison of BC1
and BC2. The BC input comparison continues until VCC
rises above VSO. Power to VOUT begins with BC1 and
switches to BC2 only when VBC1 is less than VBC2 minus VBSO. The controller alternates to the higher BC
voltage only when the difference between the BC input
voltages is greater than VBSO. Alternating the backup
batteries allows one-at-a-time battery replacement and
efficient use of both backup batteries.
VCC
VSO
0.5 VCC
CE
700ns
To prevent battery drain when there is no valid data to
retain, VOUT and CECON1-4 are internally isolated from
BC1 and BC2 by either of the following conditions:
■
Initial connection of a battery to BC1 or BC2, or
■
Presentation of an isolation signal on CE.
TD220201.eps
A valid isolation signal requires CE low as VCC crosses
both VPFD and VSO during a power-down. See Figure 2.
Between these two points in time, CE must be brought
to the point of (0.48 to 0.52)*VCC and held for at least
700ns. The isolation signal is invalid if CE exceeds
0.54*VCC at any point between VCC crossing VPFD and
VSO.
Figure 2. Battery Isolation Signal
The appropriate battery is connected to V OUT and
CECON1–4 immediately on subsequent application and
removal of VCC.
Truth Table
Input
Output
CE
A
B
CECON1
CECON2
CECON3
CECON4
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
H
L
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
H
H
L
Dec. 1992 B
3
bq2204A
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to +7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to +7.0
V
VT ≤ VCC + 0.3
0 to 70
°C
Commercial
TOPR
Operating temperature
-40 to +85
°C
Industrial “N”
TSTG
Storage temperature
-55 to +125
°C
TBIAS
Temperature under bias
-40 to +85
°C
TSOLDER
Soldering temperature
260
°C
IOUT
VOUT current
200
mA
Note:
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
4.75
5.0
5.5
V
THS = VSS
4.50
5.0
5.5
V
THS = VCC
0
0
0
V
VCC
Supply voltage
VSS
Supply voltage
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
VBC1,
VBC2
Backup cell voltage
2.0
-
4.0
V
THS
Threshold select
-0.3
-
VCC + 0.3
V
Note:
Notes
VCC < VBC
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC.
Dec. 1992 B
4
bq2204A
DC Electrical Characteristics (TA = TOPR, VCC = 5V ± 10%)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
-
-
±1
µA
2.4
-
-
V
IOH = -2.0mA
VBC - 0.3
-
-
V
VBC > VCC, IOH = -10µA
IOL = 4.0mA
ILI
Input leakage current
VOH
Output high voltage
VOHB
VOH, BC supply
VOL
Output low voltage
-
-
0.4
V
ICC
Operating supply current
-
3
6
mA
4.55
4.62
4.75
V
THS = VSS
VPFD
Power-fail detect voltage
4.30
4.37
4.50
V
THS = VCC
VSO
Supply switch-over voltage
-
VBC
-
V
ICCDR
Data-retention mode
current
-
-
100
nA
Active backup cell
voltage
-
VBC1
-
V
VBC1 > VBC2 + VBSO
VBC
-
VBC2
-
V
VBC2 > VBC1 + VBSO
VBSO
Battery switch-over voltage
0.25
0.4
0.6
V
IOUT1
VOUT current
-
-
160
mA
VOUT > VCC - 0.3V
IOUT2
VOUT current
-
100
-
µA
VOUT > VBC - 0.2V
Note:
VIN = VSS to VCC
No load on outputs.
VOUT data-retention current
to additional memory not included.
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC.
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
CIN
Input capacitance
-
-
8
pF
Input voltage = 0V
COUT
Output capacitance
-
-
10
pF
Output voltage = 0V
Note:
This parameter is sampled and not 100% tested.
Dec. 1992 B
5
bq2204A
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5ns
Input and output timing reference levels
1.5V (unless otherwise specified)
5V
960
CECON
100pF
510
FG220102.eps
Figure 3. Output Load
Power-Fail Control (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tPF
VCC slew, 4.75V to 4.25V
300
-
-
µs
tFS
VCC slew, 4.25V to VSO
10
-
-
µs
Notes
tPU
VCC slew, 4.25V to 4.75V
0
-
-
µs
tCED
chip-enable propagation delay
-
7
10
ns
tAS
A,B set up to CE
0
-
-
ns
tCER
chip-enable recovery
40
80
120
ms
Time during which SRAM is
write-protected after VCC
passes VPFD on power-up.
tWPT
Write-protect time
40
100
150
µs
Delay after VCC slews down
past VPFD before SRAM is
write-protected.
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Dec. 1992 B
6
bq2204A
Power-Down Timing
tPF
4.75
VPFD
VCC
tFS
4.25
VSO
CE
tWPT
VOHB
CECON
TD220102.eps
Power-Up Timing
tPU
VCC
4.75
VPFD
4.25
VSO
tCER
CE
CECON
tCED
VOHB
tCED
TD220103.eps
Address-Decode Timing
A,B
tAS
CE
tCED
CECON1
tCED
CECON4
TD220402.eps
Dec. 1992 B
7
bq2204A
Data Sheet Revision History
Change No.
Page No.
1
All
1
1, 4–5
10% tolerance requires the THS
pin to be tied to VCC, not VOUT.
1
3
Energy cell input selection process alternates between BC1 and
BC2.
Note:
Description of Change
Nature of Change
bq2204A replaces bq2204.
Change 1 = Dec. 1992 changes from Sept. 1991
Dec. 1992 B
10
PACKAGE OPTION ADDENDUM
www.ti.com
3-Dec-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
BQ2204APN
ACTIVE
PDIP
N
16
25
Pb-Free (RoHS)
BQ2204ASN
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ2204ASN-N
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ2204ASN-NG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ2204ASNG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ2204ASNTR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ2204ASNTRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
CU NIPDAU N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Dec-2011
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ2204ASNTR
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ2204ASNTR
SOIC
D
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
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