ON NCP1082DER2G Integrated poe-pd & dc-dc converter controller with 9 v auxiliary supply support Datasheet

NCP1082
Integrated PoE-PD & DC-DC
Converter Controller with
9V Auxiliary Supply Support
Introduction
The NCP1082 is a member of ON Semiconductor’s Power over
Ethernet Powered Device (PoE−PD) product family and represents a
robust, flexible and highly integrated solution targeting demanding
Ethernet applications. It combines in a single unit an enhanced
PoE−PD interface fully supporting the IEEE 802.3af specification and
a flexible and configurable DC−DC converter controller.
The NCP1082’s exceptional capabilities enable applications to
smoothly transition from non−PoE to PoE enabled networks by also
supporting power from auxiliary sources such as AC power adapters
and battery supplies, eliminating the need for a second switching
power supply.
ON Semiconductor’s unique manufacturing process and design
enhancements allow the NCP1082 to deliver up to 13 W of regulated
power to support PoE applications according to the IEEE 802.3af
standard. This device leverages the significant cost advantages of
PoE−enabled systems to a broad spectrum of products in markets such
as VoIP phones, wireless LAN access points, security cameras, point
of sales terminals, RFID readers, industrial ethernet devices, etc.
The integrated current mode DC−DC controller facilitates isolated
and non−isolated fly−back, forward and buck converter topologies. It
has all the features necessary for a flexible, robust and highly efficient
design including programmable switching frequency, duty cycle up to
80 percent, slope compensation, and soft start−up.
The NCP1082 is fabricated in a robust high voltage process and
integrates a rugged vertical N−channel DMOS with a low loss current
sense technique suitable for the most demanding environments and
capable of withstanding harsh environments such as hot swap and
cable ESD events.
The NCP1082 complements ON Semiconductor’s ASSP portfolio
in communications and industrial devices and can be combined with
other high−voltage interfacing devices to offer complete solutions to
the communication, industrial and security markets.
Features
Powered Device Interface
Connections
Fully Supports IEEE 802.3af Standard
Regulated Power Output up to 13 W
Programmable Classification Current
Adjustable Under Voltage Lock Out
Programmable Inrush Current Limit
© Semiconductor Components Industries, LLC, 2008
November, 2008 − Rev. 0
1
TSSOP−20 EP
DE SUFFIX
CASE 948AB
NCP1082 = Specific Device Code
XXXX = Date Code
Y
= Assembly Location
ZZ
= Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
• Programmable Operational Current Limit up to 500 mA
• Over−temperature Protection
• Industrial Temperature Range −40°C to 85°C with Full
• Flexible Auxiliary Power Supply Support
• 9 V Front, Rear and Direct Auxiliary Supply
•
•
•
•
•
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Operation up to 150°C Junction Temperature
• 0.6 Ohm Hot−swap Pass−switch with Low Loss
•
1
Current Sense Technique
Vertical N−channel DMOS Pass−switch Offers the
Robustness of Discrete MOSFETs with Integrated
Temperature Control
Publication Order Number:
NCP1082/D
NCP1082
DC−DC Converter Controller
PIN DIAGRAM
• Current Mode Control
• Supports Isolated and Non−isolated DC−DC Converter
VPORTP
CLASS
UVLO
INRUSH
ILIM1
VPORTN1
RTN
VPORTN2
AUX
TEST
Applications
• Internal Voltage Regulators
• Wide Duty Cycle Range with Internal Slope
Compensation Circuitry
• Programmable Oscillator Frequency
• Programmable Soft−start Time
SS
FB
COMP
VDDL
VDDH
GATE
ARTN
NC
CS
OSC
1
Exposed
Pad
(Top View)
Ordering Information
Package
Shipping Configuration†
Temperature Range
NCP1082DEG
TSSOP−20 EP
(Pb−Free)
74 units / Tube
−40°C to 85°C
NCP1082DER2G
TSSOP−20 EP
(Pb−Free)
2500 / Tape & Reel
−40°C to 85°C
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
VPORTP
DETECTION
AUX
INTERNAL
SUPPLY
&
BANDGAP
THERMAL
SHUT
DOWN
AUXILIARY
SUPPLY
DETECTION
VDDH
VDDH
VDDL
VDDL
VDDL
CLASS
VDDL
CLASSIFICATION
5 mA
SS
VDDL
UVLO
UVLO
5K
VPORT
MONITOR
DC−DC
CONVERTER
CONTROL
1.2 V
FB
COMP
CS
OSC
OSC
VDDH
INRUSH
ILIM1
HOT SWAP SWITCH
INRUSH
ILIM1
GATE
CONTROL & CURRENT
LIMIT BLOCKS
NC
ARTN
RTN
VPORTN1,2
Figure 1. NCP1082 Block Diagram
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NCP1082
Simplified Application Diagrams
VAUX(+)
D4
RJ−45
Rclass
Cline
DB1
R1
Data
Pairs
Rinrush
Rilim1
Raux1
VPORTP
CLASS
Cpd
VDDH
VDDL
ILIM1
UVLO
Raux3
R2
Spare
Pairs
GATE
CS
FB
ARTN
RTN
AUX
TEST
VPORTN1
VPORTN2
SS
OSC COMP
DB2
Z_line
LD1
Rd1
Cvddl
NCP1082
D3
Voutput
Cload
INRUSH
Raux2
D1
T1
Cvddh
M1
Rslope
Rcs
Optocoupler R5
OC1
C2
R3
C1
Rosc
Z1
Css
R4
VAUX(−)
Figure 2. Isolated Fly−back Converter with Rear Auxiliary Support
Figure 2 shows the integrated PoE−PD switch and DC−DC controller configured to work in a fully isolated application. The
output voltage regulation is accomplished with an external opto−coupler and a shunt regulator (Z1).
VAUX(+)
D3
RJ−45
Rclass
Cline
DB1
R1
Data
Pairs
Rinrush
Rilim1
Raux1
VPORTP
CLASS
INRUSH
UVLO
Raux3
R2
Spare
Pairs
VDDL
Z_line
GATE
CS
AUX
TEST
FB
VPORTN1
ARTN
VPORTN2
RTN
SS
OSC COMP
Rosc
Css
VAUX(−)
LD1
Cvddl
NCP1082
D2
T1
Cvddh
ILIM1
Raux2
DB2
Cpd
VDDH
D1
R3
Voutput
Cload
Rd1
M1
Rslope
R4
Rcs
Rcomp
C1comp
C2comp
Figure 3. Non−Isolated Fly−back Converter with Rear Auxiliary Support
Figure 3 shows the integrated PoE−PD and DC−DC controller configured in a non−isolated fly−back configuration. A
compensation network is inserted between the FB and the COMP pin for overall stability of the feedback loop.
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NCP1082
Simplified Application Diagrams
VAUX(+)
D2
D4
RJ−45
Rclass
Cline
DB1
R1
Data
Pairs
Rinrush
Rilim1
Raux1
VPORTP
CLASS
INRUSH
UVLO
Cvddl
AUX
TEST
VPORTN1
VPORTN2
Raux3
R2
Spare
Pairs
GATE
CS
FB
ARTN
RTN
OSC COMP
SS
Z_line
D1
LD1
ILIM1
NCP1082
D3
R5
Cvddh
Cpd
VDDL
Raux2
DB2
VDDH
T1
Voutput
R3
Cload
Rd1
M1
Rslope
R4
Rcs
Rcomp
Rosc
Css
C1comp
VAUX(−)
C2comp
Figure 4. Non−Isolated Fly−back with Extra Winding and Rear Auxiliary Support
Figure 4 shows the same non−isolated fly−back configuration as Figure 3, but adds a 12 V auxiliary bias winding on the
transformer to provide power to the NCP1082 DC−DC controller via its VDDH pin. This topology shuts off the current flowing
from VPORTP to VDDH and therefore reduces the internal power dissipation of the PD, resulting in higher overall power
efficiency.
VAUX(+)
D5
RJ−45
Rclass
Cline
DB1
Rinrush
R1
Data
Pairs
Raux1
Rilim1
VPORTP
CLASS
UVLO
Raux3
R2
Spare
Pairs
Z_line
D1
AUX
TEST
FB
VPORTN1
ARTN
VPORTN2
RTN
SS
OSC COMP
Rosc
Css
VAUX(−)
Rd1
M1
Rslope
Rcomp
C1comp
Figure 5. Non−Isolated Forward Converter with Rear Auxiliary Support
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R3
R4
Rcs
C2comp
Figure 5 shows the NCP1082 used in a non−isolated forward topology.
D2
LD1
Cvddl
GATE
CS
L1
Voutput
Cvddh
VDDL
ILIM1
NCP1082
D4
DB2
VDDH
INRUSH
Raux2
D3 T1
Cpd
Cload
NCP1082
Table 1. Pin Descriptions
Name
Pin No.
Type
1
Supply
Positive input power. Voltage with respect to VPORTN1,2
6,8
Ground
Negative input power. Connected to the source of the internal pass−switch.
RTN
7
Ground
DC−DC controller power return. Connected to the drain of the internal pass−switch. It must
be connected to ARTN. This pin is also the drain of the internal pass−switch.
ARTN
14
Ground
DC−DC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
VDDH
16
Supply
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with
low ESR.
VDDL
17
Supply
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external low−power LED (1 mA max.) connected to ARTN, and can also be
used to add extra biasing current in the external opto−coupler. VDDL must be bypassed to
ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
CLASS
2
Input
Classification current programming pin. Connect a resistor between CLASS and VPORTN1,2.
INRUSH
4
Input
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN1,2.
ILIM1
5
Input
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN1,2.
UVLO
3
Input
DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN1,2. Connect
a resistor−divider from VPORTP to UVLO to VPORTN1,2 to set an external UVLO threshold.
GATE
15
Output
OSC
11
Input
NC
13
COMP
18
I/O
Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
opto−coupler. Voltage with respect to ARTN.
FB
19
Input
DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
CS
12
Input
Current−sense input for the DC−DC controller. Voltage with respect to ARTN.
SS
20
Input
Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the
soft−start timing.
AUX
9
Input
When the pin is pulled up, the IEEE detection mode is disabled and the device can be supplied by an auxiliary supply. Voltage with respect to VPORTN1,2. Connect the pin to the auxiliary supply through a resistor divider.
TEST
10
Input
Digital test pin must always be connected to VPORTN1,2.
VPORTP
VPORTN1
VPORTN2
EP
Description
DC−DC controller gate driver output pin.
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
No connect pin, must not be connected.
Exposed pad. Connected to VPORTN1,2 ground.
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NCP1082
Table 2. Absolute Maximum Ratings
Symbol
Min.
Max.
Units
Input power supply
−0.3
72
V
Voltage with respect to VPORTN1,2
RTN
ARTN
Analog ground supply 2
−0.3
72
V
Pass−switch in off−state
(Voltage with respect to VPORTN1,2)
VDDH
Internal regulator output
−0.3
17
V
Voltage with respect to ARTN
VDDL
Internal regulator output
−0.3
3.6
V
Voltage with respect to ARTN
CLASS
Analog output
−0.3
3.6
V
Voltage with respect to VPORTN1,2
INRUSH
Analog output
−0.3
3.6
V
Voltage with respect to VPORTN1,2
ILIM1
Analog output
−0.3
3.6
V
Voltage with respect to VPORTN1,2
UVLO
Analog input
−0.3
3.6
V
Voltage with respect to VPORTN1,2
OSC
Analog output
−0.3
3.6
V
Voltage with respect to ARTN
Analog input / output
−0.3
3.6
V
Voltage with respect to ARTN
FB
Analog input
−0.3
3.6
V
Voltage with respect to ARTN
CS
Analog input
−0.3
3.6
V
Voltage with respect to ARTN
SS
Analog input
−0.3
3.6
V
Voltage with respect to ARTN
NC
Open pin
VPORTP
COMP
Parameter
Conditions
AUX
Analog input
−0.3
3.6
V
Voltage with respect to VPORTN1,2
TEST
Digital input
−0.3
3.6
V
Voltage with respect to VPORTN1,2
Ta
Ambient temperature
−40
85
°C
Tj
Junction temperature
−
150
°C
Junction temperature (Note 1)
−
175
°C
−55
150
°C
37.6
°C/W
Tj−TSD
Tstg
Storage Temperature
TθJA
Thermal Resistance,
Junction to Air (Note 2)
ESD−HBM
Human Body Model
3.5
−
kV
ESD−CDM
Charged Device Model
750
−
V
Machine Model
300
−
V
Latch−up
±200
−
mA
System ESD (contact/air) (Note 3)
8/15
−
kV
ESD−MM
LU
ESD−SYS
Thermal shutdown condition
Exposed pad connected to VPORTN1,2 ground
per MIL−STD−883, Method 3015
per JEDEC Standard JESD78
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. Mounted on a 1S2P (3 layer) test board with copper coverage of 25 percent for the signal layers and 90 percent copper coverage for the
inner planes at an ambient temperature of 85°C in still air. Refer to JEDEC JESD51−7 for details.
3. Surges per EN61000−4−2, 1999 applied between RJ−45 and output ground and between adapter input and output ground of the demo board.
The specified values are the test levels and not the failure levels.
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NCP1082
Recommended Operating Conditions
Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the
functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the
recommended operating conditions for extended periods of time may affect device reliability.
All values concerning the DC−DC controller, VDDH and VDDL blocks are with respect to ARTN. All others are with respect
to VPORTN1,2 (unless otherwise noted).
Table 3. Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
0
57
V
1.4
9.5
V
23.75
26.25
kW
Conditions
INPUT SUPPLY
VPORT
Input supply voltage
VPORT = VPORTP −
VPORTN1,2
SIGNATURE DETECTION
Vsignature
Input supply voltage signature detection range
Rsignature
Signature resistance (Note 4)
Offset_current
I_VportP + I_Rtn
−
1.8
5
mA
VPORTP = RTN = 1.4 V
Sleep_current
I_VportP + I_Rtn
−
15
25
mA
VPORTP = RTN = 9.5 V
20.5
V
CLASSIFICATION
Vcl
Input supply voltage classification range
13
Iclass0
Class 0: Rclass 10 kW (Note 5)
0
−
4
mA
Iclass0 = I_VportP + I_Rdet
Iclass1
Class 1: Rclass 130 W (Note 5)
9
−
12
mA
Iclass1 = I_VportP + I_Rdet
Iclass2
Class 2: Rclass 69.8 W (Note 5)
17
−
20
mA
Iclass2 = I_VportP + I_Rdet
Iclass3
Class 3: Rclass 44.2 W (Note 5)
26
−
30
mA
Iclass3 = I_VportP + I_Rdet
Iclass4
Class 4: Rclass 30.9 W (Note 5)
36
−
44
mA
Iclass4 = I_VportP + I_Rdet
IDCclass
Internal current consumption during
classification (Note 6)
−
600
−
mA
For information only
38
40
V
UVLO pin tied to
VPORTN1,2
29.5
32
−
V
UVLO pin tied to
VPORTN1,2
UVLO
Vuvlo_on
Default turn on voltage (VportP rising)
Vuvlo_off
Default turn off voltage (VportP falling)
Vhyst_int
UVLO internal hysteresis
−
6
−
V
UVLO pin tied to
VPORTN1,2
Vuvlo_pr
UVLO external programming range
13
−
50
V
UVLO pin connected to the
resistor divider (R1 & R2)
AUX pin tied to VPORTN1,2
For information only
8.5
−
18
V
UVLO & AUX pins configured
for auxiliary supply support
Vuvlo_pr_aux
UVLO external programming VPORT range
with low auxiliary supply support
Vhyst_ext
UVLO external hysteresis
−
15
−
%
UVLO pin connected to the
resistor divider (R1 & R2)
Uvlo_Filter
UVLO on/off filter time
−
90
−
mS
For information only
AUXILIARY SUPPLY OPERATION – INPUT SUPPLY
Vaux_min1
VPORTP−ARTN voltage at startup
(required for VDDH > VDDH_Por_R)
8.7
−
−
V
VAUX rising − No external
load on VDDL & VDDH
Vaux_min2
VPORTP−ARTN voltage during PWM operation (required for VDDH > VDDH_Por_F)
8.5
−
−
V
Voltage with respect to
Ivddl_load1 & Ivddh_load1
for the load current conditions
4. Test done according to the IEEE 802.3af 2 Point Measurement. The minimum probe voltages measured at the PoE−PD are 1.4 V and 2.4 V,
and the maximum probe voltages are 8.5 V and 9.5 V.
5. Measured with an external Rdet of 25.5 kW between VPORTP and VPORTN1,2, and for 13 V < VPORT < 20.5 V (with VPORT = VPORTP
– VPORTN1,2).
6. This typical current excludes the current in the Rclass and Rdet external resistors.
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NCP1082
Table 3. Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
Conditions
AUXILIARY SUPPLY OPERATION – AUX PIN
AUX_threshold
AUX pin internal threshold
0.2
−
1.5
V
Voltage with respect to
VPORTN1,2.
AUX_bias_min
Minimum Voltage required on the AUX
pin for low auxiliary supply operation
1.5
−
−
V
Defined at VPORT = 8.5 V,
Voltage with respect to
VPORTN1,2
AUX_bias_max
Maximum Voltage allowed on the AUX pin
−
−
3.3
V
Voltage with respect to
VPORTN1,2
AUX_res_ladder
Resistor ladder value on AUX pin
−
−
25
kW
Between VAUX supply &
VPORTN1,2
AUXILIARY SUPPLY OPERATION – VDDL REGULATOR
Ivddl_load1
Current load on the VDDL pin with
VPORTP − ARTN = 8.5 V (Notes 7 and 8)
−
−
1
mA
Ivddh_load + Ivddl_load
< 4.5 mA
Ivddl_load2
Current load on the VDDL pin with
VPORTP − ARTN > 12.5 V
(Notes 7 and 8)
−
−
2.25
mA
Ivddh_load + Ivddl_load
< 10 mA
AUXILIARY SUPPLY OPERATION – VDDH REGULATOR
Ivddh_load1
Current load on the VDDH regulator with
VPORTP − ARTN = 8.5 V (Notes 7 and 8)
−
−
4.5
mA
Ivddh_load + Ivddl_load
< 4.5 mA
Ivddh_load2
Current load on the VDDH regulator with
VPORTP − ARTN > 12.5 V
(Notes 7 and 8)
−
−
10
mA
Ivddh_load + Ivddl_load
< 10 mA
PASS−SWITCH AND CURRENT LIMITS
Ron
Pass−switch Rds−on
−
0.6
1.2
W
Max Ron specified at
Tj = 130°C
I_Rinrush1
Rinrush = 150 kW (Note 9)
95
125
155
mA
Measured at RTN−
VPORTN1,2 = 3 V
I_Rinrush2
Rinrush = 57.6 kW (Note 9)
260
310
360
mA
Measured at RTN−
VPORTN1,2 = 3 V
I_Rilim1
Rilim1 = 84.5 kW (Note 9)
450
510
570
mA
Current limit threshold
0.8
1
1.2
V
RTN−VPORTNx falling;
voltage with respect to
VPORTN1,2
−
8.2
−
V
Voltage with respect to
VPORTN1,2
INRUSH AND ILIM1 CURRENT LIMIT TRANSITION
Vds_pgood
VDS required for power good status
Vds_pgood_hyst
VDS hysteresis required for power good
status
7. Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
8. See Figures 6 and 7 for specifications on the load current at lower or higher VPORTP-ARTN voltages. In case the application requires more
current capability on VDDL and VDDH, it is recommended to externally supply the VDDH pin with a bias winding from the transformer or
to add a diode between VAUX(+) and VDDH pin (verify the VAUX voltage does not exceed the VDDH voltage range).
9. The current value corresponds to the PoE−PD input current (the current flowing in the external Rdet and the quiescent current of the device
are included).
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NCP1082
Table 3. Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
Conditions
VDDH REGULATOR
VDDH_reg
Regulator output voltage
(Notes 10 and 11)
8.4
9
9.6
V
Ivddh_load + Ivddl_load < 10 mA
with Ivddl_load < 2.25 mA and
12.5 V < VPORTP − ARTN < 57 V
VDDH_Off
Regulator turn−off voltage
−
VDDH_reg
+ 0.5 V
−
V
For information only
VDDH_lim
VDDH regulator current limit
(Notes 10 and 11)
13
−
26
mA
VDDH_Por_R
VDDH POR level (rising)
7.3
−
8.3
V
VDDH_Por_F
VDDH POR level (falling)
6
−
7
V
VDDH_ovlo
VDDH over−voltage level (rising)
16
−
18.5
V
VDDL REGULATOR
VDDL_reg
Regulator output voltage
(Notes 10 and 11)
3.05
3.3
3.55
V
Ivddl_load < 2.25 mA with
Ivddh_load + Ivddl_load < 10 mA
and 12.5 V < VPORTP −
ARTN < 57 V
VDDL_Por_R
VDDL POR level (rising)
VDDL
– 0.2
−
VDDL
– 0.02
V
VDDL_Por_F
VDDL POR level (falling)
2.5
−
2.9
V
Gate_Tr
GATE rise time (10−90%)
−
−
50
ns
Cload = 2 nF, VDDHreg = 9 V
Gate_Tf
GATE fall time (90−10%)
−
−
50
ns
Cload = 2 nF, VDDHreg = 9 V
1.3
−
3
V
For information only
V
Voltage with respect to ARTN
GATE DRIVER
PWM COMPARATOR
VCOMP
COMP control voltage range
ERROR AMPLIFIER
Vbg_fb
Reference voltage
1.15
1.2
1.25
Av_ol
DC open loop gain
−
80
−
dB
For information only
GBW
Error amplifier GBW
1
−
−
MHz
For information only
Vss
Soft−start voltage range
−
1.15
−
V
Vss_r
Soft−start low threshold
(rising edge)
0.35
0.45
0.55
V
Iss
Soft−start source current
3
5
7
mA
324
360
396
mV
−
100
−
nS
SOFT−START
CURRENT LIMIT COMPARATOR
CSth
CS threshold voltage
Tblank
Blanking time
For information only
10. Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding.
11. Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
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9
NCP1082
Table 3. Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
−
80%
−
100
−
500
Units
Conditions
OSCILLATOR
DutyC
Maximum duty cycle
Frange
Oscillator frequency range
F_acc
Oscillator frequency accuracy
Fixed internally
kHz
%
±25
CURRENT CONSUMPTION
IvportP1
VPORTP internal current consumption
(Note 12)
−
2.5
3.5
mA
DC−DC controller off
IvportP2
VPORTP internal current consumption
(Note 13)
−
4.7
6.5
mA
DC−DC controller on
150
−
−
°C Tj
Tj = junction temperature
−
15
−
°C Tj
Tj = junction temperature
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thyst
Thermal hysteresis
THERMAL RATINGS
Ta
Ambient temperature
−40
−
85
°C
Tj
Junction temperature
−
−
125
150
°C
°C
Parametric values guaranteed
Max 1000 hours
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
2.50
2.25
LOAD CURRENT (mA)
LOAD CURRENT (mA)
12. Conditions
a. No current through the pass−switch
b. DC−DC controller inactive (SS shorted to RTN)
c. No external load on VDDH and VDDL
d. VPORTP = 57 V
13. Conditions
a. No current through the pass−switch
b. Oscillator frequency = 100 kHz
c. No external load on VDDH and VDDL
d. Aux winding not used
e. 2 nF on GATE, DC−DC controller enabled
f. VPORTP = 57 V
2.00
1.75
1.50
1.25
1.00
0.75
8.5 9.0
9.5
10
10.5 11
11.5
12 12.5
13 13.5
0.50
8.5 9.0
9.5
10
10.5 11
11.5
12 12.5
13 13.5
VPORTP−ARTN VOLTAGE DURING PWM
OPERATION (V)
VPORTP−ARTN VOLTAGE DURING PWM
OPERATION (V)
Figure 6. (Ivddl_load)max with Auxiliary
Supply Operation
Figure 7. (Ivddh_load+Ivddl_load)max with
Auxiliary Supply Operation
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10
NCP1082
Description of Operation
Powered Device Interface
Power Mode
The PD interface portion of the NCP1082 supports the
IEEE 802.3af defined operating modes: detection signature,
current source classification, inrush and operating current
limits. In order to give more flexibility to the user and also
to keep control of the power dissipation in the NCP1082,
both current limits are configurable. The device enters
operation once its programmable Vuvlo_on threshold is
reached, and operation ceases when the supplied voltage
falls below the Vuvlo_off threshold. Sufficient hysteresis
and Uvlo filter time are provided to avoid false power on/off
cycles due to transient voltage drops on the cable.
When the classification hand−shake is completed, the
PSE and PD devices move into the operating mode.
Under Voltage Lock Out (UVLO)
The NCP1082 incorporates an under voltage lock out
(UVLO) circuit which monitors the input voltage and
determines when to apply power to the DC−DC controller.
To use the default settings for UVLO (see Table 3), the pin
UVLO must be connected to VPORTN1,2. In this case the
signature resistor has to be placed directly between
VPORTP and VPORTN1,2, as shown in Figure 9.
Detection
VPORTP
During the detection phase, the incremental equivalent
resistance seen by the PSE through the cable must be in the
IEEE 802.3af standard specification range (23.75 kW to
26.25 kW) for a PSE voltage from 2.7 V to 10.1 V. In order
to compensate for the non−linear effect of the diode bridge
and satisfy the specification at low PSE voltage, the
NCP1082 presents a suitable impedance in parallel with the
25.5 kW Rdet external resistor. For some types of diodes
(especially Schottky diodes), it may be necessary to adjust
this external resistor.
When the Detection_Off level is detected (typically
11.5 V) on VPORTP, the NCP1082 turns on its internal
3.3 V regulator and biasing circuitry in anticipation of the
classification phase as the next step.
VPORT
VPORTN1,2
NCP1082
Figure 9. Default UVLO Settings
To define the UVLO threshold externally, the UVLO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN1,2 as shown in
Figure 10. The series resistance value of the external
resistors must add to 25.5 kW and replaces the internal
signature resistor.
Classification
Once the PSE device has detected the PD device, the
classification process begins. In classification, the PD
regulates a constant current source that is set by the external
resistor RCLASS value on the CLASS pin. Figure 8 shows
the schematic overview of the classification block. The
current source is defined as:
I class +
VPORTP
V bg
R class
UVLO
Rdet
VPORTP
R1
VPORT
UVLO
, (where V bg is 1.2 V)
R2
VDDA1
1.2 V
VPORTN1,2
NCP1082
CLASS
Figure 10. External UVLO Configuration
For a Vuvlo_on desired turn−on voltage threshold, R1 and
R2 can be calculated using the following equations:
Rclass
R1 ) R2 + R det
VPORTN1,2
R2 +
NCP1082
1.2
V ulvo_on
R det
When using the external resistor divider, the NCP1082 has
an external reference voltage hysteresis of 15 percent typical.
Figure 8. Classification Block Diagram
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11
NCP1082
Auxiliary Supply Support
To support applications connected to non PoE enabled
networks and minimize the bill of materials, the NCP1082
supports drawing power from an external supply. The
NCP1082 supports the IEEE 802.3af standard when the PoE
capability is available and acts as a regular DC-DC converter
when there is no power source on the Ethernet cable as
shown in Figure 11.
Auxiliary supply support can be implemented in three
ways depending on where the auxiliary supply is injected.
The front, rear and direct auxiliary supply configurations are
explained in more detail in the application note “NCP1082-3
PoE Auxiliary Supply Applications”.
D1
VAUX(+)
POE(+)
VPORTP
Raux2
Rdet1
NCP1082
Cpd
D2
VPORT
Optional −
for very low
VAUX only
Raux1
UVLO
Rdet2
AUX
Raux3
POE(−)
Pass
Switch
VPORTN1,2
VAUX(−)
Or
RTN
DC−DC Stage
to VPORTN1,2 (Front AUX Configuration)
to RTN (Rear AUX Configuration)
Figure 11. Front and Rear Auxiliary Supply Input with Support for Very Low Input Voltages
Vdp = 0.5 V the forward voltage drop of the NCP1082
internal diode, and
Vt is the desired voltage at the AUX pin.
Note that as soon the auxiliary supply is connected the
PoE interface (detection and classification) is disabled and
does not allow the PD device to be powered from the
Ethernet until the auxiliary supply is removed.
If the PoE PD device was drawing the current from the
Ethernet cable before the auxiliary supply is connected, the
power will continue to be supplied from the Ethernet cable
unless the voltage of the auxiliary supply is higher than the
Ethernet supply voltage.
When the auxiliary input supply is above 13.5 V, connect
the AUX pin to VPORTN1,2.. When the auxiliary supply is
below 13.5 V (but above 9 V), calculate the voltage dividers
Raux1, Raux3 and Raux2, Rdet1, Rdet2 to divide the input
voltage to at least 2 V at the UVLO pin and 2 V at the AUX
pin using the following formulas. Note the maximum
voltage is 3.3 V.
R aux3 +
R aux2 +
R aux1 V t
V aux * V dp * V t
V aux * V dp * V d * V t
V aux*V dp*Vd*Vt
Vt
*
845
24 K
Inrush and Operational Current Limitations
R aux1 + 20 KW
The inrush current limit and the operational current limit
are programmed individually by an external Rinrush and
Rilim1 resistors respectively connected between INRUSH
and VPORTN1,2, and between ILIM1 and VPORTN1,2 as
shown in Figure 12.
With
Vd is the voltage drop over the rectifiers and masking diodes
(typical 0.6 V), and
VDDA1
VDDA1
ILIM1 /
INRUSH
Vbg1
Ilim_ref
NCP1082
VPORTNx
Figure 12. Current Limitation Configuration (Inrush & Ilim1 Pins)
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12
NCP1082
Inrush
0
Ilim1
1
I_pass_switch
&
VDS_PGOOD
Vds_pgood
threshold
Current_limit_ON
detector
VDDA1
VDDA1
VDDA1
2V
1 V / 9.2 V
VPORTNx
RTN
Pass Switch
NCP1082
Figure 13. Inrush and Ilim1 Selection Mechanism
Thermal Shutdown
When VPORT reaches the UVLO_on level, the Cpd
capacitor is charged with the INRUSH current (in order to
limit the internal power dissipation of the pass−switch).
Once the Cpd capacitor is fully charged, the current limit
switches from the inrush current to the operational current
level (ilim1) as shown in Figure 13. This transition occurs
when both following conditions are satisfied:
1. The VDS of the pass−switch is below the
Vds_pgood low level (1 V typical).
2. The pass−switch is no longer in current limit
mode, meaning the gate of the pass−switch is
“high” (above 2 V typical).
The operational current limit will stay selected as long as
Vds_pgood is true (meaning that RTN−VPORTN1,2 is
below the high level of Vds_pgood). This mechanism allows
a current level transition without any current spike in the
pass−switch because the operational current limit (ilim1) is
enabled once the pass−switch is not limiting the current
anymore, meaning that the Cpd capacitor is fully charged.
The NCP1082 includes thermal protection which shuts
down the device in case of high power dissipation. Once the
thermal shutdown (TSD) threshold is exceeded, following
blocks are turned off:
• DC−DC controller
• Pass−switch
• VDDH and VDDL regulators
• CLASS regulator
When the TSD error disappears and if the input line
voltage is still above the UVLO level, the NCP1082
automatically restarts with the current limit set in the inrush
state, the DC−DC controller is disabled and the Css
(soft−start capacitor) discharged. The DC−DC controller
becomes operational as soon as RTN−VPORTN1,2 is below
the Vds_pgood threshold.
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13
NCP1082
DC−DC Converter Controller
The NCP1082 implements a current mode DC−DC converter controller which is illustrated in Figure 14.
VPORTP
OSC
VDDL
5 kW
1.2 V
Oscillator
&
Sawtooth
Generator
FB
Reset
CLK
VDDL
Set
CLK
3.3 V LDO
COMP
9 V LDO
Current Slope
Compensation
10 mA
0
VDDH
PWM comp
CS
Blanking
time
S
Q
1.45 V
11 kW
Gate
Driver
GATE
R
2
ARTN
Current limit
comp
VDDL
360 mV
5 mA
SS
Soft−start
Figure 14. DC−DC Controller Block Diagram
Internal VDDH and VDDL Regulators and Gate Driver
In isolated topologies the error amplifier is not used
because it is already implemented externally with the shunt
regulator on the secondary side of the DC−DC controller
(see Figure 2). Therefore the FB pin must be strapped to
ARTN and the output transistor of the opto−coupler has to
be connected on the COMP pin where an internal 5 kW
pull−up resistor is tied to the VDDL supply (see Figure 14).
An internal linear regulator steps down the VPORTP
voltage to a 9 V output on the VDDH pin. VDDH supplies
the internal gate driver circuit which drives the GATE pin
and the gate of the external power MOSFET. The NCP1082
gate driver supports an external MOSFET with high Vth and
high input gate capacitance. A second LDO regulator steps
down the VDDH voltage to a 3.3 V output on VDDL. VDDL
powers the analog circuitry of the DC−DC controller.
In order to prevent uncontrolled operations, both regulators
include power−on−reset (POR) detectors which prevent the
DC−DC controller from operating when either VDDH or
VDDL is too low. In addition, an over−voltage lockout
(OVLO) on the VDDH supply disables the gate driver in case
of an open−loop converter with a configuration using the bias
winding of the transformer (see Figure 4).
Both VDDH and VDDL regulators turn on as soon as
VPORT reaches the Vuvlo_on threshold.
Soft−Start
The soft−start function provided by the NCP1082 allows
the output voltage to ramp up in a controlled fashion,
eliminating output voltage overshoot. This function is
programmed by connecting a capacitor Css between the SS
and ARTN pins.
While the DC−DC controller is in POR, the capacitor Css
is fully discharged. After coming out of POR, an internal
current source of 5 mA typically starts charging the capacitor
Css to initiate soft−start. When the voltage on SS pin has
reached 0.45 V (typical), the gate driver is enabled and
DC−DC operation starts with a duty cycle limit which
increases with the SS pin voltage. The soft−start function is
finished when the SS pin voltage goes above 1.6 V for which
the duty cycle limit reaches its maximum value of 80
percent.
Soft−start can be programmed by using the following
equation:
Error Amplifier
In non−isolated converter topologies, the high gain
internal error amplifier of the NCP1082 and the internal
1.2 V reference voltage regulate the DC−DC output voltage.
In this configuration, the feedback loop compensation
network should be inserted between the FB and COMP pins
as shown in Figures 3, 4 and 5.
tss(ms) + 0.23
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14
Css(nf)
NCP1082
Current Limit Comparator
conduction mode (CCM) and when the duty cycle is close
or above 50 percent, the NCP1082 integrates a current slope
compensation circuit. The amplitude of the added slope
compensation is typically 110 mV over one cycle.
As an example, for an operating switching frequency of
250 kHz, the internal slope provided by the NCP1082 is
27.5 mV/ mA typically.
The NCP1082 current limit block behind the CS pin
senses the current flowing in the external MOSFET for
current mode control and cycle−by−cycle current limit. This
is performed by the current limit comparator which, on the
CS pin, senses the voltage across the external Rcs resistor
located between the source of the MOSFET and the ARTN
pin.
The NCP1082 also provides a blanking time function on
CS pin which ensures that the current limit and PWM
comparators are not prematurely trigged by the current spike
that occurs when the switching MOSFET turns on.
DC−DC Controller Oscillator
The frequency is configured with the Rosc resistor
inserted between OSC and ARTN, and is defined by the
following equation:
R OSC(kW) +
Slope Compensation Circuitry
To overcome sub−harmonic oscillations and instability
problems that exist with converters running in continuous
38600
F OSC(kHz)
The duty cycle limit is fixed internally at 80 percent.
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15
NCP1082
PACKAGE DIMENSIONS
TSSOP−20 EP
CASE 948AB−01
ISSUE O
D
B
B
DETAIL B
20
e/2
0.20 C A-B D
11
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.07 IN EXCESS OF THE LEAD WIDTH AT
MMC. DAMBAR CANNOT BE LOACTED ON THE
LOWER RADIUS OR THE FOOT OF THE LEAD.
4. DIMENSIONS b, b1, c, c1 TO BE MEASURED
BETWEEN 0.10 AND 0.25 FROM LEAD TIP.
5. DATUMS A AND B ARE ARE DETERMINED AT DATUM
H. DATUM H IS LOACTED AT THE MOLD PARTING
LINE AND COINCIDENT WITH LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY.
6. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.15 PER SIDE. D AND E1 ARE
DETERMINED AT DATUM H.
2X 10 TIPS
E1
DETAIL B
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN 1
REFERENCE
1
E
b
b1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
D
c c1
10
e
20X
A
SECTION B−B
b
0.10
TOP VIEW
M
C A-B D
A2
B
0.05 C
B
A
DETAIL A
END VIEW
0.08 C
20X
DIM
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L2
M
P
P1
M
SIDE VIEW
A1
C
SEATING
PLANE
H
L2
P
SEATING
PLANE
GAUGE
PLANE
L
C
DETAIL A
MILLIMETERS
MAX
MIN
--1.10
0.05
0.15
0.85
0.95
0.19
0.30
0.19
0.25
0.09
0.20
0.09
0.16
6.40
6.60
6.40 BSC
4.30
4.50
0.65 BSC
0.50
0.70
0.25 BSC
0_
8_
--4.20
--3.00
SOLDERING FOOTPRINT*
P1
4.30
BOTTOM VIEW
6.76
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
20X
0.98
3.10
0.65
PITCH
The product described herein may be covered by one or more US patents pending.
20X
0.35
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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