SEMICONDUCTOR TECHNICAL DATA The MC100LVEL/EL90 is a triple ECL to PECL translator. The device receives either standard or low voltage differential ECL signals and translates them to either standard or low voltage differential PECL output signals. The LVEL device can handle the low voltage signals while the EL device is designed for the standard signals. It is possible to have low voltage signals on one side and standard signals on the other if the LVEL90 is used. • • • • 500ps Propagation Delays Fully Differential Design Supports both Standard and Low Voltage Operation 20 1 20–Lead SOIC Packaging A VBB output is provided for interfacing with single ended ECL signals at the input. If a single ended input is to be used the VBB output should be connected to the D input. The active signal would then drive the D input. When used the VBB output should be bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the EL90 under single ended input switching conditions, as a result this pin can only source/sink up to 0.5mA of current. DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 To accomplish the level translation the EL/LVEL90 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins as expected are connected to the system ground plain. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors. Under open input conditions, the D input will be biased at VEE/2 and the D input will be pulled to VEE. This condition will force the Q output to a LOW, ensuring stability. PIN NAMES Pins Function Dn Qn VBB ECL Inputs PECL Outputs ECL Reference Voltage Output Logic Diagram and Pinout: 20-Lead SOIC (Top View) VCC Q0 Q0 GND Q1 Q1 GND Q2 Q2 VCC 20 19 18 17 16 15 14 13 12 11 PECL PECL PECL ECL ECL ECL 1 2 3 4 5 6 7 8 9 10 VCC D0 D0 VBB D1 D1 VBB D2 D2 VEE 7/95 Motorola, Inc. 1996 4–1 REV 1 MC100LVEL90 MC100EL90 ECL INPUT DC CHARACTERISTICS –40°C Symbol Characteristic EL90 LVEL90 0°C 25°C Min Max Min Max Min –4.2 –3.0 –5.5 –3.8 –4.2 –3.0 –5.5 –3.8 –4.2 –3.0 Typ 85°C Max Min Max Unit –5.5 –3.8 –4.2 –3.0 –5.5 –3.8 V 150 µA VEE Power Supply Voltage IIH Input HIGH Current IIL Input LOW Current 0.5 0.5 0.5 0.5 µA VPP Minimum Peak-to-Peak Input1 150 150 150 150 mV VIH Input HIGH Voltage –1165 –880 –1165 –880 –1165 –880 –1165 –880 V VIL Input LOW Voltage –1810 –1475 –1810 –1475 –1810 –1475 –1810 –1475 V VBB Reference Output –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V IEE Power Supply Current 8.0 mA 150 150 8.0 150 8.0 6.0 8.0 Condition 1. 150mV input guarantees full logic swing at the output. LVPECL OUTPUT DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Max Min Max Min Typ Max Min Max Unit VCC Power Supply Voltage 3.0 3.8 3.0 3.8 3.0 3.3 3.8 3.0 3.8 V VOH Output HIGH Voltage1 2.215 2.42 2.275 2.42 2.275 2.35 2.42 2.275 2.42 V VCC = 3.3V VOL Output LOW Voltage1 1.47 1.745 1.49 1.68 1.49 1.60 1.68 1.49 1.68 V VCC = 3.3V 20 24 26 mA IGND Power Supply Current 1. Levels will vary 1:1 with VCC. 24 24 Condition PECL OUTPUT DC CHARACTERISTICS –40°C Symbol 0°C 25°C Characteristic Min Max Min Max Min VCC Power Supply Voltage 4.75 5.25 4.75 5.25 4.75 VOH Output HIGH Voltage1 3.915 4.12 3.975 4.12 3.975 VOL Output LOW Voltage1 3.17 3.445 3.19 3.38 3.19 IGND Power Supply Current 1. Levels will vary 1:1 with VCC. MOTOROLA 24 24 4–2 Typ 85°C Max Min Max Unit 5.25 4.75 5.25 V Condition 4.05 4.12 3.975 4.12 V VCC = 5.0V 3.30 3.38 3.19 3.38 V VCC = 5.0V 20 24 26 mA ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL90 MC100EL90 MC100LVEL90 AC CHARACTERISTICS (VEE = –3.0V to –3.8V; VCC = 3.0V to 3.8V) –40°C Symbol Characteristic Min 390 340 Max Min 590 640 410 360 Typ 25°C Max Min 610 660 420 370 Typ 85°C Max Min 620 670 460 410 Typ Max Unit 660 710 ps 100 200 ps tPLH tPHL Propagation Delay D to Q tSKEW Skew Output–to–Output1 Part–to–Part (Diff)1 Duty Cycle (Diff)2 VPP Minimum Input Swing3 150 150 150 150 VCMR Common Mode Range4 See4 –0.4 See4 –0.4 See4 –0.4 See4 –0.4 tr tf Output Rise/Fall Times Q (20% – 80%) 230 500 230 500 230 500 230 500 1. 2. 3. 4. Diff S.E. Typ 0°C 20 100 200 20 25 100 200 20 25 100 200 20 25 25 mV V ps Skews are valid across specified voltage range, part–to–part skew is for a given temperature. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. VCMRmin depends on VEE, VPP and temperature. At VPP < 500mV and –40°C, VCMR is VEE +1.3V; and for 0–85°C, VCMR is VEE +1.2V. At VPP ≥ 500mV and –40°C, VCMR is VEE +1.5V; and for 0–85°C, VCMR is VEE +1.4V. MC100EL90 AC CHARACTERISTICS (VEE = –4.20V to –5.5V; VCC = 4.5V to 5.5V) –40°C Symbol Characteristic Min tPLH tPHL Propagation Delay D to Q Diff S.E. tSKEW Skew Output–to–Output1 Part–to–Part (Diff)1 Duty Cycle (Diff)2 Typ 390 340 20 0°C Max Min 590 640 410 360 100 200 Typ 20 25 25°C Max Min 610 660 420 370 100 200 Typ 20 25 85°C Max Min 620 670 460 410 100 200 Typ 20 25 Max Unit 660 710 ps 100 200 ps 25 VPP Minimum Input Swing3 150 VCMR Common Mode Range4 See4 –0.4 See4 –0.4 See4 –0.4 See4 –0.4 tr tf Output Rise/Fall Times Q (20% – 80%) 230 500 230 500 230 500 230 500 1. 2. 3. 4. 150 150 150 mV V ps Skews are valid across specified voltage range, part–to–part skew is for a given temperature. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. VCMRmin depends on VEE, VPP and temperature. At VPP < 500mV and –40°C, VCMR is VEE +1.3V; and for 0–85°C, VCMR is VEE +1.2V. At VPP ≥ 500mV and –40°C, VCMR is VEE +1.5V; and for 0–85°C, VCMR is VEE +1.4V. ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVEL90 MC100EL90 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A – 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 1 –B – P 10 PL A B 0.010 (0.25) M B M 10 D 20 PL 0.010 (0.25) J M T S S F R X 45° C –T G K 18 PL SEATING – PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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