LINER LTC2150-14 300mhz digital predistortion receiver Datasheet

LTM9013
300MHz Digital
Predistortion Receiver
FEATURES
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DESCRIPTION
Integrated I/Q Demodulator, IF Amplifier, and Dual
14-Bit, 310Msps High Speed ADC
External Highpass Filter Allows Bandwidth
Adjustment
300MHz Lowpass Filter for Each Channel
RF Input Frequency Range: 0.7GHz to 4GHz
50Ω Single-Ended RF Port
50Ω Differential LO Port
Frequency Flatness: 1.3dB Typical
66dBc IM3 Level at –7dBFS
59dB SNR at –1dBFS
Parallel DDR LVDS Outputs
Clock Duty Cycle Stabilizer
Low Power: 2.6W
Shutdown and Nap Modes
15mm × 15mm BGA Package
The LTM®9013 is a 300MHz digital predistortion receiver.
Utilizing an integrated system in a package (SiP) technology, it is a μModule® (micromodule) receiver that includes
a dual high speed 14-bit A/D converter, lowpass filter,
differential gain stages and a quadrature demodulator.
The LTM9013 is perfect for digital predistortion applications, with AC performance that includes 59dB SNR and
1.3dB frequency flatness from DC to 300MHz. A highpass
filter or simple AC coupling are used external to the device
for design flexiblity. The integrated on-chip broadband
transformers provide a 50Ω single-ended interface at
the RF input.
A 5V supply powers the demodulator and a 3.3V supply
powers the IF amplifiers for minimal distortion. A 1.8V
supply allows low power ADC operation. A separate output
supply allows the DDR LVDS outputs to drive 1.8V logic.
An optional multiplexer allows both channels to share a
digital output bus. An optional clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
APPLICATIONS
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Telecommunications
Wideband, Low IF Receivers
Digital Predistortion Receivers
Cellular Base Stations
L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation.
TYPICAL APPLICATION
100Ω
5V
VCC1
5V
100Ω
LTM9013
15nH
0.01µF
64k Point FFT
fIN = 1950MHz, –1dBFS
6.8pF
15nH
0.01µF
VDD
1.8V
VCC2
3.3V
0
GAIN_Q GAIN_I
–10
OVDD
1.8V
–20
ADC
CLKOUT
0°
LNA
90°
ADC CLK
OF
GND
SCK CS
SDI SDO
GND
PAR/SER
9013 TA01
100Ω
5V
100Ω
15nH
0.01µF
6.8pF
15nH
–40
–50
–60
–70
–80
–90
ADC
LO IN
AMPLITUDE (dBFS)
–30
–100
–110
–120
0
16 32 48 64 80 96 112 128 144 160
FREQUENCY (MHz)
9013 TA01b
0.01µF
9013f
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1
LTM9013
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage
VCC1....................................................... –0.3V to 5.5V
VCC2....................................................... –0.3V to 3.8V
VDD, OVDD.............................................. –0.3V to 2.0V
Analog Input Voltage
EN, EIP2, REF, IP2I, IP2Q............–0.3V to VCC1 + 0.3V
PAR/SER, SENSE...................... –0.3V to (VDD + 0.2V)
Digital Input Voltage (Note 3)
CLK+, CLK– .............................. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4)
CS, SDI, SCK.......................................... –0.3V to 3.9V
RF Input DC Voltage................................................ ±0.1V
LO+, LO – Input DC Voltage..............–0.3V to VCC1 + 0.3V
Analog Input Current
+IN_I, –IN_I, +IN_Q, –IN_Q............................. ±20mA
GAIN_I, GAIN_Q, EN_I, EN_Q, SHDN_I,
SHDN_Q........................................................... ±10mA
LO+, LO – Input Power......................................... +10dBm
RF Input Power...................................................+20dBm
Analog Input Power, Continuous
+IN_I, –IN_I, +IN_Q, –IN_Q............................ +15dBm
Analog Input Power, 100μs Pulse
+IN_I, –IN_I, +IN_Q, –IN_Q............................+20dBm
Analog Output Voltage
+OUT_I, –OUT_I,
+OUT_Q, –OUT_Q..........................2.5V to VCC1 + 0.3V
Digital Output Voltage
SDO ...................................................... –0.3V to 3.9V
Except SDO............................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTM9013C................................................ 0°C to 70°C
LTM9013I.............................................–40°C to 85°C
Storage Temperature Range................... –55°C to 125°C
PIN CONFIGURATION
1
2
3
4
5
6
TOP VIEW
7 8 9
10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
BGA PACKAGE
196-LEAD (15mm × 15mm × 2.82mm)
TJMAX = 125°C, θJA = 20°C/W, θJCbottom = 6°C/W, θJCtop =19°C/W, θJB =9°C/W
θ VALUES DEFINED PER JESD 51-12
WEIGHT = 1.35g
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions
be observed when handling the RF and LO inputs of the
LTM9013.
9013f
2
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LTM9013
ORDER INFORMATION
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM9013CY-AA#PBF
LTM9013CY-AA#PBF
LTM9013Y-AA
196-Lead (15mm × 15mm × 2.8mm) BGA
0°C to 70°C
LTM9013IY-AA#PBF
LTM9013IY-AA#PBF
LTM9013Y-AA
196-Lead (15mm × 15mm × 2.8mm) BGA
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PRF = –5dBm, PLO = 0dBm (Notes 5, 7) unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
RF Input Frequency Range
No External Matching (Mid Band)
with External Matching (Low Band, High Band)
MIN
1.5 to 2.7
0.7 to 4.0
GHz
GHz
LO Input Frequency Range
No External Matching (Mid Band)
With External Matching (Low Band, High Band)
1.5 to 2.7
0.7 to 4.0
GHz
GHz
0.5 to 300
MHz
IF Frequency Range
TYP
MAX
UNITS
RF Input Return Loss
ZO = 50Ω, 1.5GHz to 2.7GHz, Internally Matched
>10
LO Input Return Loss
ZO = 50Ω, 1.5GHz to 2.7GHz, Internally Matched
>10
dB
RF Input Power for –1dBFS
RF = 2140MHz, LO = 1990MHz (Figure 14)
–5
dBm
–6 to +6
dBm
LO Input Power
dB
I/Q Gain Mismatch
RF = 2140MHz, LO = 1990MHz (Figure 14)
0.15
dB
I/Q Phase Mismatch
RF = 2140MHz, LO = 1990MHz (Figure 14)
1
Deg
LO to RF Leakage
LO = 1990MHz
–55
dBm
RF to LO Isolation
RF = 2140MHz
58
dBm
Gain Flatness (Notes 5, 6)
fIF = 500kHz to 300MHz (Figure 14)
0.5
dB
Lowpass Filter Cutoff Frequency
0.5dB Point
300
MHz
Resolution (No Missing Codes)
l
Integral Linearity Error (Note 8)
Differential Analog Input
Differential Linearity Error
Differential Analog Input
Offset Error (Note 9)
14
Bits
±4.5
LSB
–1
±0.35
1
LSB
–186
±62
186
LSB
9013f
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3
LTM9013
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. PRF = –5dBm, PLO = 0dBm (Notes 5, 7) unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IIP3
Input 3rd Order Intercept, 1 Tone
RF = 2140MHz, LO = 1990MHz
30
dBm
IIP2
Input 2nd Order Intercept, 1 Tone
RF = 2140MHz, LO = 1990MHz
56
dBm
SNR
Signal-to-Noise Ratio at –1dBFS
RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
l
59
59
62
dBFS
dBFS
Spurious Free Dynamic Range
2nd or 3rd Harmonic
RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
l
60
65
70
dB
dB
Spurious Free Dynamic Range
4th or Higher
RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
75
80
dB
dB
Signal-to-Noise Plus Distortion Ratio
RF = 2140MHz, LO = 1990MHz (Figure 14)
fIF = 150MHz (Note 6)
58
61
dBFS
dBFS
66
dB
SFDR
S/(N+D)
IMD3
Intermodulation Distortion at –7dBFS per
Tone
MIN
l
58
RF = 2140MHz and 2141MHz, LO = 1990MHz
(Figure 14)
TYP
MAX
UNITS
ANALOG INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Demodulator Adjust Inputs (IP2I, IP2Q)
Input Voltage
0
Input Impedance
1.3
2||1
Settling Time
For Step Input; Output with 90% of Final Value
V
kΩ||pF
2
μs
Demodulator Adjust Input (REF)
Input Voltage
0.4
Input Impedance
0.5
0.7
8||1
V
MΩ||pF
Amplifier Analog Inputs (+IN_I, –IN_I, +IN_Q, –IN_Q)
VIN(DIFF) = 100mV
Differential Input Resistance
49
57
65
Ω
Input Common Mode Voltage
640
mV
Minimum Input Frequency (3dB Corner)
500
kHz
Amplifier Gain Control Analog Inputs (GAIN_I, GAIN_Q)
RIN
IIL
Input Resistance
Input Low Current
Gain Control Range
GAIN_I, GAIN_Q = 1.0V, RIN = 1V/∆IIL
7.8
7.2
9.2
l
10.6
12.8
kΩ
kΩ
–9
–10
–5
l
–1
–1
µA
µA
l
27.5
29
30.5
GAIN_I, GAIN_Q = 0V
VGAIN = 0.2V to 1.2V
Temperature Coefficient of Gain at Fixed
Gain Control Voltage
–0.007
30.6
32.6
dB
dB/°C
34.7
dB/V
Gain Control Slope
Gain Control Voltage = 0.2V to 1V, Slope of the
Least-Square Fit Line
Average Conformance Error to Gain
Slope Line
Gain Control Voltage = 0.2V to 1V, Standard
Error to the Least-Square Fit Line
0.12
dB
Maximum Conformance Error to Gain
Slope Line
Gain Control Voltage = 0.2V to 1V, Maximum
Error to the Least-Square Fit Line
0.2
dB
l
9013f
4
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LTM9013
ANALOG INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADC Analog Inputs (SENSE)
Input Leakage Current
1.1V < SENSE < 1.2V
–1
1
μA
Demodulator Analog Outputs (+OUT_I, –OUT_I, +OUT_Q, –OUT_Q)
VCC1 – 1.5V
Common Mode Voltage
Differential Output Impedance
V
50||6
Ω||pF
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Demodulator Logic Inputs (EN, EIP2)
VIH
High Level Input Voltage
VCC = 5V
l
VIL
Low Level Input Voltage
VCC = 5V
l
Input Pull-Up Resistance
VCC = 5V, VEN = 4.4V to 2.6V
EIP2 Input Current
EIP2 = 5V
2
V
0.3
V
100
kΩ
40
μA
Turn-On Time
0.2
µs
Turn-Off Time
0.8
µs
I and Q Channel Logic Inputs (EN_I, EN_Q, SHDN_I, SHDN_Q)
VIH
VIL
High Level Input Voltage
VCC = 3.3V
l
l
2.2
V
Low Level Input Voltage
VCC = 3.3V
Input Pull-Up Resistance
VCC = 3.3V, VEN_I,EN_Q = 0V to 0.5V
0.8
Input High Current
EN_I, EN_Q = 2.2V, SHDN_I, SHDN_Q = 2.2V
–30
–15
–1
µA
Input Low Current
EN_I, EN_Q = 0.8V, SHDN_I, SHDN_Q = 0.8V
–60
–30
–1
µA
1.5
V
V
100
V
kΩ
ADC Encode Clock Inputs (CLK+, CLK–)
Differential Input Voltage
VDD = 1.8V
Common Mode Input Voltage
Internally Set
Externally Set
l
l
0.2
1.1
Input Resistance
Input Capacitance
(Note 10)
V
1.2
10
kΩ
2
pF
ADC Logic Inputs (SDI, SCK, CS)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
Input Current
VIN = 0V to 3.6V
l
Input Capacitance
(Note 10)
1.3
V
–10
0.6
V
10
μA
3
pF
ADC Logic Inputs (PAR/SER)
Input Leakage Current
–1
0 < PAR/SER < VDD
1
μA
10
µA
ADC Logic Output (SDO)
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
Logic High Output Leakage Current
SDO = 0V to 3.6V
Output Capacitance
(Note 10)
200
l
–10
4
Ω
pF
9013f
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5
LTM9013
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mV
mV
Data Outputs (OVDD = 1.8V)
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
V
V
100
Ω
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
VCC1
Demodulator and Amplifier Supply Voltage
l
4.75
5.25
V
VCC2
Amplifier Analog Supply Voltage
l
2.7
3.3
3.6
V
VDD
ADC Analog Supply Voltage
l
1.74
1.8
1.9
V
OVDD
ADC Digital Output Supply Voltage
l
1.74
1.8
1.9
V
ICC1
Demodulator and Amplifier Supply Current
l
285
330
mA
ICC1(SHDN)
Demodulator and Amplifier Shutdown
Current
l
16
20
mA
ICC2
Amplifier Supply Current
l
132
160
mA
IDD
ADC Supply Current
l
335
385
mA
IOVDD
Digital Supply Current
3.5mA Mode
80
90
mA
ADC Sleep Power
ADC Programmed for Sleep Mode, No CLK
EN = 0V, EN_I, EN_Q = 3.3V, SHDN_I,
SHDN_Q = 0V
MIN
TYP
MAX
5
Total Power Dissipation
UNITS
mW
2.6
W
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
fS
Sampling Frequency
CONDITIONS
MIN
tL
CLK Low Time
tH
CLK High Time
tJITTER
Sample-and-Hold Acquisition Delay Time
Jitter
0.15
tAP
Sample-and-Hold Acquisition Delay Time
1
l
1
Duty Cycle Stabilizer Off (Note 10)
Duty Cycle Stabilizer On (Note 10)
l
l
1.5
1.2
Duty Cycle Stabilizer Off (Note 10)
Duty Cycle Stabilizer On (Note 10)
l
l
1.5
1.2
TYP
MAX
UNITS
310
MHz
1.6
1.6
50
50
ns
ns
1.6
1.6
50
50
ns
ns
psRMS
ns
DATA Outputs (Note 10)
tD
CLK to DATA Delay
CL = 5pF
l
1.7
2
2.3
ns
tC
CLK to CLKOUT Delay
CL = 5pF
l
1.3
1.6
2
ns
tSKEW
DATA to CLKOUT Skew
tD – tC
l
0.3
0.4
0.55
ns
9013f
6
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LTM9013
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Port Timing (Note 10)
tSCK
SCK Period
tS
Write Mode
Readback Mode CSDO = 20pF, RPULLUP = 2kΩ
40
250
ns
ns
CS to SCK Set-up Time
5
ns
tH
SCK to CS Hold Time
5
ns
tDS
SDI Set-Up Time
5
ns
tDH
SDI Hold Time
tDO
SCK Falling to SDO Valid
l
l
5
Readback Mode CSDO = 20pF, RPULLUP = 2kΩ
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD,
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
ns
125
ns
Note 5: Using test circuit 1 (see Figure 14 Design Example in Applications
Information section).
Note 6: Signal applied to the ±INn pins and measures only the amplifier
and ADC.
Note 7: VCC1 = 5V, VCC2 = 3.3V, VDD = 1.8V, EN = 5V, EN_I, EN_Q = 0V,
GAIN_I, GAIN_Q = 1.2V, SHDN_I, SHDN_Q = 3.3V, SENSE = 1.15V,
fS = 310MHz, unless otherwise noted.
Note 8: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 9: DC offset is the ADC output code with no RF or LO input signal
applied the module.
Note 10: Guaranteed by design, not subject to test
9013f
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7
LTM9013
TYPICAL PERFORMANCE CHARACTERISTICS
64k Point FFT, fIN = 1950MHz,
–1dBFS
Baseband Frequency Response
AMPLITUDE (dBFS)
–1
AMPLITUDE (dB)
–2
–3
–4
–5
–6
0
0
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–70
–80
–80
–90
–100
–110
–110
0
–120
16 32 48 64 80 96 112 128 144 160
FREQUENCY (MHz)
HD2 at 150MHz IF vs LO Power
HD2 at 150MHz IF vs RF Drive
–45
–40
60.5
–50
–45
–55
59.0
–65
–50
HD2, Q CHANNEL
–60
HD2 (dBc)
HD2 (dBc)
60.0
HD2, I CHANNEL
58.5
0
5
RF DRIVE (dBm)
10
–80
–22 –18 –14 –10 –6 –2 2
LO POWER (dBm)
15
HD2, I CHANNEL
–65
–75
–5
HD2, Q CHANNEL
–55
–60
–70
58.0
6
9013 G04
–70
10
–5
HD3 at 150MHz IF vs RF Drive
IM3 at 150MHz vs RF Drive
–45
–10
–50
–20
IM3 (dBc)
–70
–75
–5
0
5
10
15
RF DRIVE (dBm)
9013 G07
ISOLATION (dB)
–45
–50
–55
–60
–65
15
–30
–40
–50
–70
–60
–75
–70
–80
–12 –10 –8 –6 –4 –2 0 2 4 6
RF DRIVE PER TONE (dBm)
10
LO to RF Isolation
0
–65
5
RF DRIVE (dBm)
9013 G06
–40
–60
0
9013 G05
–40
–55
16 32 48 64 80 96 112 128 144 160
FREQUENCY (MHz)
9013 G03
61.0
59.5
0
9013 G02
SNR at 150MHz IF vs RF Drive
SNR (dB)
–60
–70
–100
9013 G01
HD3 (dBc)
–40
–50
–90
–120
50 100 150 200 250 300 350 400 450 500
BASEBAND FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
64K Point FFT, fIN = 1925MHz,
1975MHz, –7dBFS per Tone
8 10
9013 G08
–80
1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5
LO FREQUENCY (GHz)
9013 G09
9013f
8
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LTM9013
PIN FUNCTIONS
Supply Pins
VCC1 (Pin B7): Analog 5V Supply for Demodulator and
Amplifiers. The specified operating range is 4.75V to 5.25V.
The voltage on this pin provides power for the demodulator
and amplifier stages only and is internally bypassed to GND.
VCC2 (Pins A2, A3, A12, A13, D1, D12): Analog 3.3V Supply for Amplifiers. The specified operating range is 2.7V to
3.6V. VCC2 is internally bypassed to GND.
V DD (Pins J6, J9): Analog 1.8V Supply for ADC. The
specified operating range is 1.74V to 1.9V. VDD is internally
bypassed to GND.
GAIN_I (Pin C12): I Channel Gain Control Input. This is
an input that controls the gain of the amplifier. This pin is
internally pulled low with 10kΩ to GND. The gain control
slope is approximately 32dB/V with a gain control range
of 0.1V to 1.1V.
GAIN_Q (Pin C1): Q Channel Gain Control Input. This is
an input that controls the gain of the amplifier. This pin is
internally pulled low with 10kΩ to GND. The gain control
slope is approximately 32dB/V with a gain control range
of 0.1V to 1.1V.
CLK+, CLK– (Pins J5, K5): ADC Clock Input. Conversion
starts on the rising edge of CLK+.
OVDD (Pins N5, N10): Positive 1.8V Supply for the Digital
Output Drivers. The specified operating range is 1.74V to
1.9V. OVDD is internally bypassed to GND.
IP2_I (Pin C10): IP2 Adjustment Pin for I Channel.
GND: Analog Ground. See Pin Configuration table for pin
locations.
REF (Pin D8): Voltage Reference Input for Analog Control
Voltage Pins.
Analog Inputs
RF (Pin A10): RF Input Pin. This is a single-ended 50Ω
terminated input. No external matching network is required
for the 1.5GHz to 2.7GHz band. An external series inductor
(and/or shunt capacitor) may be required for impedance
transformation to 50Ω in the band from 700MHz to 1.5GHz,
or for the band from 2.7GHz to 4GHz (see Figure 2). If the
RF source is not DC blocked, a series blocking capacitor
should be used. Otherwise, damage to the IC may result.
LO+, LO– (Pins A6, A5): Local Oscillator Input Pins. This is a
differential 50Ω terminated input. An external series inductor (and/or shunt capacitor) may be required for impedance
transformation to 50Ω in the band from 700MHz to 1.5GHz,
or for the band from 2.7GHz to 4GHz (see Figure 4). If the
LO source is not DC blocked, a series blocking capacitor
must be used. Otherwise, damage to the IC may result.
+IN_I, –IN_I (Pins E10, E11): Channel I Signal Input. This
is a differential input that drives the amplifier. It has an
internally generated DC bias. Series blocking capacitors
are required between these pins and +OUT_I, –OUT_I.
+IN_Q, –IN_Q (Pins E4, E5): Channel Q Signal Input. This
is a differential input that drives the Amplifier. It has an
internally generated DC bias. Series blocking capacitors
are required between these pins and +OUT_Q, –OUT_Q.
IP2_Q (Pin D10): IP2 Adjustment Pin for Q Channel.
SENSE (Pin J8): ADC Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and
a 1.32V input range.
Analog Outputs
+OUT_I, –OUT_I (Pins F10, F11): Channel I Signal Output.
This is a differential output from the demodulator. The DC
bias point is VCC1 – 1.5V for each pin. These pins must
have an external 100Ω or inductor pull-up to VCC1. Series
blocking capacitors are required between these pins and
+IN_I, –IN_I.
+OUT_Q, –OUT_Q (Pins F4, F5): Channel Q Signal Output.
This is a differential output from the demodulator. The DC
bias point is VCC1 – 1.5V for each pin. These pins must
have an external 100Ω or inductor pull-up to VCC1. Series
blocking capacitors are required between these pins and
+IN_Q, –IN_Q.
Control Pins
EN (Pin B8): Demodulator Enable Pin. If EN = high (the
input voltage is higher than 2.0V), the demodulator is enabled. If EN = low (the input voltage is less than 1.0V), it
is disabled. If the enable function is not needed, then this
pin should be tied to VCC1.
EIP2 (Pin D6): Demodulator IP2 Adjust Enable Pin. Pin is
internally pulled low with 200kΩ to GND. If EIP2 = high
9013f
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9
LTM9013
PIN FUNCTIONS
(the input voltage is higher than 2.0V), the IP2 adjust
circuit is enabled. If EIP2 = low (the input voltage is less
than 1.0V), it is disabled.
NC1, NC2, NC3 (Pins C6, C9, D9): Do Not Connect.
EN_I (Pin C14): First Amplifier I Channel Enable Pin. Pin
is internally pulled high with 100kΩ to VCC2. Assert pin to
a low voltage to enable the amplifier. Connect pin to GND
if enable function is not used.
EN_Q (Pin C3): First Amplifier Q Channel Enable Pin. Pin
is internally pulled high with 100kΩ to VCC2. Assert pin to
a low voltage to enable the amplifier. Connect pin to GND
if enable function is not used.
SHDN_I (Pin D14): Amplifier I Channel Shutdown Pin.
Pin is internally pulled high with 100kΩ to VCC2. Assert
pin to a low voltage to shut down the amplifier. Proper
sequencing of the EN_I and SHDN_I pins is required to
avoid non-monotonic output signal behavior. Connect pin
to VCC2 if shutdown function is not used.
SHDN_Q (Pin D3): Amplifier Q Channel Shutdown Pin.
Pin is internally pulled high with 100kΩ to VCC2. Assert
pin to a low voltage to shut down the amplifier. Proper
sequencing of the EN_Q and SHDN_Q pins is required to
avoid non-monotonic output signal behavior. Connect pin
to VCC2 if shutdown function is not used.
SDI (Pin K11): Serial Interface Data Input. In serial programming mode, (PAR/SER = GND), SDI is the serial
interface data input. Data on SDI is clocked into the mode
control registers on the rising edge of SCK. In the parallel
programming mode (PAR/SER = VDD), SDI selects 3.5mA
or a 7.5mA LVDS output current (see Table 4). SDI can be
driven with 1.8V to 3.3V logic.
SCK (Pin J11): Serial Interface Clock Input. In serial
programming mode (PAR/SER = GND), SCK is the serial
interface clock input. In the parallel programming mode
(PAR/SER = VDD), SCK can be used to place the part in the
low power sleep mode (see Table 4). SCK can be driven
with 1.8V to 3.3V logic.
CS (Pin K10): Serial Interface Chip Select Input. In serial
programming mode (PAR/SER = GND), CS is the serial
interface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
In the parallel programming mode (PAR/SER = VDD), CS
10
controls the clock duty stabilizer (see Table 4). CS can be
driven with 1.8V to 3.3V logic.
PAR/SER (Pin J10): Programming Mode Selection Pin.
Connect to GND to enable the serial programming mode
where CS, SCK, SDI, SDO become a serial interface that
controls the ADC operating modes. Connect to VDD to enable
the parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the ADC operating modes. PAR/SER should be connected
directly to GND or VDD and not be driven by a logic signal.
Digital Outputs
SDO (Pin L11): Serial Interface Data Output. In serial programming mode (PAR/SER = GND), SDO is the optional
serial inter-face data output. Data on SDO is read back from
the mode control registers and can be latched on the falling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2kΩ pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
LVDS Digital Outputs
The following pins are differential LVDS outputs. The output
current level is programmable. There is an optional internal
100Ω termination resistor between the pins of each LVDS
output pair.
CLKOUT+, CLKOUT– (Pins P8, P7): ADC Data Output Clock.
DB0_1–/DB0_1+ to DB12_13–/DB12_13+ (See Pin Configuration table for pin locations): Q Channel ADC Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DB0,
DB2, DB4, DB6, DB8, DB10, DB12) appear when CLKOUT+
is low. The odd data bits (DB1, DB3, DB5, DB7, DB9, DB11,
DB13) appear when CLKOUT+ is high.
DA0_1–/DA0_1+ to DA12_13–/DA12_13+ (See Pin Configuration table for pin locations): Q Channel ADC Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DA0,
DA2, DA4, DA6, DA8, DA10, DA12) appear when CLKOUT+
is low. The odd data bits (DA1, DA3, DA5, DA7, DA9, DA11,
DA13) appear when CLKOUT+ is high.
OF+, OF– (Pins K2, K1): Overflow/Underflow Outputs. OF+
is high when an overflow/underflow has occurred. 9013f
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LTM9013
PIN FUNCTIONS
Pin Configuration
1
2
3
4
5
6
7
8
LO+
9
10
11
12
13
14
GND
A
GND
VCC2
VCC2
GND
LO–
GND
GND
GND
RF
GND
VCC2
VCC2
B
GND
GND
GND
GND
GND
GND
VCC1
EN
GND
GND
GND
GND
GND
GND
C
GAIN_Q
GND
EN_Q
GND
GND
NC1
GND
GND
NC2
IP2_I
GND
GAIN_I
GND
EN_I
D
VCC2
GND
SHDN_Q
GND
GND
EIP2
GND
REF
NC3
IP2_Q
GND
VCC2
GND
SHDN_I
E
GND
GND
GND
+IN_Q
–IN_Q
GND
GND
GND
GND
+IN_I
–IN_I
GND
GND
GND
F
GND
GND
GND
+OUT_Q
–OUT_Q
GND
GND
GND
GND
+OUT_I
–OUT_I
GND
GND
GND
G
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J
GND
GND
GND
GND
CLK+
VDD
GND
SENSE
VDD
PAR/SER
SCK
GND
GND
GND
K
OF–
OF+
GND
GND
CLK–
GND
GND
GND
GND
CS
SDI
GND
GND
GND
L
DB01–
DB01+
GND
GND
GND
GND
GND
GND
GND
GND
SDO
GND
DA1213– DA1213+
M
DB23–
DB23+
DB45–
DB45+
GND
GND
GND
GND
GND
GND
DA89–
DA89+
DA1011– DA1011+
N
DB67–
DB67+
DB89–
DB89+
GND
OVDD
DA45–
DA45+
DA67–
DA67+
P
GND
GND
DA23+
DA23–
DA01+
DA01–
GND
OVDD
GND
DB1213+ DB1213– DB1011+ DB1011–
GND
GND
GND
CLKOUT– CLKOUT+
Top View of BGA Package (Looking Through Component)
OVDD
VDD
VCC2
IN_I+
IN_I–
OUT_I+
OUT_I–
VCC1
BLOCK DIAGRAM
DA12_13
•
•
•
RF
DA0_1
CLKOUT+
CLKOUT–
OF+
0°
IP2
CONTROL
90°
ADC
CONTROL
RANGE
SELECT
OF–
CLOCK DUTY
CYCLE CONTROL
DB12_13
•
•
•
DB0_1
GND
CLK
–
CLK+
SENSE
SDI
SD0
CS
SCK
PAR/SER
EN_I
SHDN_I
SHDN_Q
EN_Q
GAIN_I
GAIN_Q
IN_Q+
IN_Q–
IP2_I
IP2_Q
REF
EIP2
OUT_Q–
OUT_Q+
EN
LO–
LO+
9013 F01
Figure 1. Functional Block Diagram
9013f
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11
LTM9013
TIMING DIAGRAMS
Double-Data Rate Output Timing, All Data Are Differential LVDS
N
tAP
N+3
N+2
N+1
tL
tH
CLK–
CLK+
CLKOUT+
CLKOUT –
DA0_1–
DA0_1+
DA12_13–
DA12_13+
DB0_1–
DB0_1+
tC
DA0N-5
DA1N-5
DA0N-4
DA1N-4
DA0N-3
DA1N-3
tD
DA12N-5 DA13N-5 DA12N-4 DA13N-4 DA12N-3 DA13N-3
DB0N-5
DB1N-5
DB0N-4
DB1N-4
DB0N-3
DB1N-3
DB12_13–
DB12_13+
DB12N-5 DB13N-5 DB12N-4 DB13N-4 DB12N-3 DB13N-3
OF–
OF+
OF_A N-5 OF_B N-5 OF_A N-4 OF_B N-4 OF_A N-3 OF_B N-3
tSKEW
9013 TD01
9013f
12
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LTM9013
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
9013 TD02
HIGH IMPEDANCE
9013f
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13
LTM9013
OPERATION
Description
The LTM9013 is a low IF receiver targeting digital predistortion receiver applications, such as wireless infrastructure
with RF input frequencies up to 4GHz. It is an integrated
μModule receiver utilizing system in a package (SiP) technology to combine a dual, high speed 14-bit A/D converter,
300MHz lowpass filters, one low noise, differential amplifier
per channel with adjustable gain and an I/Q demodulator
with IP2 adjustment.
The following sections describe in further detail the operation of each section.
Demodulator Operation
The RF signal is applied to the inputs of the RF transconductance amplifiers and is then demodulated into I/Q
baseband signals using quadrature LO signals which are
internally generated from an external LO source by precision 90° phase shifters.
Broadband transformers are integrated at the RF input to
enable a single-ended RF interface. In the mid frequency
band (1.5GHz to 2.7GHz), both RF and LO ports are internally matched to 50Ω. No external matching components
are needed. For the low (700MHz to 1.5GHz), and high
(2.7GHz to 4GHz) frequency bands a simple network with
series inductors and/or shunt capacitors can be used as
the impedance matching network.
Amplifier Operation
Each channel of the LTM9013 consists of a single stage of
AC-coupled, low noise and low distortion fully differential op
amp/ADC driver. Each stage is followed by a 4-pole lowpass
filter using a high speed, high performance operational
amplifier and precision passive components. The stage
is designed to provide maximum gain and phase flatness.
The LTM9013 variable gain amplifier employs an interpolated, tapped attenuator circuit architecture to generate
the variable-gain characteristic. The tapped attenuator
is fed to a buffer and output amplifier to complete the
differential signal path. This circuit architecture provides
good RF input power handling capability along with a
constant output noise and output IP3 characteristic that
are desirable for most IF signal chain applications. The
internal control circuitry takes the gain control signal from
the GAIN terminals and converts this to an appropriate set
of control signals to the attenuator ladder. The attenuator
control circuit ensures that the linear-in-dB gain response
is continuous and monotonic over the gain range for both
slow and fast moving input control signals while exhibiting very little input impedance variation over gain. These
design considerations result in a gain-vs-VG characteristic
with a ±0.1dB ripple and a 0.5µs gain response time that
is slower than a similar digital step attenuator design.
An often overlooked characteristic of an analog-controlled
VGA is upconverted amplitude modulation (AM) noise
from the gain control terminals. The VGA behaves as a
2-quadrant multiplier, so some minimal care is required
to avoid excessive AM sideband noise generation. The
following table demonstrates the effect of the baseline
20nV/√Hz equivalent input control noise from the LTM9013
circuit along with the effect of a higher combined input
noise due to a noisy external control circuit.
CONTROL INPUT TOTAL NOISE
VOLTAGE (nV/√Hz)
PEAK AM NOISE AT 10kHz OFFSET
NEAR MAXIMUM GAIN (dBc/Hz)
20
–142
40
–136
70
–131
100
–128
200
–122
9013f
14
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LTM9013
OPERATION
The baseline equivalent 20nV/√Hz input noise is seen to
produce worst-case AM sidebands of –142dBc/Hz which is
near the –147dBm/Hz output noise floor at maximum gain
for a nominal 0dBm output signal. An input control noise
voltage less than 80nV/√Hz is generally recommended to
avoid measurable AM sideband noise. While op amp control
circuit output noise voltage is usually below 80nV/√Hz,
some low power DAC outputs exceed 150nV/√Hz. DACs
with output noise in the range of 100nV/√Hz to 150nV/√Hz
can usually be accommodated with a suitable 2:1 or 3:1
resistor divider network on the DAC output to suppress the
noise amplitude by the same ratio. Noisy DACs in excess
of 150nV/√Hz should be avoided if minimal AM noise is
important in the application.
ADC Input Network
The passive network between the amplifier output and
the ADC input stages provides a 0.1dB ripple, 4th order
Chebyshev lowpass filter response.
Converter Operation
The LTM9013 includes a 2-channel, 14-bit 310Msps A/D
converter powered by a single 1.8V supply. The converter
has five pipelined ADC stages; a sampled input will result
in a digitized value five cycles later. The analog inputs
are driven differentially by the VGA. The encode inputs
should be driven differentially for optimal performance.
The digital outputs are double data rate LVDS. Additional
features can be chosen by programming the mode control
registers through a serial SPI port.
9013f
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15
LTM9013
APPLICATIONS INFORMATION
RF Input
0
–5
RETURN LOSS (dB)
Figure 2 shows the mixer’s RF input which consists of an
integrated transformer and high linearity transconductance amplifiers. The primary side of the transformer is
connected to the RF input pin. The secondary side of the
transformer is connected to the differential inputs of the
transconductance amplifiers. Under no circumstances
should an external DC voltage be applied to the RF input
pin. DC current flowing into the primary side of the transformer may cause damage to the integrated transformer.
A series blocking capacitor should be used to AC-couple
the RF input port to the RF signal source.
–10
–15
–20
–25
NO MATCHING
ELEMENTS
1.95GHz MATCH
(3.3nH + 1.5pF)
–30
100
1000
FREQUENCY (MHz)
10000
9013 F03
Figure 3. RF Input Return Loss with External Matching
RF
INPUT
EXTERNAL
MATCHING
NETWORK FOR
LOW BAND AND
MID BAND
C19
LTM9013
TO I-MIXER
L5
C20
Table 1. RF Input Impedance
RF
C21
TO Q-MIXER
9013 F02
Figure 2. RF Input Interface
The RF input port is internally matched over a wide frequency range from 1.5GHz to 2.7GHz with input return
loss typically better than 10dB. No external matching
network is needed for this frequency range. When the
part is operated at lower frequencies, however, the input
return loss can be improved with the matching network
shown in Figure 2. Shunt capacitors C20, C21 and series
inductor L5 can be selected for optimum input impedance
matching at the desired frequency as illustrated in Figure 3.
C19 serves as a series DC blocking capacitor.
The RF input impedance and S11 parameters (without
external matching components) are listed in Table 1.
FREQUENCY MAGNITUDE
500MHz
0.96
600MHz
0.93
700MHz
0.90
800MHz
0.81
900MHz
0.70
1000MHz
0.74
1100MHz
0.78
1200MHz
0.82
1300MHz
0.81
1400MHz
0.83
1500MHz
0.83
1600MHz
0.83
1700MHz
0.84
1800MHz
0.83
1900MHz
0.84
2000MHz
0.81
2100MHz
0.81
2200MHz
0.78
2300MHz
0.75
2400MHz
0.73
2500MHz
0.68
2600MHz
0.66
2700MHz
0.63
2800MHz
0.62
2900MHz
0.61
3000MHz
0.59
PHASE
41.2
50.6
61.3
71.3
90.7
109.6
122.1
130.2
136.9
143.6
149.0
157.2
165.3
175.9
–173.1
–161.6
–150.2
–141.5
–132.7
–129.9
–126.8
–128.6
–129.1
–126.9
–124.9
–117.7
R
92.3Ω
85.3Ω
76.0Ω
66.9Ω
49.4Ω
34.8Ω
25.9Ω
20.4Ω
16.8Ω
13.2Ω
11.0Ω
7.9Ω
5.8Ω
4.7Ω
4.8Ω
7.3Ω
10.9Ω
15.2Ω
20.2Ω
22.2Ω
24.9Ω
24.3Ω
24.8Ω
26.0Ω
27.2Ω
31.5Ω
X
–95.4Ω
–62.0Ω
–36.0Ω
–17.6Ω
0.4Ω
8.5Ω
11.2Ω
12.1Ω
11.6Ω
10.9Ω
9.7Ω
7.7Ω
5.2Ω
1.5Ω
–2.5Ω
–6.2Ω
–9.2Ω
–10.5Ω
–10.9Ω
–10.6Ω
–9.7Ω
–9.4Ω
–8.8Ω
–8.6Ω
–8.5Ω
–7.6Ω
9013f
16
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LTM9013
APPLICATIONS INFORMATION
LO Input Port
0
LO
INPUT C22
T1
–5
RETURN LOSS (dB)
The mixer’s LO input interface is shown in Figure 4. The
input consists of a precision quadrature phase shifter
which generates 0° and 90° phase-shifted LO signals for
the LO buffer amplifiers driving the I/Q mixers. Under no
circumstances should an external DC voltage be applied
to the input pin. DC current flowing into the primary side
of the transformer may damage the transformer.
–10
–15
–20
–25
NO MATCHING
ELEMENTS
1.8GHz MATCH
(0.5pF + 6.8nH)
–30
100
LTM9013
LO–
C24
LO+
LO QUADRATURE
GENERATOR AND
BUFFER AMPLIFIERS
1000
FREQUENCY (MHz)
10000
9013 F05
Figure 5. LO Input Return Loss with External Matching
Table 2. LO Input Impedance
9013 F04
Figure 4. LO Input Interface
The LO input port is internally matched over a wide frequency range from 1.5GHz to 2.7GHz with input return
loss typically better than 10dB. No external matching
network is needed for this frequency range. The LO input
impedance and S11 parameters (without external matching
components) are listed in Table 2. Outside this frequency
range, the impedance match can be improved using series
capacitor C22 and shunt capacitor C24.
FREQUENCY MAGNITUDE
500MHz
0.71
600MHz
0.66
700MHz
0.66
800MHz
0.62
900MHz
0.55
1000MHz
0.51
1100MHz
0.48
1200MHz
0.52
1300MHz
0.57
1400MHz
0.62
1500MHz
0.66
1600MHz
0.67
1700MHz
0.69
1800MHz
0.67
1900MHz
0.66
2000MHz
0.61
2100MHz
0.55
2200MHz
0.46
2300MHz
0.34
2400MHz
0.30
2500MHz
0.33
2600MHz
0.42
2700MHz
0.51
2800MHz
0.53
2900MHz
0.52
3000MHz
0.33
PHASE
–70.3
–83.9
–97.1
–119.8
–144.9
–177.8
146.5
115.0
87.9
70.5
55.0
44.0
34.1
24.3
15.5
2.5
–10.2
–34.3
–63.8
–113.3
–164.3
164.8
140.5
120.3
101.7
98.1
R
67.7Ω
55.0Ω
44.5Ω
29.8Ω
20.2Ω
16.1Ω
22.2Ω
34.3Ω
51.6Ω
66.9Ω
84.7Ω
101.4Ω
123.7Ω
154.8Ω
193.5Ω
206.9Ω
163.1Ω
101.7Ω
65.5Ω
40.0Ω
25.8Ω
21.4Ω
23.1Ω
31.4Ω
42.2Ω
45.9Ω
X
15.5Ω
3.6Ω
–3.3Ω
–8.3Ω
–6.5Ω
–0.4Ω
5.3Ω
6.1Ω
–0.9Ω
–12.4Ω
–30.5Ω
–46.6Ω
–67.4Ω
–75.6Ω
–70.8Ω
–10.8Ω
24.2Ω
21.3Ω
5.5Ω
–2.5Ω
–1.6Ω
2.2Ω
6.3Ω
6.7Ω
3.6Ω
1.3Ω
9013f
For more information www.linear.com/LTM9013
17
LTM9013
APPLICATIONS INFORMATION
IM2 Adjustment Circuitry
IF Input Port Characteristics
The LTM9013 also contains circuitry for the independent
adjustment of IM2 levels on the I and Q channels. When
the EIP2 pin is a logic high, this circuitry is enabled and
the IP2I and IP2Q analog control voltage inputs are able
to adjust the IM2 level. The IM2 level can be effectively
minimized over a large range of the baseband bandwidth.
The circuitry has an effective baseband frequency upper
limit of about 200MHz. Any IM2 component that falls in
this frequency range can be minimized.
The amplifier inputs provide a nominal 50Ω differential
input impedance over the operating frequency range.
Variable Gain Amplifier
The LTM9013 includes a high linearity, fully-differential
analog-controlled variable-gain amplifier (VGA) optimized for application frequencies in the range of 1MHz to
500MHz. The VGA architecture provides a constant OIP3
and constant output noise level (NF + Gain) over the 31dB
gain-control range and thus exhibits a uniform spuriousfree dynamic range (SFDR) over gain. This constant SFDR
characteristic is ideal for use in receiver IF chains.
Gain Characteristics
The LTM9013 provides a continuously adjustable gain of
31dB that is linear-in-dB with respect to the control voltages applied to GAIN_I and GAIN_Q. In this way, a positive
gain-control slope is easily achieved:
Apply gain control voltage to the GAIN_I/GAIN_Q pins.
Gain increases with increasing GAIN_I/GAIN_Q voltage.
When connected in this typical single-ended configuration,
the active control input range extends from 0.1V to 1.1V.
This control input range can be extended using a resistor
divider with a suitably low output resistance. For example,
two series resistors of 1k each would extend the control
input range from 0.2V to 2.2V while providing an effective
500Ω Thevinin equivalent source resistance, a relatively
small loading effect compared to the 10k input resistance
of the GAIN_I/GAIN_Q terminals.
The input impedance characteristic derives from the differential attenuator ladder. The internal circuit controls the
IF connections to this attenuator ladder and generates the
appropriate common mode DC voltage.
Enable/Shutdown
Both the EN and SHDN pins are self-biased to VCC2 through
their respective 100k pull-up resistors, so the default
open-pin state is powered on with the output amplifier
signal path disabled. Pulling the EN pin low completes the
signal path from the attenuator ladder through the output
amplifier. The EN pin essentially provides a fast muting
function while the SHDN pin provides slower power on/
off function.
For applications requiring the SHDN function, it is recommended that the output amplifier signal path be disabled
with a high EN voltage before transitioning the SHDN
signal. When enabling the amplifier, allow at least 5ms
dwell time between the rising SHDN transition and the
falling EN transition to avoid non-monotonic output signal
behavior though the VGA. The opposite delay sequence
is recommended for the falling SHDN transition, but this
is less critical as the output signal amplitude will drop
abruptly regardless of the EN pin.
SHDN
tDWELL
tDWELL
9013 F06
EN
Figure 6
9013f
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LTM9013
APPLICATIONS INFORMATION
ESD
Encode Input
The amplifier inputs are protected with reverse-biased
ESD diodes on all pins. If any pin is forced one diode drop
above the positive supply or one diode drop below the
negative supply, then large currents may flow through the
diodes. No damage to the devices will occur if the current
is kept below 10mA.
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
Reference
The LTM9013 has an internal 1.25V voltage reference for
the ADC. For a 1.32V input range with internal reference,
connect SENSE to VDD. For a 1.32V input range with an
external reference, apply a 1.25V reference voltage to
SENSE (Figure 7). Apply a 1.15V reference voltage to
SENSE to achieve specified performance.
5Ω
VREF
0.1µF
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
the encode inputs directly. Otherwise a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD + 0.1V or go below –0.1V.
LTM9013
1.25V
SCALER/
BUFFER
SENSE
ADC
REFERENCE
SENSE
DETECTOR
9013 F07
Figure 7. Reference Circuit
LTM9013
VDD
1.2V
CLK+
10k
CLK–
9013 F08
Figure 8. Equivalent Encode Input Circuit
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LTM9013
APPLICATIONS INFORMATION
LTM9013
VDD
1.2V
0.1µF
10k
50Ω
100Ω
0.1µF
50Ω
T1: MACOM
ETC1-1-13
9013 F09
Figure 9. Sinusoidal Encode Circuit
LTM9013
DIGITAL OUTPUTS
VDD
The digital outputs are double data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are seven LVDS output pairs for channel A (DA0_1+/DA0_1– through DA12_13–/DA12_13+)
and seven pairs for channel B (DB0_1+/DB0_1– through
DB12_13–/DB12_13+). Overflow (OF+/OF –) and the data
output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that overflow for both channels is multiplexed onto the OF+/OF – output pair.
1.2V
0.1µF
PECL OR
LVDS INPUT
CLK+
10k
100Ω
0.1µF
CLK–
9013 F10
Figure 10. PECL or LVDS Encode Drive
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 5) or
by CS in parallel programming mode.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 5). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this cases care should be taken to make the clock a 50%
(± 5%) duty cycle.
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APPLICATIONS INFORMATION
Optional LVDS Driver Internal Termination
Phase Shifting the Output Clock
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
To allow adequate set-up and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
The OF output is double data rate; when CLKOUT+ is low,
channel A’s overflow is available; when CLKOUT+ is high,
channel B’s overflow is available.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combination of these two features enables phase shifts of 45° up
to 315° (Figure 11).
CLK+
D0-D13, OF
CLKOUT+
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1
CLKPHASE0
0°
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
9013 F11
Figure 11. Phase Shifting CLKOUT
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LTM9013
APPLICATIONS INFORMATION
DATA FORMAT
Table 3 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
CLKOUT
OF
OF
D13
Table 3. Output Codes vs Input Level
D13/D0
D12
+IN – –IN
OF
D13-D0
(OFFSET BINARY)
+Overflow
1
11 1111 1111 1111
01 1111 1111 1111
+Full Scale
0
11 1111 1111 1111
01 1111 1111 1111
D13-D0
(2’s COMPLEMENT)
0
11 1111 1111 1110
01 1111 1111 1110
0
10 0000 0000 0001
00 0000 0000 0001
0
10 0000 0000 0000
00 0000 0000 0000
0
01 1111 1111 1111
11 1111 1111 1111
0
01 1111 1111 1110
11 1111 1111 1110
–Full Scale
0
00 0000 0000 0001
10 0000 0000 0001
–Overflow
0
00 0000 0000 0000
10 0000 0000 0000
1
00 0000 0000 0000
10 0000 0000 0000
Mid-Scale
CLKOUT
D12/D0
•
•
•
RANDOMIZER
ON
D1
D1/D0
D0
D0
9013 F12
Figure 12. Functional Equivalent of Digital Output Randomizer
PC BOARD
CLKOUT FPGA
OF
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive‑OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled
by serially programming mode control register A4.
D13/D0
LTM9013
D13
D12/D0
D1/D0
D0
•
•
•
D12
D1
D0
9013 F13
Figure 13. Decoding a Randomized Digital Output Signal
9013f
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LTM9013
APPLICATIONS INFORMATION
Alternate Bit Polarity
Output Disable
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11, D13) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output randomizer—either both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
The A/D may be placed in sleep mode to conserve power.
In sleep mode the entire A/D converter is powered down,
resulting in <5mW power consumption. If the encode
input signal is not disabled the power consumption will be
higher (up to 5mW at 250Msps). Sleep mode is enabled
by mode control register A1 (serial programming mode),
or by SCK (parallel programming mode).
Digital Output Test Patterns
In the serial programming mode it is also possible to disable channel B while leaving channel A in normal operation.
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13 to D0) to known values:
Sleep Mode
All 0s: All outputs are 0
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitor on VREF . With
the 2.2µF value used internally, the A/D will stabilize after
0.1ms + 2500 • tp where tp is the period of the sampling
clock.
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Nap Mode
All 1s: All outputs are 1
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wakeup.
Recovering from nap mode requires at least 100 clock
cycles. Nap mode is enabled by power-down register A1
in the serial programming mode.
Wake-up time from nap mode is guaranteed only if the
clock is kept running, otherwise Power-Down Wake-up
conditions apply.
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LTM9013
APPLICATIONS INFORMATION
DEVICE PROGRAMMING MODES
The operating modes of the A/D can be programmed by
either a parallel interface or a simple serial interface. The
serial interface has more flexibility and can program all
available modes. The parallel interface is more limited and
can only program some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
CMOS logic. Table 4 shows the modes set by CS, SCK
and SDI.
Table 4. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 5 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is necessary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is write-only.
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APPLICATIONS INFORMATION
Table 5. Serial Programming Mode Register Map (PAR/SER = GND). X Indicates Unused Bit
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
RESET
Bit 7
Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused Bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
SLEEP
NAP
PDB
0
Bits 7-4
Unused, this bit read back as 0
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
PDB
Bit 1
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0
Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, This Bit Read Back as 0
Bit 3
CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
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LTM9013
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
X
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
Bits 7-5
Unused, This Bit Read Back as 0
Bits 4-2
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1
TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
Bit 0
OUTOFF Digital Output Mode Control Bits
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled (High Impedance)
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
OUTTEST2
Bits 7-5
D6
D5
D4
D3
D2
D1
D0
OUTTEST1
OUTTEST0
ABP
0
DTESTON
RAND
TWOSCOMP
OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111
100 = Checkerboard Output Pattern. OF, D13-D0 alternate between 101 0101 0101 0101 and 010 1010 1010 1010
Note 1: Other bit combinations are not used.
Note 2: Patterns from channel A and channel B may not be synchronous.
Bit 4
ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3
Must Be Set to 0
Bit 2
Enable the digital output test patterns (set by Bits 7-5)
DTESTON
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Bit 1
RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
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LTM9013
APPLICATIONS INFORMATION
Design Examples
0
The LTM9013 allows the user to tailor the highpass corner
frequency to suit the application. The 0.5dB lowpass corner
is set by the internal network at 300MHz. By cascading
the external highpass and internal lowpass networks a
bandpass characteristic is realized. An example of a very
low frequency highpass corner is shown in Figure 14.
AMPLITUDE (dB)
–1
The typical performance for the overall module is shown
below:
–2
–3
–4
–5
–6
IF passband (1.5dB): 1MHz to 300MHz
0
50 100 150 200 250 300 350 400 450 500
BASEBAND FREQUENCY (MHz)
RF input for –1dBFS: –5dBm at maximum gain
9013 F15
Figure 15. Baseband Frequency Response
SNR at –1dBFS: 59.1dB
HD2 at –1dBFS: 74dBc
IMD3 at –7dBFS per tone: –72dBc
The frequency response is shown in Figure 15:
100Ω
5V
VCC1
5V
100Ω
LTM9013
15nH
0.01µF
6.8pF
15nH
0.01µF
VDD
1.8V
VCC2
3.3V
GAIN_Q GAIN_I
OVDD
1.8V
ADC
CLKOUT
0°
LNA
90°
ADC CLK
OF
ADC
GND
SCK CS
SDI SDO
GND
PAR/SER
9013 F14
LO IN
100Ω
5V
100Ω
15nH
0.01µF
6.8pF
15nH
0.01µF
Figure 14. Highpass Filter Set for 1MHz
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LTM9013
APPLICATIONS INFORMATION
For those applications that require a higher frequency
corner at the highpass point, the network can be tailored,
for example, as shown in Figure 16.
0
–0.5
AMPLITUDE (dB)
The typical performance for the overall module is shown
below:
–1.0
–1.5
IF passband (1.0dB): 55MHz to 315MHz
–2.0
RF input for –1dBFS: –5dBm at maximum gain
–2.5
SNR at –1dBFS: 59.1dB
–3.0
HD2 at –1dBFS: 74dBc
IMD3 at –7dBFS per tone: –72dBc
0
50 100 150 200 250 300 350 400 450 500
BASEBAND FREQUENCY (MHz)
9013 F17
Figure 17. Baseband Frequency Response
The frequency response is shown in Figure 17:
56pF
100Ω
5V
VCC1
5V
100Ω
LTM9013
0.01µF
180nH
56pF
150nH
0.01µF
VDD
1.8V
VCC2
3.3V
GAIN_Q GAIN_I
OVDD
1.8V
ADC
CLKOUT
0°
LNA
90°
ADC CLK
OF
ADC
GND
SCK CS
SDI SDO
GND
PAR/SER
9013 F16
LO IN
100Ω
5V
100Ω
56pF
0.01µF
180nH
56pF
150nH
0.01µF
Figure 16. Highpass Filter Set for 55MHz
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LTM9013
APPLICATIONS INFORMATION
Supply Sequencing
Recommended Layout
The VCC1 pins supply voltage to the demodulator. The
VCC2 pins supply voltage to the amplifiers. The amplifier
output stages are also fed by the VCC1 pins, so careful
power supply sequencing is important. Power must be
applied to the VCC2 pins before power is applied to the
VCC1 pins to avoid damage to the amplifiers. Note also that
the amplifiers must be enabled before voltage is applied
to the VCC1 pins for the same reason.
The high integration of the LTM9013 makes the PCB
board layout simple. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
Grounding and Bypassing
The LTM9013 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9013 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. A continuous row of ground pads facilitate a
layout that ensures that digital and analog signal lines are
separated as much as possible.
The LTM9013 is internally bypassed with the ADC (VDD),
mixer, amplifier (VCC) digital (OVDD) supplies returning to
a common ground (GND). Additional bypass capacitance
is optional and may be required if power supply noise is
significant.
Heat Transfer
Most of the heat generated by the LTM9013 is transferred
through the bottom-side ground pins. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
• Use large PCB copper areas for ground. This helps to
dissipate heat in the package through the board and
also helps to shield sensitive on-board analog signals.
• Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the
board and creates necessary barriers separating analog
and digital traces on the board at high frequencies.
• Separate analog and digital traces as much as possible,
using vias to create high frequency barriers. This will
reduce digital feedback that can reduce the signal-tonoise ratio (SNR) and dynamic range of the LTM9013.
Figures 18 through 25 give a good example of the recommended layout.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
use a type 3 or 4 printing no-clean solder paste. The solder
stencil design should follow the guidelines outlined in PCB
Assembly and Manufacturing Guidelines
BGA Packages: Assembly Considerations for Linear Technology µModule BGA Packages.
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CLK_IN
J3
LO_IN
Matched for 1.8GHz
R34
1K
RF_IN
2.2uF
C18
R32
1K
2.2uF
Matched for 1.95GHz
E6
DEMOD REF
VDD
C17
VDD
J2
49.9
R26
C25
0.01uF
C26
0.01uF
R20
0
4
5
T2
MABA007159
C24
0.5pF
C20
1.5pF
L5
3.3nH
3
1
R38
DNI
R36
DNI
BD0826J50200A00
3
5
4
2
T1
R33
178
1.00K
R31
R30
1.74K
6
1
C21
DNI
GAIN ADJUST (Q CH)
R28
178
VCC2
1.00K
R25
R23
1.74K
VCC2
1.00K
R15
R12
3.83K
VCC1
GAIN ADJUST (I CH)
C22
6.8nH
100pF
C19
R29
1.58K
R24
1K
J1
VDD
R11
0
IP2 ADJUST (Q CH)
IP2 ADJUST (I CH)
1.00K
0
R39
0
R35
C27
DNI
AMP RUN
AMP SHUTDOWN
I/Q DISABLE
I/Q ENABLE
C23
0.01uF
IP2 ADJUST DISABLE
IP2 ADJUST ENABLE
R9
10K
2
R10
1K
6
1
R37
49.9
~AMP_SHDN
4
3
U1
Si1563DH
A1
A2
A5
A6
A7
A8
A9
A14
B2
B3
B4
B5
B6
B7
B8
B9
C2
C5
C6
C7
C8
C9
C10
C11
D1
E9
E10
E1
F1
K1
H4
H9
A3
M3
F4
K3
K4
H2
P3
C3
P4
C4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CLK+
CLK-
LOLO+
RF
REF
SENSE
GAIN_Q
GAIN_I
EIP2
IP2_I
IP2_Q
EN
EN#_I
EN#_Q
SHDN#_I
SHDN#_Q
U2
LTM9013
5
R8
100
R22
100
R14
100
C11
0.01uF
L2
15nH
C2
DNI
VCC1_load
C5
0.01uF
VCC1_load
L4
15nH
C8
DNI
L3
15nH
C3
DNI
C9
DNI
0.01uF
C6
C4
6.8pF
0.01uF
C16
C10
6.8pF
0.01uF
C7
Figure 18. Schematic for Recommended Layout
2
JP7
R27
1K
VCC1
2
JP6
R21
1K
VCC1
2
JP5
R13
1K
VCC2
3
1
E1
AMP_MUTE (HI)
D6
R7
E6
+OUT_Q
R6
3.83K
K6
-OUT_Q
3
1
R5
100
F3
J3
J4
NC
NC
NC
VCC2
L5
-IN_I
VCC2
K5
+IN_I
VCC1
L6
-OUT_I
+OUT_I
0.01uF
E5
-IN_Q
2
JP1
VDD
3
C1
2
JP2
0.1uF
C12
VCC1_load
R16
0.1
VCC1
SERIAL
PARALLEL
R1
1K
VDD
E2
0.1uF
C13
E3
R17
0.1
VCC2
0.1uF
C14
E4
R18
0.1
CLOCK DUTY STABILIZE OFF
CLOCK DUTY STABILIZE ON
R2
1K
G2
VCC1
VDD
2
JP3
VDD
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DB01+
DB01DB23+
DB23DB45+
DB45DB67+
DB67DB89+
DB89DB1011+
DB1011DB1213+
DB1213-
OF+
OF-
DA01+
DA01DA23+
DA23DA45+
DA45DA67+
DA67DA89+
DA89DA1011+
DA1011DA1213+
DA1213-
CLKOUT+
CLKOUT-
RUN
SLEEP
R3
1K
P14
P10
P9
P8
P7
P6
P5
P2
P1
N10
N9
N8
N7
N6
N5
N4
N3
N2
B11
A11
B12
A12
D12
C12
B13
A13
D13
C13
D14
E14
B14
C14
B10
A10
M14
N14
K14
L14
M13
L13
P13
N13
M12
L12
P12
N12
P11
N11
H14
G14
0.1uF
C15
E5
R19
0.1
1
L1
15nH
A4
B1
C1
M1
M4
N1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
D2
D3
D4
D7
D8
D9
D10
D11
E2
E3
E4
E7
E8
E11
E12
F2
F5
F6
F7
F8
F10
F11
F12
F13
F14
G1
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
H1
H3
H5
H6
H7
H8
H10
H11
H12
H13
J1
J2
J5
J6
J7
J8
J10
J11
J12
J13
J14
K2
K7
K8
K11
K12
L1
L2
L3
L4
L7
L8
M2
M5
M6
M7
M8
M9
M10
M11
3
1
D5
+IN_Q
3
1
F9
J9
VDD
VDD
1
K9
K10
L9
L10
L11
PAR_SER#
CS#
SCK
SDI
SDO
E13
K13
OVDD
OVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
JP4
VDD
3
30
1
VCC1
DB01+
DB01DB23+
DB23DB45+
DB45DB67+
DB67DB89+
DB89DB1011+
DB1011DB1213+
DB1213-
OF+
OF-
DA01+
DA01DA23+
DA23DA45+
DA45DA67+
DA67DA89+
DA89DA1011+
DA1011DA1213+
DA1213-
CLKOUT+
CLKOUT-
~CS
SCK
SDI
SDO
3.5 mA
1.75 mA
R4
1K
LTM9013
TYPICAL APPLICATIONS
9013f
GND
+5V IN
E8
+
C29
47uF
2
4.7uF
4.7uF
~AMP_SHDN
C31
C30
VCTRL
VIN
VIN
R47
1K
C37
0.1uF
5
8
7
U4
VCTRL
VIN
VIN
C34
0.1uF
5
8
7
6
1
SET
4
C33
0.1uF
1
9
2
3
R43
182K
0.1uF
9
VCC1
+5V
VCC1
C36
1
2
3
U7
Si1563DH
PAD
VOUT
VOUT
VOUT
LT3080EDD
R41
330K
PAD
VOUT
VOUT
VOUT
LT3080EDD
5
SET
4
U3
4
3
+5V_IN
+
+
R40
3K
C35
47uF
VDD
VCC2
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
SEAM-10X40PIN
J4C
EN
DIS
R48
10K
SDA
2
JP8
SCL
R49
10K
SDO
SDA
SCL
R50
10K
EEPROM WRITE
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
R44
10K
SCK
SDI
~CS
R45
10K
R46
10K
6
5
7
3
2
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
SCL
SDA
WP
A2
A1
A0
U5
24LC32A-I /ST
SEAM-10X40PIN
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_N
GA1
3P3V
GND
3P3V
GND
3P3V
J4D
0.1uF
C38
GND
CLK0_C2M_P
CLK0_C2M_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
U8
FMC_MOUNTING_HOLE
U6
SEAM-10X40PIN
J4G
FMC_MOUNTING_HOLE
FMC_MOUNTING_HOLE U10
FMC_MOUNTING_HOLE U9
CLKOUT+
CLKOUT-
Figure 19. Additional Schematic Elements for Recommended Layout
R42
3K
VDD
+1.8V
C32
47uF
VCC2
+3.3V
3
1
8
VCC
VSS
4
GND
GND
GND
For more information www.linear.com/LTM9013
GND
E7
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
DA1213+
DA1213-
OF+
OF-
DB01+
DB01-
DB45+
DB45-
DB89+
DB89-
DB1213+
DB1213-
DA01+
DA01-
DA45+
DA45-
DA89+
DA89-
VREF_A_M2C
PRSNT_M2C_N
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
SEAM-10X40PIN
J4H
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
DA1011+
DA1011-
DB23+
DB23-
DB67+
DB67-
DB1011+
DB1011-
DA23+
DA23-
DA67+
DA67-
LTM9013
TYPICAL APPLICATIONS
9013f
31
LTM9013
TYPICAL APPLICATIONS
Figure 20. Layer 1
Figure 21. Layer 2
9013f
32
For more information www.linear.com/LTM9013
LTM9013
TYPICAL APPLICATIONS
Figure 22. Layer 3
Figure 23. Layer 4
9013f
For more information www.linear.com/LTM9013
33
LTM9013
TYPICAL APPLICATIONS
Figure 24. Layer 5
Figure 25. Layer 6
9013f
34
For more information www.linear.com/LTM9013
0.60 ±0.025 Ø 196x
2.50
SUGGESTED PCB LAYOUT
TOP VIEW
1.50
PACKAGE TOP VIEW
0.50
4
1.50
PIN “A1”
CORNER
0.00
0.50
6.20
6.80
6.50
E
2.50
aaa Z
6.50
5.50
4.50
3.50
3.50
4.50
5.50
Y
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTM9013
6.50
5.50
4.50
3.50
2.50
1.50
0.50
0.50
1.50
2.50
3.50
4.50
5.50
6.50
D
X
6.80
6.20
0.00
aaa Z
// bbb Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
NOM
2.82
0.50
2.32
0.60
0.60
15.0
15.0
1.0
13.0
13.0
0.32
2.00
A
MAX
3.02
0.60
2.42
0.65
0.65
NOTES
DETAIL B
PACKAGE SIDE VIEW
A2
0.42
2.05
0.15
0.10
0.15
0.15
0.08
TOTAL NUMBER OF BALLS: 196
0.22
1.95
b1
DIMENSIONS
ddd M Z X Y
eee M Z
MIN
2.62
0.40
2.22
0.55
0.55
DETAIL A
Øb (196 PLACES)
DETAIL B
H2
MOLD
CAP
ccc Z
Z
Z
(Reference LTC DWG# 05-08-1907 Rev Ø)
BGA Package
196-Lead (15mm × 15mm × 2.82mm)
3
F
13
12
11
e
9
8
G
7
6
5
PACKAGE BOTTOM VIEW
10
4
b
3
2
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
TRAY PIN 1
BEVEL
BGA 196 0911 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
1
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
14
COMPONENT
PIN “A1”
e
SEE NOTES
P
N
M
L
K
J
H
G
F
E
D
C
B
A
PIN 1
LTM9013
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
9013f
35
LTM9013
TYPICAL APPLICATION
Block Diagram for IM2 Adjustment. Only the I-Channel Is Shown
DSP
1-D
MINIMIZATION
ALGORITHM
DAC
IP2I
1MHz BPF
LTM9013
LNA
RMS
DETECTION
ADC
LOOPBACK
fLO = 1990MHz
f1 = 20MHz
DAC
PA
+
f2 = 21MHz
LTC5588-1
9013 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
1250mW, 77.7dB SNR, 100dB SFDR, 64-Lead QFN Package
ADCs
LTC2208
LTC2157-14/ LTC2156-14/ 14-Bit, 250Msps/210Msps/170Msps,
LTC2155-14
1.8V Dual ADC, DDR LVDS Outputs
605mW/565mW/511mW, 70dB SNR, 90dB SFDR, 9mm × 9mm
64-Lead QFN Package
LTC2152-14/LTC2151-14/
LTC2150-14
14-Bit, 250Msps/210Msps/170Msps,
1.8V Single ADC, DDR LVDS Outputs
338mW/316mW/290mW, 70dB SNR, 90dB SFDR, 6mm × 6mm
40-Lead QFN Package
LTC2158-14
14-Bit, 310Msps 1.8V Dual ADC, DDR LVDS Outputs,
Low Power
724mW, 68.8dB SNR, 88dB SFDR, 9mm × 9mm 64-Lead
QFN Package
LT5517
40MHz to 900MHz Direct Conversion Quadrature
Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5527
400MHz to 3.7GHz High Linearity Downconverting Mixer
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
LT5575
800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator,
Integrated RF and LO Transformer
LTC6409
10GHz GBW, 1.1nV/√Hz Differential Amplifier/ADC Driver
88dB SFDR at 100MHz, Input Range Includes Ground 52mA
Supply Current, 3mm × 2mm QFN Package
LTC6412
800MHz, 31dB Range, Analog-Controlled Variable
Gain Amplifier
Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz,
10dB Noise Figure, 4mm × 4mm QFN-24 Package
LTC6420-20
1.8GHz Dual Low Noise, Low Distortion Differential ADC
Drivers for 300MHz IF
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply
Current per Amplifier, 3mm × 4mm QFN-20 Package
LTM9002
14-Bit Dual Channel IF/Baseband Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain
Differential Amplifiers
LTM9003
12-Bit Digital Pre-Distortion Receiver
Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to
3.8GHz Input Frequency Range
RF Mixers/Demodulators
Amplifiers/Filters
Receiver Subsystems
9013f
36
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM9013
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM9013
LT 0313 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2013
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