TI CY74FCT2543CTSOC 8-bit latched transceiver with 3-state output Datasheet

CY74FCT2543T
8-BIT LATCHED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
Q OR SO PACKAGE
(TOP VIEW)
Function and Pinout Compatible With FCT
and F Logic
25-W Output Series Resistors to Reduce
Transmission-Line Reflection Noise
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
12-mA Output Sink Current
15-mA Output Source Current
Separation Controls for Data Flow in Each
Direction
Back-to-Back Latches for Storage
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
3-State Outputs
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
CEAB
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CEBA
B0
B1
B2
B3
B4
B5
B6
B7
LEAB
OEAB
description
The CY74FCT2543T octal latched transceiver contains two sets of eight D-type latches. Separate latch enable
(LEAB, LEBA) and output enable (OEAB, OEBA) inputs permit each latch set to have independent control of
inputting and outputting in either direction of data flow. For example, for data flow from A to B, the A-to-B enable
(CEAB) input must be low to enter data from A or to take data from B, as indicated in the function table. With
CEAB low, a low signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a
subsequent low-to-high transition of LEAB puts the A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both low, the 3-state B output buffers are active and reflect
data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and
OEAB inputs. On-chip termination resistors at the outputs reduce system noise caused by reflections. The
CY74FCT2543T can replace the CY74FCT543T to reduce noise in an existing design.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CY74FCT2543T
8-BIT LATCHED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001
PIN DESCRIPTION
NAME
DESCRIPTION
OEAB
A-to-B output-enable input (active low)
OEBA
B-to-A output-enable input (active low)
CEAB
A-to-B enable input (active low)
CEBA
B-to-A enable input (active low)
LEAB
A-to-B latch-enable input (active low)
LEBA
B-to-A latch-enable input (active low)
A
A-to-B data inputs or B-to-A 3-state outputs
B
B-to-A data inputs or A-to-B 3-state outputs
ORDERING INFORMATION
QSOP – Q
SOIC – SO
–40°C to 85°C
SPEED
(ns)
PACKAGE†
TA
QSOP – Q
SOIC – SO
ORDERABLE
PART NUMBER
Tape and reel
5.3
CY74FCT2543CTQCT
Tube
5.3
CY74FCT2543CTSOC
Tape and reel
5.3
CY74FCT2543CTSOCT
Tape and reel
6.5
CY74FCT2543ATQCT
Tube
6.5
CY74FCT2543ATSOC
Tape and reel
6.5
CY74FCT2543ATSOCT
TOP-SIDE
MARKING
FCT2543C
FCT2543C
FCT2543A
FCT2543A
QSOP – Q
Tape and reel
8.5
CY74FCT2543TQCT
FCT2543
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
CEAB
LEAB
OEAB
LATCH
A-TO-B‡
OUTPUT
B
H
X
X
Storing
Z
X
H
X
Storing
X
X
X
H
X
Z
L
L
L
Transparent
Current A inputs
L
H
L
Storing
Previous A inputs
‡ Before LEAB low-to-high transition
H = High logic level, L = Low logic level, X = Don’t care,
Z = High-impedance state
A-to-B data flow shown; B-to-A is the same, except using CEBA, LEBA,
and OEBA.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY74FCT2543T
8-BIT LATCHED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001
functional block diagram
Detail A
B0
D Q
LE
A0
Q D
LE
A1
B1
A2
B2
A3
A4
B3
Detail A x 7
B4
A5
B5
A6
B6
A7
B7
OEBA
OEAB
CEBA
CEAB
LEBA
LEAB
absolute maximum rating over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 135_C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
– 15
mA
IOL
TA
Low-level output current
12
mA
85
°C
High-level input voltage
2
Operating free-air temperature
–40
V
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CY74FCT2543T
8-BIT LATCHED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
IIN = –18 mA
IOH = –15 mA
VOL
Rout
VCC = 4.75 V,
VCC = 4.75 V,
IOL = 12 mA
IOL = 12 mA
Vhys
All inputs
MIN
2.4
20
TYP†
MAX
UNIT
–0.7
–1.2
V
3.3
V
0.3
0.55
25
40
0.2
IIH
VCC = 5
5.25
25 V
VIN = VCC
VIN = 2.7 V
IIL
IOZH
VCC = 5.25 V,
VCC = 5.25 V,
VIN = 0.5 V
VOUT = 2.7 V
IOZL
IOS‡
VCC = 5.25 V,
VCC = 5.25 V,
VOUT = 0.5 V
VOUT = 0 V
Ioff
ICC
VCC = 0 V,
VCC = 5.25 V,
VOUT = 4.5 V
VIN ≤ 0.2V,
∆ICC
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open,
CEAB and OEAB = LOW, CEBA = HIGH,
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
V
W
V
5
±1
µA
±1
µA
15
µA
–15
µA
–120
–225
mA
±1
µA
0.1
0.2
mA
0.5
2
mA
0.06
1.2
mA/
MHz
0.7
1.4
VIN = 3.4 V or GND
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
1.2
3.4
2.8
5.6||
VIN = 3.4 V or GND
5.1
14.6||
Ci
5
10
pF
Co
9
12
pF
ICCD¶
IC#
VCC = 5.25 V, f0 = 10 MHz,
Outputs open,
CEAB and OEAB = LOW
LOW,
CEBA = HIGH,
f0 = LEAB = 10 MHz
–60
VIN ≥ VCC – 0.2 V
One bit switching
at f1 = 5 MHz
at 50% duty cycle
Eight bits switching
at f1 = 5 MHz
at 50% duty cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
mA
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC
= Total supply current
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY74FCT2543T
8-BIT LATCHED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY74FCT2543T
PARAMETER
MIN
CY74FCT2543AT
MAX
MIN
MAX
CY74FCT2543CT
MIN
MAX
UNIT
tw
tsu
Pulse duration, LEBA or LEAB low
5
5
5
ns
Setup time, high or low
A or B before LEBA↓ or LEAB↓
2
2
2
ns
th
Hold time, high or low
A or B after LEBA↓ or LEAB↓
2
2
2
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
tPLH
tPHL
CY74FCT2543T
CY74FCT2543AT
CY74FCT2543CT
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
B or A
25
2.5
85
8.5
25
2.5
65
6.5
25
2.5
55
5.5
ns
LEBA or LEAB
A or B
25
2.5
12 5
12.5
25
2.5
8
25
2.5
7
ns
tPZH
tPZL
A or B
2
12
2
9
2
8
OEBA or OEAB
2
12
2
9
2
8
tPZH
tPZL
2
12
2
9
2
8
CEBA or CEAB
A or B
2
12
2
9
2
8
A or B
2
9
2
7.5
2
6.5
OEBA or OEAB
2
9
2
7.5
2
6.5
A or B
2
9
2
7.5
2
6.5
CEBA or CEAB
2
9
2
7.5
2
6.5
tPHZ
tPLZ
tPHZ
tPLZ
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
ns
ns
ns
5
CY74FCT2543T
8-BIT LATCHED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
74FCT2543ATSOCTE4
ACTIVE
SOIC
DW
24
TBD
Call TI
Call TI
-40 to 85
74FCT2543ATSOCTG4
ACTIVE
SOIC
DW
24
TBD
Call TI
Call TI
-40 to 85
CY74FCT2543ATQCT
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT2543A
CY74FCT2543ATQCTE4
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT2543A
CY74FCT2543ATQCTG4
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT2543A
CY74FCT2543ATSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT2543A
CY74FCT2543ATSOCE4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT2543A
CY74FCT2543ATSOCG4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT2543A
CY74FCT2543ATSOCT
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
-40 to 85
FCT2543A
CY74FCT2543CTQCT
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT2543C
CY74FCT2543CTQCTE4
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT2543C
CY74FCT2543CTQCTG4
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT2543C
CY74FCT2543CTSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT2543C
CY74FCT2543CTSOCE4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT2543C
CY74FCT2543CTSOCG4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT2543C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CY74FCT2543ATQCT
SSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT2543CTQCT
SSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CY74FCT2543ATQCT
SSOP
DBQ
24
2500
367.0
367.0
38.0
CY74FCT2543CTQCT
SSOP
DBQ
24
2500
367.0
367.0
38.0
Pack Materials-Page 2
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