ONSEMI MJW16206

MOTOROLA
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by MJW16206/D
SEMICONDUCTOR TECHNICAL DATA
MJW16206
SCANSWITCH
NPN Bipolar Power Deflection Transistors
For High and Very High Resolution CRT Monitors
The MJF16206 and the MJW16206 are state–of–the–art SWITCHMODE bipolar
power transistors. They are specifically designed for use in horizontal deflection
circuits for high and very high resolution, monochrome and color CRT monitors.
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POWER TRANSISTORS
12 AMPERES
1200 VOLTS — VCES
50 and 150 WATTS
1200 Volt VCES Breakdown Capability
Typical Dynamic Desaturation Specified (New Turn–Off Characteristic)
Maximum Repetitive Emitter–Base Avalanche Energy Specified (Industry First)
High Current Capability: Performance Specified at 6.5 Amps
Continuous Rating — 12 Amps Max
Pulsed Rating — 15 Amps Max
Isolated MJF16206 is UL Recognized
Fast Switching: 100 ns Inductive Fall Time (Typ)
1000 ns Inductive Storage Time (Typ)
Low Saturation Voltage
0.25 Volts (Typ) at 6.5 Amps Collector Current
High Emitter–Base Breakdown Capability For High Voltage Off Drive Circuits —
8.0 V (Min)
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MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector–Emitter Breakdown Voltage
VCES
1200
Vdc
Collector–Emitter Sustaining Voltage
VCEO(sus)
500
Vdc
VEBO
8.0
Vdc
Emitter–Base Voltage
Isolation Voltage
(RMS for 1 sec., TA = 25_C,
Relative Humidity
30%)
VISOL
Vrms
—
—
Figure 19
Figure 20
Collector Current — Continuous
Collector Current — Pulsed (1)
IC
ICM
12
15
Adc
Base Current — Continuous
Base Current — Pulsed (1)
IB
IBM
5.0
10
Adc
W(BER)
0.2
mjoules
PD
150
39
1.49
Watts
TJ, Tstg
– 55 to + 150
_C
Symbol
Max
Unit
RθJC
0.67
_C/W
TL
260
_C
Repetitive Emitter–Base Avalanche Energy
Total Power Dissipation @ TC = 25_C
Total Power Dissipation @ TC = 100_C
Derated above 25_C
Operating and Storage Temperature
CASE 340K–01
TO–247AE
W/_C
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance — Junction to Case
Lead Temperature for Soldering Purposes 1/8″
from the Case for 5 seconds
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle
10%.
SCANSWITCH is a trademark of Motorola Inc.
REV 3
 Motorola, Inc. 1996
Motorola Bipolar Power Transistor Device Data
1
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MJW16206
ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
—
—
—
—
250
25
—
—
25
500
—
—
8.0
11
—
—
—
0.15
0.25
1.0
1.0
—
0.9
1.5
—
5.0
3.0
24
8.0
6.0
—
13
—
tds
—
250
—
ns
EB(off)
—
30
—
µjoules
Cob
—
180
350
pF
fT
—
3.0
—
MHz
Cc–hs
—
17
—
pF
tsv
tfi
—
—
1000
100
2250
250
OFF CHARACTERISTICS (1)
Collector Cutoff Current
(VCE = 1200 Vdc, VBE = 0 V)
(VCE = 850 Vdc, VBE = 0 V)
ICES
Emitter–Base Leakage
(VEB = 8.0 Vdc, IC = 0)
IEBO
Collector–Emitter Sustaining Voltage (Figure 10)
(IC = 10 mAdc, IB = 0)
VCEO(sus)
Emitter–Base Breakdown Voltage
(IE = 1.0 mA, IC = 0)
V(BR)EBO
µAdc
µAdc
Vdc
Vdc
ON CHARACTERISTICS (1)
Collector–Emitter Saturation Voltage
(IC = 3.0 Adc, IB = 400 mAdc)
(IC = 6.5 Adc, IB = 1.5 Adc)
VCE(sat)
Base–Emitter Saturation Voltage
(IC = 6.5 Adc, IB = 1.5 Adc)
VBE(sat)
DC Current Gain
(IC = 1.0 Adc, VCE = 5.0 Vdc)
(IC = 10 Adc, VCE = 5.0 Vdc)
(IC = 12 Adc, VCE = 5.0 Vdc)
hFE
Vdc
Vdc
—
DYNAMIC CHARACTERISTICS
Dynamic Desaturation Interval (Figure 15)
(IC = 6.5 Adc, IB = 1.5 Adc, LB = 0.5 µH)
Emitter–Base Avalanche Turn–off Energy (Figure 15)
(t = 500 ns, RBE = 22 Ω)
Output Capacitance
(VCE = 10 Vdc, IE = 0, ftest = 100 kHz)
Gain Bandwidth Product
(VCE = 10 Vdc, IC = 0.5 A, ftest = 1.0 MHz)
Collector–Heatsink Capacitance — MJF16206 Isolated Package
(Mounted on a 1″ x 2″ x 1/16″ Copper Heatsink,
VCE = 0, ftest = 100 kHz)
SWITCHING CHARACTERISTICS
Inductive Load (Figure 15) (IC = 6.5 A, IB = 1.5 A)
Storage
Fall Time
(1) Pulse Test: Pulse Width = 300 µs, Duty Cycle
2
ns
2.0%.
Motorola Bipolar Power Transistor Device Data
hFE , DC CURRENT GAIN
100
70
50
TJ = 100°C
30
20
25°C
– 55°C
10
7
5
3
VCE = 5 V
2
1
0.2
2
3
5 7
0.5 0.7 1
IC, COLLECTOR CURRENT (AMPS)
0.3
10
20
VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS)
MJW16206
5
TJ = 25°C
TJ = 100°C
3
2
1
0.7
0.5
0.3
0.2
IC/IB1 = 10
10
0.1
0.07
0.05
VBE, BASE–EMITTER VOLTAGE (VOLTS)
VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS)
8A
IC = 2 A
4A
6.5 A
10 A
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05 0.07 0.1
0.2 0.3
0.5 0.7 1
IB, BASE CURRENT (AMPS)
2
3
2 3 5 7 10 20 30 50 100 200 300 500 1K
3
IC/IB1 = 5 to 10
1
0.7
0.5
0.3
TJ = 25°C
TJ = 100°C
0.2
0.3
0.5 0.7
1
2
3
5
7
10
20
10
7
5
3
2
1
0.7
0.5
0.3
0.2
0.1
0.1
f(test) = 1 MHz
TC = 25°C
VCE = 10 V
0.2
0.3
0.5 0.7
1
2
3
5
VR, REVERSE VOLTAGE (VOLTS)
IC, COLLECTOR CURRENT (AMPS)
Figure 5. Typical Capacitance
Figure 6. Typical Transition Frequency
Motorola Bipolar Power Transistor Device Data
20
Figure 4. Typical Base–Emitter
Saturation Voltage
f T, TRANSITION FREQUENCY (MHz)
C, CAPACITANCE (pF)
Cob
TC = 25°C
f = 1 MHz
1
10
IC, COLLECTOR CURRENT (AMPS)
Cib
10
0.1 0.2 0.3 0.5
7
5
2
0.1
0.2
5
1K
700
500
300
200
100
70
50
30
20
3
10
7
5
Figure 3. Typical Collector Saturation Region
10K
7K
5K
3K
2K
2
Figure 2. Typical Collector–Emitter
Saturation Voltage
TJ = 25°C
3
2
1
IC, COLLECTOR CURRENT (AMPS)
Figure 1. Typical DC Current Gain
7
5
0.5 0.7
0.2 0.3
5
7
10
3
MJW16206
SAFE OPERATING AREA INFORMATION
20
10
MJW16206
5
3
2
dc
10 µs
5 ms
100
ns
1
0.5
0.3
0.2
WIREBOND LIMIT
THERMAL LIMIT
SECONDARY BREAKDOWN
LIMIT
0.1
0.05
0.03
0.02
IC, COLLECTOR CURRENT (AMPS)
IC, COLLECTOR CURRENT (AMPS)
30
20
II*
IC/IB1 ≥ 5
TJ ≤ 100°C
16
12
8
VBE(off) = 5 V
4
0V
2V
0
1
20 30 50
10
100 200 300 500
2 3 5
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
1K
0
200
800
600
400
1K
1.2K
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
*REGION II — EXPANDED FBSOA USING
MUR8100E, ULTRAFAST RECTIFIER (SEE FIGURE 12)
Figure 8. Maximum Reverse Bias
Safe Operating Area
Figure 7. Maximum Forward Biased
Safe Operating Area
100
FORWARD BIAS
90
POWER RATING FACTOR (%)
There are two limitations on the power handling ability of a
transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation;
i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 7 is based on TC = 25_C; T J(pk) is
variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated
when TC ≥ 25_C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the
voltages shown on Figure 7 may be found at any case temperature by using the appropriate curve on Figure 9.
At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the limitations imposed by second breakdown.
80
SECOND BREAKDOWN
DERATING
70
60
50
THERMAL
DERATING
40
30
20
10
0
25
50
75
100
125
150
TC, CASE TEMPERATURE (°C)
Figure 9. Power Derating
REVERSE BIAS
Inductive loads, in most cases, require the emitter–to–
base junction be reversed biased because high voltage and
high current must be sustained simultaneously during turn–
off. Under these conditions, the collector voltage must be
held to a safe level at or below a specific value of collector
current. This can be accomplished by several means such as
4
active clamping, RC snubbing, load line shaping, etc. The
safe level for these devices is specified as Reverse Biased
Safe Operating Area and represents the voltage–current
condition allowable during reverse biased turn–off. This rating is verified under clamped conditions so that the device is
never subjected to an avalanche mode. Figure 8 gives the
RBSOA characteristics.
Motorola Bipolar Power Transistor Device Data
MJW16206
0.02 µF
H.P. 214
OR EQUIV.
P.G.
+ V ≈ 11 V
100
T1
2N6191
+
0
–
20
IC(pk)
+V
IC
0V
10 µF
*IC
–V
RB1
≈ – 35 V
A
T.U.T.
A
MR856
RB2
0.02 µF
+ –
50
VCE(pk)
L
*IB
50
VCE
VCC
Vclamp
IB1
IB
2N5337
1 µF
RBSOA
L = 200 µH
RB2 = 0
VCC = 20 Volts
RB1 selected for desired IB1
500
100
V(BR)CEO
L = 10 mH
RB2 = ∞
VCC = 20 Volts
–V
T1
IB2
(ICpk)
[ LcoilVCC
T1 adjusted to obtain IC(pk)
*Tektronix P–6042 or Equivalent
Note: Adjust – V to obtain desired VBE(off) at Point A.
Figure 10. RBSOA/V(BR)CEO(sus) Test Circuit
r(t), TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
1
D = 0.5
0.5
0.2
0.2
0.1
0.1
RθJC(t) = r(t) RθJC
RθJC = 0.67°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
0.05
SINGLE PULSE
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
0.01
0.1
1
100
10
1K
10K
t, TIME (ms)
Figure 11. Thermal Response
VCE (1000 V MAX)
10 µF MUR8100
+15
1 µF
100 µF
150 Ω
10 mH
MTP8P10
100 Ω
MTP8P10
RB1
MUR1100
MPF930
MUR105
+10
MPF930
T.U.T.
MUR105
50 Ω
RB2
MTP12N10
MJE210
500 µF
150 Ω
1 µF
VOff
Note: Test Circuit for Ultrafast FBSOA
Note: RB2 = 0 and VOff = – 5 Volts
Figure 12. Switching Safe Operating Area
Motorola Bipolar Power Transistor Device Data
5
MJW16206
DYNAMIC DESATURATION
The SCANSWITCH series of bipolar power transistors are
specifically designed to meet the unique requirements of horizontal deflection circuits in computer monitor applications.
Historically, deflection transistor design was focused on minimizing collector current fall time. While fall time is a valid
figure of merit, a more important indicator of circuit performance as scan rates are increased is a new characteristic,
“dynamic desaturation.” In order to assure a linear collector
current ramp, the output transistor must remain in hard saturation during storage time and exhibit a rapid turn–off transition. A sluggish transition results in serious consequences.
tfi
90% IC(pk)
VCE
IC
VCE = 20 V
10% IC(pk)
0
tsv
0
0% IB
As the saturation voltage of the output transistor increases,
the voltage across the yoke drops. Roll off in the collector
current ramp results in improper beam deflection and distortion of the image at the right edge of the screen. Design
changes have been made in the structure of the SCANSWITCH series of devices which minimize the dynamic desaturation interval. Dynamic desaturation has been defined in
terms of the time required for the VCE to rise from 1.0 to
5.0 volts (Figures 13 and 14) and typical performance at optimized drive conditions has been specified. Optimization of
device structure results in a linear collector Current ramp, excellent turn–off switching performance, and significantly lower overall power dissipation.
COLLECTOR-EMITTER VOLTAGE (VOLTS)
DYNAMIC DESATURATION
5
VCE
4
3
DYNAMIC DESATURATION TIME
IS MEASURED FROM VCE = 1 V
TO VCE = 5 V
2
1
0
tds
TIME (ns)
Figure 13. Deflection Simulator Switching
Waveforms From Circuit in Figure 15
6
Figure 14. Definition of Dynamic
Desaturation Measurement
Motorola Bipolar Power Transistor Device Data
MJW16206
tant advantages. First, the configuration of T1 allows LB to be
placed outside the path of forward base current making it unnecessary to expend energy to reverse current flow as in a
series base inductor. Second, there is no base resistor to limit forward base current and hence no power loss associated
with setting the value of the forward base current. The process of generating the ramp stores rather than dissipates energy. Tailoring the amount of energy stored in T 1 to the
amount of energy, EB (off) , that is required to turn–off the output transistor results in essentially lossless operation. [Note:
B+ and the primary inductance of T1 (LP) are chosen such
that 1/2 LP Ib2 = EB(off)].
EMITTER–BASE TURN–OFF ENERGY
Typical techniques for driving horizontal outputs rely on a
pulse transformer to supply forward base current, and a
turn–off network that includes a series base inductor to limit
the rate of transition from forward to reverse drive. An alternate drive scheme has been used to characterize the
SCANSWITCH series of devices (see Figure 15). This circuit
produces a ramp of base drive, eliminating the heavy overdrive at the beginning of the collector current ramp and
underdrive just prior to turnoff produced by typical drive strategies. This high performance drive has two additional impor-
+ 24 V
U2
MC7812
VI
R14
150
R13
1K
VO
GND
+ C1
100 µF
(IB)
Q6
2N5401
R7
2.7K
R16
430
Q2
MJ11016
C7
110 pF
R8
9.1K
R9
470
+ C3
10 µF
+ C2
10 µF
R17
MDC1000A
R5
1K
R1
1K
(IC)
Q5
MJ11016
3.9 V
C6
100 µF
Q3
MTP3055E
+
LY
120
C4
0.005
R3
250
8
C5
0.1
6
7
OSC
VCC
%
OUT
GND
R6
1K
D2
SCANSWITCH
DAMPER
DIODE
R15
10K
CY
1
T1
U1
MC1391P
2
R12
470
1W
T1: FERROXCUBE POT CORE #1811P3C8
T1: PRIMARY SEC. TURNS RATIO = 13:4
T1: GAPPED FOR LP = 30 µH
LB = 0.5 µH
CY = 0.01 µF
LY = 13 µH
D1
MUR110
VCE
LB
Q4 SCANSWITCH
HORIZ OUTPUT
TRANSISTOR
R4
22
Figure 15. High Resolution Deflection Application Simulator
Motorola Bipolar Power Transistor Device Data
7
MJW16206
+15
1 µF
ts and tf
150 Ω
100 µF
100 Ω
MTP8P10
MTP8P10
V(off) adjusted
to give specified
off drive
VCC
250 V
IC
6.5 A
IB1
1.3 A
IB2
Per Fig. 17 & 18
RB1
7.7 Ω
RL
38 Ω
RB1
MPF930
A
+10 V
MPF930
MUR105
50 Ω
MTP12N10
MJE210
500 µF
1 µF
150 Ω
Voff
T.U.T.
A
*IC
*IB
RL
VCC
10
1000
7
700
5
500
IB2 = IB1
3
t, TIME (ns)
t, TIME ( µs)
Figure 16. Resistive Load Switching
2
IC/IB1 = 5
TC = 25°C
1
IB2 = 2 (IB1)
200
IC/IB = 5
TC = 25°C
100
0.7
70
0.5
IB2 = 2 (IB1)
50
1
2
3
5
10
7
IC, COLLECTOR CURRENT (AMPS)
Figure 17. Typical Resistive Storage Time
8
IB2 = IB1
300
20
1
2
3
5
7
10
IC, COLLECTOR CURRENT (AMPS)
Figure 18. Typical Resistive Fall Time
Motorola Bipolar Power Transistor Device Data
20
MJW16206
TEST CONDITIONS FOR ISOLATION TESTS*
MOUNTED
FULLY ISOLATED
PACKAGE
MOUNTED
FULLY ISOLATED
PACKAGE
LEADS
0.099” MIN
LEADS
HEATSINK
HEATSINK
0.110” MIN
Figure 19. Screw or Clip Mounting Position
for Isolation Test Number 1
Figure 20. Screw or Clip Mounting Position
for Isolation Test Number 2
* Measurement made between leads and heatsink with all leads shorted together.
MOUNTING INFORMATION**
4–40 SCREW
CLIP
PLAIN WASHER
HEATSINK
COMPRESSION WASHER
HEATSINK
NUT
Figure 21. Typical Mounting Techniques*
Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw
torque of 6 to 8 in . lbs is sufficient to provide maximum power dissipation capability. The compression washer helps to maintain a constant pressure on the package over time and during large temperature excursions.
Destructive laboratory tests show that using a hex head 4-40 screw, without washers, and applying a torque in excess of 20 in . lbs will
cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability.
Additional tests on slotted 4-40 screws indicate that the screw slot fails between 15 to 20 in . lbs without adversely affecting the package. However, in order to positively ensure the package integrity of the fully isolated device, Motorola does not recommend exceeding 10
in . lbs of mounting torque under any mounting conditions.
** For more information about mounting power semiconductors see Application Note AN1040.
Motorola Bipolar Power Transistor Device Data
9
MJW16206
PACKAGE DIMENSIONS
0.25 (0.010)
M
–T–
–Q–
T B M
E
–B–
C
4
L
U
A
R
1
K
2
3
–Y–
P
V
H
F
G
D
0.25 (0.010)
M
Y Q
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
DIM
A
B
C
D
E
F
G
H
J
K
L
P
Q
R
U
V
MILLIMETERS
MIN
MAX
19.7
20.3
15.3
15.9
4.7
5.3
1.0
1.4
1.27 REF
2.0
2.4
5.5 BSC
2.2
2.6
0.4
0.8
14.2
14.8
5.5 NOM
3.7
4.3
3.55
3.65
5.0 NOM
5.5 BSC
3.0
3.4
INCHES
MIN
MAX
0.776
0.799
0.602
0.626
0.185
0.209
0.039
0.055
0.050 REF
0.079
0.094
0.216 BSC
0.087
0.102
0.016
0.031
0.559
0.583
0.217 NOM
0.146
0.169
0.140
0.144
0.197 NOM
0.217 BSC
0.118
0.134
S
CASE 340K–01
TO–247AE
ISSUE O
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10
◊
*MJW16206/D*
Motorola Bipolar Power Transistor Device
Data
MJW16206/D