ONSEMI NTD20N06-1G

NTD20N06
Power MOSFET
20 Amps, 60 Volts, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
•
•
•
•
•
•
•
•
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Pb−Free Packages are Available
Lower RDS(on)
Lower VDS(on)
Lower Capacitances
Lower Total Gate Charge
Lower and Tighter VSD
Lower Diode Reverse Recovery Time
Lower Reverse Recovery Stored Charge
V(BR)DSS
RDS(on) TYP
ID MAX
60 V
37.5 m
20 A
N−Channel
D
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
S
MARKING
DIAGRAMS
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 10 M)
VDGR
60
Vdc
VGS
VGS
20
30
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp10 s)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
L = 1.0 mH, IL(pk) = 18.4 A, VDS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
August, 2004 − Rev. 6
4
Vdc
1 2
Adc
ID
ID
20
10
60
Apk
60
0.40
1.88
1.36
W
W/°C
W
W
TJ, Tstg
−55 to
175
°C
EAS
170
mJ
IDM
PD
2
1
3
Drain
Gate
Source
4
Drain
4
DPAK−3
CASE 369D
STYLE 2
2
3
1 2 3
Gate Drain Source
°C/W
RJC
RJA
RJA
2.5
80
110
TL
260
°C
1
DPAK
CASE 369C
STYLE 2
3
1
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using the 0.5 sq in drain pad size.
 Semiconductor Components Industries, LLC, 2004
4
Drain
AYWW
20N06
Rating
Drain−to−Source Voltage
AYWW
20N06
•
•
•
•
20N06
A
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
NTD20N06/D
NTD20N06
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(BR)DSS
Min
Typ
Max
Unit
60
−
71.7
79.4
−
−
−
−
−
−
1.0
10
−
−
±100
2.0
−
2.91
6.9
4.0
−
−
37.5
46
−
−
0.78
1.57
1.10
−
gFS
−
13.2
−
mhos
pF
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 10 Adc)
RDS(on)
Static Drain−to−Source On−Voltage (Note 3)
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 6.0 Adc)
Vdc
mV/°C
m
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
f=1
1.0
0 MHz)
Transfer Capacitance
Ciss
−
725
1015
Coss
−
213
300
Crss
−
58
120
td(on)
−
9.5
20
tr
−
60.5
120
td(off)
−
27.1
60
tf
−
37.1
80
QT
−
21.2
30
Q1
−
5.6
−
Q2
−
7.3
−
VSD
−
−
1.0
0.87
1.2
−
Vdc
trr
−
42.9
−
nss
ta
−
33
−
tb
−
9.9
−
QRR
−
0.084
−
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Vd ID = 20 Adc,
Ad
(VDD = 30 Vdc,
VGS = 10 Vdc,
Vdc
RG = 9.1 ) (Note 3)
Fall Time
Gate
Charge
Ga
eC
a ge
Vdc ID = 20 Adc,
Adc
(VDS = 48 Vdc,
VGS = 10 Vdc) (Note 3)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 20 Adc, VGS = 0 Vdc) (Note 3)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse
e e se Recovery
eco e y Time
e
(IS = 20 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/s) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
C
ORDERING INFORMATION
Device
NTD20N06
Package
Shipping†
DPAK
75 Units/Rail
NTD20N06G
DPAK
(Pb−Free)
75 Units/Rail
NTD20N06−1
DPAK−3
75 Units/Rail
DPAK
(Pb−Free)
75 Units/Rail
DPAK
2500 Tape & Reel
DPAK
(Pb−Free)
2500 Tape & Reel
NTD20N06−1G
NTD20N06T4
NTD20N06T4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTD20N06
40
40
7V
VDS ≥ 10 V
6.5 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
9V
32
8V
6V
24
5.5 V
16
5V
8
4.5 V
0
1
3
2
4
5
3.4
TJ = −55°C
4.2
5
5.8
6.6
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
TJ = 100°C
0.045
0.035
TJ = 25°C
0.025
TJ = −55°C
0
8
16
40
32
24
7.4
0.065
VGS = 15 V
0.055
TJ = 100°C
0.045
TJ = 25°C
0.035
0.025
0.015
TJ = −55°C
0
8
16
24
32
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
40
10000
VGS = 0 V
ID = 10 A
VGS = 10 V
TJ = 150°C
1000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
TJ = 25°C
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.055
1.8
16
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 10 V
2
24
0
2.6
0.065
0.015
32
TJ = 100°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
VGS = 10 V
1.6
1.4
1.2
1
TJ = 125°C
100
TJ = 100°C
10
0.8
0.6
−50 −25
1
0
25
50
75
100
125
150
175
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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60
NTD20N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
C, CAPACITANCE (pF)
2000
1600
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
1200
Crss
Ciss
800
400
Coss
Crss
0
10
5
5
0
VGS
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
1000
12
VDS = 30 V
ID = 20 A
VGS = 10 V
QT
10
8
VGS
Q2
Q1
6
t, TIME (ns)
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
NTD20N06
4
100
tf
tr
td(off)
10
td(on)
2
ID = 20 A
TJ = 25°C
0
1
0
4
16
8
12
20
QG, TOTAL GATE CHARGE (nC)
24
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
20
VGS = 0 V
TJ = 25°C
16
12
8
4
0
0.6
0.8
0.9
0.7
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
NTD20N06
I D, DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
10 s
100 s
1 ms
10 ms
1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS , SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
180
ID = 18.4 A
160
140
120
100
80
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
150
50
75
100
125
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
0.00001
t1
t2
DUTY CYCLE, D = t1/t2
0.0001
0.001
0.01
t, TIME (s)
RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJC(t)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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1
10
NTD20N06
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
−T−
C
B
V
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD20N06
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
B
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your
local Sales Representative.
NTD20N06/D