ON MC7660 Charge pump dc-to-dc voltage converter Datasheet

MC7660
Charge Pump DC-to-DC
Voltage Converter
The MC7660 is a pin–compatible replacement for the Industry
standard ICL7660 charge pump voltage converter. It converts a +1.5V
to +10V input to a corresponding –1.5V to –10V output using only two
low–cost capacitors, eliminating inductors and their associated cost,
size and EMI.
The on–board oscillator operates at a nominal frequency of 10kHz.
Operation below 10kHz (for lower supply current applications) is
possible by connecting an external capacitor from OSC to ground
(with pin 1 open).
The MC7660 is available in an 8–pin SOIC package in extended
temperature range.
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SO–8
D SUFFIX
CASE 751
Features
Converts +5V Supply to –5V Supply
Wide Input Voltage Range: 1.5V to 10V
Efficient Voltage Conversion: 99.9%
Excellent Power Efficiency: 98%
Low Power Supply: 80µA @ 5VIN
Low Cost and Easy to Use
– Only Two External Capacitors Required
• Available in Small Outline (SO) Package
• ESD Protection: ≥ 2.5kV
• No Dx Diode Required for High Voltage Operation
•
•
•
•
•
•
PIN CONFIGURATION
(Top View)
NC 1
CAP+ 2
8 V+
GND 3
CAP– 4
6 LV
7 OSC
5 VOUT
ORDERING INFORMATION
Typical Applications
• RS–232 Negative Bias
• Display Bias
• Data Aquisition Negative Supply Generation
Device
Package
Shipping
MC7660DR2
8–Pin SOIC
2500 Tape/Reel
FUNCTIONAL BLOCK DIAGRAM
V+ CAP+
8
OSC
LV
7
RC
OSCILLATOR
B2
2
VOLTAGE–
LEVEL
TRANSLATOR
4
CAP–
6
5
INTERNAL
VOLTAGE
REGULATOR
VOUT
LOGIC
NETWORK
MC7660
3
GND
 Semiconductor Components Industries, LLC, 1999
February, 2000 – Rev. 2
1
Publication Order Number:
MC7660/D
MC7660
ABSOLUTE MAXIMUM RATINGS*
Parameter
Supply Voltage
Value
Unit
+10.5
V
V
LV and OSC Inputs Voltage (Note 1.)
V+ < 5.5V
V+ > 5.5V
–0.3 to (V+ + 0.3)
(V+ – 5.5) to (V+ + 0.3)
Current Into LV (Note 1.) V+ > 3.5V
20
Output Short Duration (VSUPPLY ≤ 5.5V)
µA
Continuous
Power Dissipation (TA ≤ 70°C)
Derate above 50°C
470
5.5
mW
mW/°C
°C
Operating Temperature Range
–40 to +85
Storage Temperature Range
–65 to +150
°C
+300
°C
Lead Temperature (Soldering, 10 Seconds)
* Maximum Ratings are those values beyond which damage to the device may occur.
1. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latch–up. It is recommended that no inputs
from sources operating from external supplies be applied prior to ”power up” of the MC7660.
ELECTRICAL CHARACTERISTICS (Specifications Measured Over Operating Temperature Range, V+ = 5V, COSC = 0,
Test Circuit (Figure 1), unless otherwise noted.
Symbol
Min
Typ
Max
Unit
—
80
180
µA
Supply Voltage Range, High
(–40°C ≤ TA ≤ +85°C, RL = 10 kW, LV Open)
3.0
—
10
Supply Voltage Range, Low
(–40°C ≤ TA ≤ +85°C, RL = 10 kW, LV to GND)
1.5
—
3.5
Output Source Resistance
IOUT = 20mA, TA = 25°C
IOUT = 20mA, 0°C ≤ TA ≤ +70°C
IOUT = 20mA, –40°C ≤ TA ≤ +85°C
V+ =2V, IOUT = 3 mA, LV to GND, 0°C ≤ TA ≤ +70°C
—
—
—
—
70
—
—
150
100
120
130
300
FOSC
Oscillator Frequency (Pin 7 Open)
—
10
—
kHz
PEFF
Power Efficiency (RL = 5kW)
95
98
—
%
VOUT EFF
Voltage Conversion Efficiency
97
99.9
—
%
ZOSC
Oscillator Impedance
V+ = 2V
V+ = 5V
—
—
1000
100
—
—
I+
Supply Current (RL =
V+H
V+L
ROUT
Characteristic
R)
V
V
IS
8
1
C1
10 mF
+
2
MC7660
7
3
6
4
5
RL
+
*NOTE:
IL V+
(+6 V)
COSC*
VO
C2
10 mF
For large values of COSC (>1000 pF), the values
of C1 and C2 should be increased to 100 mF.
Figure 1. MC7660 Test Circuit
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2
W
kW
MC7660
APPLICATIONS INFORMATION
Detailed Description
can, however, degrade operation at low voltages. To
improve low–voltage operation, the LV pin should be
connected to GND, disabling the regulator. For supply
voltages greater than 3.5V, the LV terminal must be left open
to ensure latch–up–proof operation and prevent device
damage.
The MC7660 contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 µF
polarized electrolytic capacitors. Operation is best
understood by considering Figure 2, which shows an
idealized voltage inverter. Capacitor C1 is charged to a
voltage, V+, for the half cycle when switches S1 and S3 are
closed. (Note: Switches S2 and S4 are open during this half
cycle.) During the second half cycle of operation, switches
S2 and S4 are closed, with S1 and S3 open, thereby shifting
capacitor C1 negatively by V+ volts. Charge is then
transferred from C1 to C2, such that the voltage on C2 is
exactly V+, assuming ideal switches and no load on C2.
S1
Theoretical Power Efficiency Considerations
In theory, a capacitive charge pump can approach 100%
efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The MC7660 approaches these conditions for negative
voltage multiplication if large values of C1 and C2 are used.
Energy is lost only in the transfer of charge between
capacitors if a change in voltage occurs. The energy lost
is defined by:
S2
V+
C1
GND
S3
S4
C2
E = 1/2 C1 (V12 — V22)
VOUT =
–VIN
V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Figure 2), compared to
the value of RL, there will be a substantial difference in
voltages V1 and V2. Therefore, it is not only desirable to
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C1 in order to achieve maximum efficiency of operation.
Figure 2. Idealized Charge Pump Inverter
The four switches in Figure 2 are MOS power switches;
S1 is a P–channel device, and S2, S3 and S4 are N–channel
devices. The main difficulty with this approach is that in
integrating the switches, the substrates of S3 and S4 must
always remain reverse–biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start–up, and under output short circuit
conditions (VOUT = V+), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and probable
device latch–up.
This problem is eliminated in the MC7660 by a logic
network which senses the output voltage (VOUT) together
with the level translators, and switches the substrates of S3
and S4 to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the MC7660 is an integral
part of the anti–latch–up circuitry. Its inherent voltage drop
Dos and Don’ts
• Do not exceed maximum supply voltages.
• Do not connect LV terminal to GND for supply voltages
greater than 3.5V.
• Do not short circuit the output to V+ supply for voltages
above 5.5V for extended periods; however, transient
conditions including start–up are okay.
• When using polarized capacitors in the inverting mode,
the + terminal of C1 must be connected to pin 2 of the
MC7660 and the + terminal of C2 must be connected to
GND Pin 3.
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MC7660
V+
Simple Negative Voltage Converter
Figure 3 shows typical connections to provide a negative
supply where a positive supply is available. A similar
scheme may be employed for supply voltages anywhere in
the operating range of +1.5V to +10V, keeping in mind that
pin 6 (LV) is tied to the supply negative (GND) only for
supply voltages below 3.5V.
The output characteristics of the circuit in Figure 3 are
those of a nearly ideal voltage source in series with 70W.
Thus, for a load current of –10mA and a supply voltage of
+5V, the output voltage would be –4.3V.
The dynamic output impedance of the MC7660 is due,
primarily, to capacitive reactance of the charge transfer
capacitor (C1). Since this capacitor is connected to the output
for only 1/2 of the cycle, the equation is:
XC
8
1
C1
10 mF
2
+
MC7660
VOUT
7
3
6
4
5
+
C2
10 mF
Figure 3. Simple Negative Converter
Parallel Devices
Any number of MC7660 voltage converters may be
paralleled to reduce output resistance (Figure 4). The
reservoir capacitor, C2, serves all devices, while each device
requires its own pump capacitor, C1. The resultant output
resistance would be approximately:
+ 2pf2C + 3.18W,
1
where f = 10kHz and C1 = 10µF.
R OUT
OUT (of MC7660)
+ nR(number
of devices)
V+
8
1
7
1
3
6
2
4
5
2
C1
MC7660
C1
8
MC7660
RL
7
3
6
4
5
+
C2
Figure 4. Paralleling Devices Lowers Output Impedance
Cascading Devices
has generated the external clock frequency using TTL logic,
the addition of a 10kW pull–up resistor to V+ supply is
required. Note that the pump frequency with external
clocking, as with internal clocking, will be 1/2 of the clock
frequency. Output transitions occur on the positive–going
edge of the clock.
It is also possible to increase the conversion efficiency of
the MC7660 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is
achieved by connecting an additional capacitor, COSC, as
shown in Figure 7. Lowering the oscillator frequency will
cause an undesirable increase in the impedance of the pump
(C1) and the reservoir (C2) capacitors. To overcome this,
increase the values of C1 and C2 by the same factor that the
frequency has been reduced. For example, the addition of a
100pF capacitor between pin 7 (OSC) and pin 8 (V+) will
lower the oscillator frequency to 1kHz from its nominal
frequency of 10kHz (a multiple of 10), and necessitate a
corresponding increase in the values of C1 and C2 (from
10µF to 100µF).
The MC7660 may be cascaded as shown (Figure 5) to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
VOUT = –n (VIN)
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual MC7660
ROUT values.
Changing the MC7660 Oscillator Frequency
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 6. In order to prevent
possible device latch–up, a 1kW resistor must be used in
series with the clock output. In a situation where the designer
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4
MC7660
V+
8
1
10 mF
2
+
MC7660
3
“1”
4
7
1
6
2
10 mF
5
+
8
MC7660
7
6
3
“n”
4
VOUT*
5
10 mF
+
*NOTE:
VOUT = –n V+ for 1.5 V ≤ V+ ≤ 10 V
Figure 5. Increased Output Voltage by Cascading Devices
V+
10 mF
+
1
8
2
7
MC7660
3
6
4
5
V+
V+
1 kW
CMOS
GATE
VOUT
C1
COSC
7
3
6
4
5
VOUT
+
6
4
5
VOUT =
(2 V+) – (2 VF)
D2
+
+
C1
C2
Figure 9 combines the functions shown in Figures 3 and
8 to provide negative voltage conversion and positive
voltage multiplication simultaneously. This approach would
be, for example, suitable for generating +9V and –5V from
an existing +5V supply. In this instance, capacitors C1 and
C3 perform the pump and reservoir functions, respectively,
for the generation of the negative voltage, while capacitors
C2 and C4 are pump and reservoir, respectively, for the
multiplied positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.
8
MC7660
MC7660
3
D1
Combined Negative Voltage Conversion and Positive
Supply Multiplication
V+
2
7
Figure 8. Positive Voltage Multiplier
Figure 6. External Clocking
+
8
2
10 mF
+
1
1
C2
Figure 7. Lowering Oscillator Frequency
Positive Voltage Multiplication
The MC7660 may be employed to achieve positive
voltage multiplication using the circuit shown in Figure 8.
In this application, the pump inverter switches of the
MC7660 are used to charge C1 to a voltage level of V+ – VF
(where V+ is the supply voltage and VF is the forward voltage
drop of diode D1). On the transfer cycle, the voltage on C1
plus the supply voltage (V+) is applied through diode D2 to
capacitor C2. The voltage thus created on C2 becomes (2 V+)
– (2 VF), or twice the supply voltage minus the combined
forward voltage drops of diodes D1 and D2.
The source impedance of the output (VOUT) will depend on
the output current, but for V+ = 5V and an output current of
10 mA, it will be approximately 60W.
V+
8
1
2
+
C1
VOUT =
–(V+ – VF)
MC7660
7
3
6
4
5
+
C2
D1
+
C3
VOUT =
(2 V+) – (2 VF)
D2
+
C4
Figure 9. Combined Negative Converter and
Positive Muliplier
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5
MC7660
Efficient Positive Voltage Multiplication/Conversion
switch–drive section will not operate until some positive
voltage has been generated. An initial inefficient pump, as
shown in Figure 9, could be used to start this circuit up, after
which it will bypass the other (D1 and D2 in Figure 9 would
never turn on), or else the diode and resistor shown dotted
in Figure 10 can be used to ”force” the internal regulator on.
Since the switches that allow the charge pumping
operation are bidirectional, the charge transfer can be
performed backwards as easily as forwards. Figure 10 shows
a MC7660 transforming –5V to +5V (or +5V to +10V, etc.).
The only problem here is that the internal clock and
VOUT = –V–
+
C1
10 mF
1
8
2
7
MC7660
3
6
4
5
+
1 MW
10 mF
V– INPUT
Figure 10. Positive Voltage Conversion
Voltage Splitting
parallel, the output impedance is much lower than in the
standard circuits, and higher currents can be drawn from the
device. By using this circuit, and then the circuit of Figure
5, +15V can be converted (via +7.5V and –7.5V) to a
nominal –15V, though with rather high series resistance
(~250W).
The same bidirectional characteristics used in Figure 10
can also be used to split a higher supply in half, as shown in
Figure 11. The combined load will be evenly shared between
the two sides. Once again, a high value resistor to the LV pin
ensures start–up. Because the switches share the load in
50 mF
RL1
V
+ *2 V
OUT
V)
8
1
–
50 mF +
–
RL2
V+
+
2
100 kW 100 kW
50 mF
MC7660
7
3
6
4
5
1 MW
+
–
V–
Figure 11. Splitting a Supply in Half
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MC7660
TYPICAL PERFORMANCE CHARACTERISTICS
12
100
SUPPLY VOLTAGE (VOLTS)
98
POWER CONVERSION
EFFICIENCY (%)
10
8
6
SUPPLY VOLTAGE RANGE
4
2
IOUT = 1 mA
96
94
92
90
IOUT = 15 mA
88
86
84
TA = +25°C
V+ = +5 V
82
80
0
–55
–25
0
25
50
75
TEMPERATURE (°C)
100
125
100
10 k
TA = +25°C
1k
100
10
0
1
5
2
3
4
6
SUPPLY VOLTAGE (VOLTS)
7
8
350
IOUT = 1 mA
300
250
200
150
V+ = +2 V
100
V+ = +5 V
50
0
–55
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (Hz)
10 k
TA = +25°C
V+ = +5 V
1k
100
10
10
100
1000
OSCILLATOR CAPACITANCE (pF)
–25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 15. Output Source Resistance
versus Temperature
Figure 14. Output Source Resistance versus
Supply Voltage
1
10 k
Figure 13. Power Conversion Efficiency
versus Oscillator Frequency
OUTPUT SOURCE RESISTANCE ( W )
OUTPUT SOURCE RESISTANCE ( W )
Figure 12. Operating Voltage versus
Temperature
1k
OSCILLATOR FREQUENCY (Hz)
20
V+ = +5 V
18
16
14
12
10
8
6
10 k
–55
Figure 16. Frequency of Oscillation versus
Oscillator Capacitance
–25
0
25
50
75
TEMPERATURE (°C)
100
Figure 17. Unloaded Oscillator Frequency
versus Temperature
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7
125
MC7660
0
5
–1
4
OUTPUT VOLTAGE (VOLTS)
OUTPUT VOLTAGE (VOLTS)
TYPICAL CHARACTERISTICS (Cont.)
–2
–3
–4
–5
–6
–7
TA = +25°C
LV OPEN
–8
–9
–10
0
10
20
80
30 40 50
60 70
OUTPUT CURRENT (mA)
90
TA = +25°C
V+ = +5 V
3
2
1
0
–1
–2
–3
SLOPE 55 W
–4
–5
100
0
10
20
90
18
16
TA = +25°C
V+ = +2 V
60
14
12
50
10
40
8
30
6
20
4
10
0
2
0
0
1.5
3.0
4.5
6.0
LOAD CURRENT (mA)
7.5
9.0
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
TA = +25°C
V+ = +5 V
20
10
0
0
10
20
30
40
LOAD CURRENT (mA)
OUTPUT VOLTAGE (VOLTS)
TA = +25°C
V+ = +2 V
0
–1
SLOPE 150 W
–2
1
2
20
10
0
50
60
Figure 21. Supply Current and Power
Conversion Efficiency versus Load Current
2
0
80
100
Figure 20. Supply Current and Power
Conversion Efficiency versus Load Current
1
70
3
4
5
6
LOAD CURRENT (mA)
7
8
Figure 22. Output Voltage versus Load Current
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SUPPLY CURRENT (mA)
80
POWER CONVERSION EFFICIENCY (%)
100
70
30
40
50
60
LOAD CURRENT (mA)
Figure 19. Output Voltage versus
Load Current
SUPPLY CURRENT (mA)
POWER CONVERSION EFFICIENCY (%)
Figure 18. Output Voltage versus
Output Current
20
MC7660
PACKAGE DIMENSIONS
8–Pin SOIC
PLASTIC PACKAGE
CASE 751–06
ISSUE T
D
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
B
e
X 45 _
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
q
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9
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
MC7660
Notes
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MC7660
Notes
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MC7660
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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MC7660/D
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