Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 DAC8812 Dual, Serial-Input 16-Bit Multiplying Digital-to-Analog Converter 1 • • • 1 • • • • • • • • • 2 • • • Features 3 Description Relative Accuracy: 1 LSB Max Differential Nonlinearity: 1 LSB Max 2-mA Full-Scale Current ±20%, With VREF = ±10 V 0.5-μs Settling Time Midscale or Zero-Scale Reset Separate 4Q Multiplying Reference Inputs Reference Bandwidth: 10 MHz Reference Dynamics: –105-dB THD SPI™-Compatible 3-Wire Interface: 50 MHz Double Buffered Registers to Enable Simultaneous Multichannel Update Internal Power-On Reset Industry-Standard Pin Configuration The DAC8812 is a dual, 16-bit, current-output digitalto-analog converter (DAC) designed to operate from a single 2.7-V to 5.5-V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier. A double-buffered, serial data interface offers highspeed, 3-wire, SPI and microcontroller compatible inputs using serial data in (SDI), clock (CLK), and a chip-select (CS). A common level-sensitive load DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to zero at system turnon. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to half-scale code when MSB = 1. Applications The DAC8812 is available in a TSSOP-16 package. Automatic Test Equipment Instrumentation Digitally Controlled Calibration Device Information(1) PART NUMBER PACKAGE DAC8812 TSSOP (16) BODY SIZE (NOM) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Space Space Space Functional Block Diagram VREFA B D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 SDI RFBA 16 Input Register R DAC A Register R DAC A IOUTA AGNDA RFBB Input Register R DAC B Register R DAC B IOUTB AGNDB CLK CS EN DAC A B Decode DGND Power-On Reset RS MSB LDAC 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 4 4 4 4 5 6 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics.......................................... Timing Requirements ................................................ Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 13 8.4 Device Functional Modes........................................ 15 9 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 9.2 Typical Application ................................................. 18 10 Power Supply Recommendations ..................... 19 11 Layout................................................................... 20 11.1 Layout Guidelines ................................................. 20 11.2 Layout Example .................................................... 21 12 Device and Documentation Support ................. 22 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (November 2015) to Revision D • Page Changed the DAC8812 Timing Diagram image to show the setup and hold time with respect to rising edge .................... 7 Changes from Revision B (February 2007) to Revision C Page • Added ESD Ratings table, Timing Requirements and Switching Characteristics tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................................................................................................................................................................. 1 • Replaced Package/Ordering Information table with Device Comparison table...................................................................... 3 • Added I/O column to Pin Functions table ............................................................................................................................... 3 2 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 5 Device Comparison Table DEVICE MAXIMUM RELATIVE ACCURACY (LSB) DAC8812C ±1 DAC8812B ±2 6 Pin Configuration and Functions PW Package 16-Pin TSSOP Top View RFBA 1 16 CLK VREFA 2 15 LDAC IOUTA 3 14 MSB AGNDA 4 13 VDD AGNDB 5 12 DGND IOUTB 6 11 CS VREFB 7 10 RS RFBB 8 9 SDI Pin Functions PIN NO. NAME I/O DESCRIPTION 1 RFBA I Establish voltage output for DAC A by connecting to external amplifier output. 2 VREFA I DAC A reference voltage input pin. Establishes DAC A full-scale output voltage. Can be tied to VDD pin. 3 IOUTA O DAC A current output 4 AGNDA — DAC A analog ground 5 AGNDB — DAC B analog ground 6 IOUTB O DAC B current output 7 VREFB I DAC B reference voltage input pin. Establishes DAC B full-scale output voltage. Can be tied to VDD pin. 8 RFBB I Establish voltage output for DAC B by connecting to external amplifier output. 9 SDI I Serial data input; data loads directly into the shift register. 10 RS I Reset pin; active-low input. Input registers and DAC registers are set to all 0s or midscale. Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812. 11 CS I Chip-select; active-low input. Disables shift register loading when high. Transfers serial register data to input register when CS goes high. Does not affect LDAC operation. 12 DGND 14 MSB I MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or VDD. 13 VDD I Positive power-supply input. Specified range of operation 2.7 V to 5.5 V. 15 LDAC I Load DAC register strobe; level-sensitive active-low. Transfers all input register data to the DAC registers. Asynchronous active-low input. See Table 2 for operation. 16 CLK I Clock input. Positive edge clocks data into shift register. — Digital ground Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 3 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted) (1) VDD to GND MIN MAX UNIT –0.3 7 V VREFx, RFBx to GND –18 18 V Digital logic inputs to GND –0.3 VDD + 0.3 V IOUTx to GND –0.3 VDD + 0.3 V AGNDx to DGND –0.3 0.3 V Input current to any pin except supplies –50 50 mA (150°C – TA) / RθJA W Package power dissipation Maximum junction temperature (TJmax) 150 °C Operating temperature –40 85 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±4000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage to GND 2.7 5.5 V TA Operating ambient temperature –40 125 °C 7.4 Thermal Information DAC8812 THERMAL METRIC (1) PW (TSSOP) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 100.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.8 °C/W RθJB Junction-to-board thermal resistance 46.8 °C/W ψJT Junction-to-top characterization parameter 2 °C/W ψJB Junction-to-board characterization parameter 46 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com 7.5 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 Electrical Characteristics VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (1) Resolution INL Relative accuracy DNL Differential nonlinearity IOUTx Output leakage current GFSE Full-scale gain error TCVFS Full-scale temperature coefficient (2) RFBX Feedback resistor REFERENCE INPUT 16 DAC8812B ±2 DAC8812C ±1 ±1 Data = 0000h, TA = 25°C 10 Data = 0000h, TA = TA max 20 Data = FFFFh ±0.75 VDD = 5 V LSB LSB nA mV 1 ppm/°C 5 kΩ (2) VREFx VREFx range RREFx Input resistance –15 4 Input resistance match CREFx ±4 Bits 5 15 V 6 kΩ 1% Input capacitance 5 pF ANALOG OUTPUT (2) IOUTx Output current Data = FFFFh COUTx Output capacitance Code-dependent 1.6 2.5 mA 50 pF LOGIC INPUTS (2) VIL Input low voltage VIH Input high voltage IIL Input leakage current CIL Input capacitance (1) (2) VDD = 2.7 V 0.6 VDD = 5 V 0.8 VDD = 2.7 V 2.1 VDD = 5 V 2.4 V V 1 μA 10 pF All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter amplifier. The DAC8812 RFB pin is tied to the amplifier output. Typical values represent average readings measured at 25°C. These parameters are not subject to production testing. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 5 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY CHARACTERISTICS VDD RANGE Power supply range 5.5 V Logic inputs = 0 V, VDD = 4.5 V to 5.5 V 2.7 2 5 μA Logic inputs = 0 V, VDD = 2.7 V to 3.6 V 1 2.5 μA 0.0275 mW IDD Positive supply current PDISS Power dissipation Logic inputs = 0 V PSS Power supply sensitivity ΔVDD = ±5% AC CHARACTERISTICS (2) ts 0.006% (3) Output voltage settling time To ±0.1% of full-scale, Data = 0000h to FFFFh to 0000h 0.3 To ±0.0015% of full-scale, Data = 0000h to FFFFh to 0000h 0.5 µs QG DAC glitch impulse VREFx = 10 V, data = 7FFFh to 8000h to 7FFFh 5 nV-s BW –3 dB Reference multiplying BW VREFx = 100 mVRMS, data = FFFFh, CFB = 3 pF 10 MHz Feedthrough error Data = 0000h, VREFx = 100 mVRMS, f = 100 kHz –70 dB Crosstalk error Data = 0000h, VREFB = 100 mVRMS, Adjacent channel, f = 100 kHz –100 dB QD Digital feedthrough CS = 1 and fCLK = 1 MHz THD Total harmonic distortion VREF = 5 VPP, data = FFFFh, f = 1 kHz en Output spot noise voltage f = 1 kHz, BW = 1 Hz (3) 1 nV-s –105 dB 12 nV/√Hz All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier. 7.6 Timing Requirements See Figure 1 MIN NOM MAX UNIT INTERFACE TIMING (1) tCH Clock duration, high 10 ns tCL Clock duration, low 10 ns tCSS CS to clock setup 0 ns tCSH Clock to CS hold 10 ns tLDAC Load DAC pulse duration 20 ns tDS Data setup 10 ns tDH Data hold 10 ns tLDS Load setup 5 ns tLDH Load hold 25 ns (1) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 7.7 Switching Characteristics over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERFACE TIMING tPD 6 Clock to SDO propagation delay 2 Submit Documentation Feedback 20 ns Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 A1 SDI A0 DB15 DB1 DB0 tDS tDH CLK 1 16 tCL tCH tCSH tCSS CS tLDH tLDS LDAC tLDAC Figure 1. DAC8812 Timing Diagram Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 7 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com 7.8 Typical Characteristics 7.8.1 Channel A—5 V At TA = 25°C, VDD = 5 V, unless otherwise noted 1.0 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 2. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = -40°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 3. Differential Nonlinearity vs Digital Input Code TA = -40°C 0.8 INL (LSB) 0.2 -0.4 -1.0 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 4. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = +85°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 5. Differential Nonlinearity vs Digital Input Code TA = +85°C 0.8 INL (LSB) TA = +25°C 0.8 DNL (LSB) INL (LSB) 1.0 TA = +25°C 0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 6. Integral Nonlinearity vs Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 7. Differential Nonlinearity vs Digital Input Code Space Space Space 8 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 7.8.2 Channel B—5 V At TA = 25°C, VDD = 5 V, unless otherwise noted 1.0 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 8. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = -40°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 9. Differential Nonlinearity vs Digital Input Code TA = -40°C 0.8 INL (LSB) 0.2 -0.4 -1.0 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 10. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = +85°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 11. Differential Nonlinearity vs Digital Input Code TA = +85°C 0.8 INL (LSB) TA = +25°C 0.8 DNL (LSB) INL (LSB) 1.0 TA = +25°C 0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 12. Integral Nonlinearity vs Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 13. Differential Nonlinearity vs Digital Input Code Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 9 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com Channel B—5 V (continued) At TA = 25°C, VDD = 5 V, unless otherwise noted 180 160 VDD = +5.0V 120 100 80 60 40 VDD = +2.7V 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0x0000 1 00 1k 10k 10 0k 1M 10M 100 M Bandwidth (H z ) Logic Input Voltage (V) Figure 15. Reference Multiplying Bandwidth Code: 7FFFh to 8000h Output Voltage (5V/div) Figure 14. Supply Current vs Logic Input Voltage Output Voltage (50mV/div) 0xFFFF 0x8000 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 Attenuation (dB) Supply Current, IDD (mA) 140 6 0 −6 − 12 − 18 − 24 − 30 − 36 − 42 − 48 − 54 − 60 − 66 − 72 − 78 − 84 − 90 − 96 − 102 − 108 − 114 10 Voltage Output Settling Trigger Pulse LDAC Pulse Time (0.2ms/div) Time (0.1ms/div) Figure 16. DAC Glitch Figure 17. DAC Settling Time Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space Space 10 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 7.8.3 Channel A—2.7 V At TA = 25°C, VDD = 2.7 V, unless otherwise noted 1.0 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 18. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = -40°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 19. Differential Nonlinearity vs Digital Input Code TA = -40°C 0.8 INL (LSB) 0.2 -0.4 -1.0 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 20. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = +85°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 21. Differential Nonlinearity vs Digital Input Code TA = +85°C 0.8 INL (LSB) TA = +25°C 0.8 DNL (LSB) INL (LSB) 1.0 TA = +25°C 0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 22. Integral Nonlinearity vs Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 23. Differential Nonlinearity vs Digital Input Code Space Space Space Space Space Space Space Space Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 11 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com 7.8.4 Channel B—2.7 V At TA = 25°C, VDD = 2.7 V, unless otherwise noted 1.0 0.6 0.6 0.4 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8 -1.0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 24. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = -40°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 25. Differential Nonlinearity vs Digital Input Code TA = -40°C 0.8 INL (LSB) 0 -0.2 -0.6 0 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 0 Figure 26. Integral Nonlinearity vs Digital Input Code 1.0 1.0 TA = +85°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 27. Differential Nonlinearity vs Digital Input Code TA = +85°C 0.8 INL (LSB) 0.2 -0.4 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 28. Integral Nonlinearity vs Digital Input Code 12 TA = +25°C 0.8 DNL (LSB) INL (LSB) 1.0 TA = +25°C 0.8 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 29. Differential Nonlinearity vs Digital Input Code Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 8 Detailed Description 8.1 Overview The DAC8812 contains two 16-bit, current-output, digital-to-analog converters (DACs). Each DAC has its own independent multiplying reference input. The DAC8812 uses a 3-wire, SPI-compatible serial data interface, with a configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC strobe enables two channel simultaneous updates for hardware synchronized output voltage changes. 8.2 Functional Block Diagram VREFA B D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 SDI RFBA 16 Input Register DAC A Register R IOUTA DAC A R AGNDA RFBB Input Register DAC B Register R DAC B R IOUTB AGNDB CLK EN CS DAC A B Decode Power-On Reset DGND RS MSB LDAC 8.3 Feature Description 8.3.1 Digital-to-Analog Converters The DAC8812 contains two current-steering R-2R ladder DACs. Figure 30 shows a typical equivalent DAC. Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin is connected to the output of the external amplifier. The IOUTX pin is connected to the inverting input of the external amplifier. The AGNDX pin should be Kelvin-connected to the load point in the circuit requiring the full 16-bit accuracy. VDD R R R VREFX RFBX 2R 2R 2R R 5 kW S2 S1 IOUTX AGNDX DGND Digital interface connections omitted for clarity. Switches S1 and S2 are closed, VDD must be powered. Figure 30. Typical Equivalent DAC Channel Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 13 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) The DAC is designed to operate with both negative or positive reference voltages. The VDD power pin is only used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users are attempting to measure the value of RFB, power must be applied to VDD in order to achieve continuity. The DAC output voltage is determined by VREF and the digital data (D) according to Equation 1: D VOUT = VREF ´ 65 536 (1) Note that the output polarity is opposite of the VREF polarity for dc reference voltages. The DAC is also designed to accommodate ac reference input signals. The DAC8812 accommodates input reference voltages in the range of –15 V to 15 V. The reference voltage inputs exhibit a constant nominal input resistance of 5 kΩ, ±20%. On the other hand, DAC outputs IOUTA and B are code-dependent and produce various output resistances and capacitances. The choice of external amplifier should take into account the variation in impedance generated by the DAC8812 on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor, CFB (4 pF to 20 pF typical), may be needed to provide a critically damped output response for step changes in reference input voltages. Figure 15 shows the gain vs frequency performance at various attenuation settings using a 3 pF external feedback capacitor connected across the IOUTX and RFBX pins. In order to maintain good analog performance, power-supply bypassing of 0.01 μF, in parallel with 1 μF, is recommended. Under these conditions, clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is best to derive the DAC8812 5-V supply from the system analog supply voltages (do not use the digital 5-V supply); see Figure 31. 15 V 2R 5V + Analog Power Supply R VDD R R R RFBX VREFX 2R 2R 2R R 5 kW 15 V S2 S1 IOUTX VCC VOUT A1 + AGNDX VEE Load DGND DGND Digital interface connections omitted for clarity. Switches S1 and S2 are closed, VDD must be powered. Figure 31. Recommended Kelvin-Sensed Hookup 14 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 VREF A B CS EN VDD CLK SDI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 RFBB 16 DAC A Register R Input Register R DAC A IOUTA AGNDA RFBB DAC B Register R Input Register R DAC B IOUTB AGNDB DAC A B Set MSB Decode Set MSB Poweron Reset DGND MSB LDAC RS Figure 32. System-Level Digital Interfacing 8.3.2 Power-On Reset When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the zero-code state or half-scale, depending on the MSB pin voltage. The VDD power supply should have a smooth positive ramp without drooping, in order to have consistent results, especially in the region of VDD = 1.5 V to 2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place. 8.3.2.1 ESD Protection Circuits All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and VDD as shown in Figure 33. VDD DIGITAL INPUTS 250 W DGND Figure 33. Equivalent ESD Protection Circuits 8.4 Device Functional Modes 8.4.1 Serial Data Interface The DAC8812 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8812 is clocked into the serial input register in an 18-bit data-word format. MSB bits are loaded first. Table 1 defines the 18 data-word bits for the DAC8812. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 15 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com Device Functional Modes (continued) Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the Interface Timing specifications of the Electrical Characteristics. Data can only be clocked in while the CS chip select pin is active low. For the DAC8812, only the last 18 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state. Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the DAC8812. Keeping the CS line low between the first, second, and third byte transfers will result in a successful serial register update. Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target DAC register, determined by the decoding of address bits A1 and A0. For the DAC8812, Table 1, Table 2, Table 3, and Figure 1 define the characteristics of the software serial interface. Table 1. Serial Input Register Data Format, Data Loaded MSB First (1) Bit B17 (MSB) B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Data A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (1) Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to logic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D15-D0) to the decoded DACinput-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8812 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 2. Control Logic Truth Table (1) CS CLK LDAC RS MSB H X H H X No effect Latched Latched L L H H X No effect Latched Latched L ↑+ H H X Shift register data advanced one bit Latched Latched L H H H X No effect Latched Latched ↑+ L H H X No effect Selected DAC updated with current SR contents Latched H X L H X No effect Latched Transparent H X H H X No effect Latched Latched H X ↑+ H X No effect Latched Latched H X H L 0 No effect Latched data = 0000h Latched data = 0000h H X H L H No effect Latched data = 8000h Latched data = 8000h (1) SERIAL SHIFT REGISTER INPUT REGISTER DAC REGISTER ↑+ = Positive logic transition; X = Don't care Table 3. Address Decode 16 A1 A0 0 0 DAC DECODE None 0 1 DAC A 1 0 DAC B 1 1 DAC A and DAC B Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 Figure 34 shows the equivalent logic interface for the key digital control pins for the DAC8812. To Input Register Address Decoder CS A B EN CLK Shift Register SDI Figure 34. DAC8812 Equivalent Logic Interface Two additional pins, RS and MSB, provide hardware control over the preset function and DAC register loading. If these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1). Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 17 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information This design features one channel of the DAC8812 followed by a four-quadrant circuit for multiplying DACs. The circuit conditions the current output of an MDAC into a symmetrical bipolar voltage. The design uses an op amp in a transimpedance configuration to convert the MDAC current into a voltage, followed by an additional amplifier in a summing configuration to apply an offset voltage. 9.2 Typical Application Transimpedance Stage Gain and Offset Stage RG2 VREF REFIN RFB IOUT RG1 + MDAC RFB2 A1 VDAC VOUT + A2 Figure 35. Four-Quadrant Multiplying Application Circuit 9.2.1 Design Requirements Using a multiplying DAC requires a transimpedance stage using an amplifier with minimal input offset voltage. The tolerance of the external resistors varies depending on the goals of the application, but for optimal performance with the DAC8812 the tolerance should be 0.1 % for all of the external resistors. The summing stage amplifier also requires low input-offset voltage and enough slew rate for the output range desired. 9.2.2 Detailed Design Procedure The first stage of the design converts the current output of the MDAC (IOUT) to a voltage (VOUT) using an amplifier in a transimpedance configuration. A typical MDAC features an on-chip feedback resistor sized appropriately to match the ratio of the resistor values used in the DAC R-2R ladder. This resistor is available using the input shown in Figure 35 called RFB on the MDAC. The MDAC reference and the output of the transimpedance stage are then connected to the inverting input of the amplifier in the summing stage to produce the output that is defined by Equation 2. æ 2 FB2 VREF ´ Code ö æ R FB2 ö VOUT (Code ) = ç V ´ ÷ ç ´ ÷ REF ç R G1 ÷ ç R G2 ÷ 2 bits è ø è ø (2) 9.2.3 Application Curves Figure 36 shows the output voltage vs code of this design, and Figure 37 shows the output error vs code. Notice that the error gets worse as the output code increases because the contribution of the DAC gain error increases with code. 18 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 Typical Application (continued) 10 0.014 8 0.012 Output Error (%FSR) Output Voltage (V) 6 4 2 0 -2 -4 0.01 0.008 0.006 0.004 -6 0.002 -8 -10 0 0 8192 16384 24576 32768 40960 49152 57344 65536 Input Code (Decimal) D001 0 Figure 36. Input Code vs Output Voltage 8192 16384 24576 32768 40960 49152 57344 65536 Input Code (Decimal) D002 Figure 37. Input Code vs Output Error 10 Power Supply Recommendations This device can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD should be well-regulated and low-noise. In order to further minimize noise from the power supplies, a strong recommendation is to include a 100-pF to 1-nF capacitor and a 0.1-μF to 1-μF bypass capacitor very close to the VDD pin. The current consumption of the VDD pin, the short-circuit current limit, and the load current for these devices are listed in the Electrical Characteristics table. Choose a power supply for these devices to meet the aforementioned current requirements. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 19 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com 11 Layout 11.1 Layout Guidelines A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8812 offers single-supply operation, and is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. This device has three ground pins: two for analog ground (AGNDA and AGNDB) and one for digital ground (DGND), which are pinned out on opposite sides of the device. Ideally, the analog grounds would be connected directly to an analog ground plane, and similarly the digital ground connected to a digital ground plane. These planes would be separated until they were connected at the power-entry point of the system. The power applied to VDD should be well-regulated and low-noise. Switching power supplies and dc-dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. VDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until the analog and digital supplies are connected at the power-entry point. In addition, adding both a 100-pF to 1-nF capacitor and a 0.1-μF to 1-μF bypass capacitor is strongly recommended. In some situations, additional bypassing may be required, such as a 100-μF electrolytic capacitor or even a pi filter made up of inductors and capacitors – all designed essentially to provide low-pass filtering for the supply and remove the high-frequency noise. The compensation capacitors shown on the layout in Figure 38 are not required for normal operation of the DAC. However, overshoot of the amplifier output voltage on large code changes is possible. This can be mitigated by using a compensation capacitor between the IOUTx and RFBx nodes, as shown implemented here. Performance of the DAC8812 can be compromised by grounding and PCB lead trace resistance. The 16-bit DAC8812 with a 10-V full-scale range has an LSB size of 153 µV. The ladder and associated reference and analog ground currents for a given channel can be as high as 2 mA. With this 2-mA current level, a series wiring and connector resistance of only 76 mΩ causes 1 LSB of voltage drop. The preferred PCB layout for the DAC8812 is to have all AGNDx pins connected directly to an analog ground plane at the device. The noninverting input for the transimpedance amplifier of each channel should also either connect directly to the analog ground plane or have an individual sense trace back to the AGNDx pin connection. The feedback resistor trace to the transimpedance amplifier should also be kept short and have low resistance in order to prevent IR drops from contributing to gain error. Therefore, it is important to place the transimpedance amplifier as close to the DAC as possible. This attention to wiring and placement ensures the optimal performance of the DAC8812. 20 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 DAC8812 www.ti.com SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 11.2 Layout Example Digital Interface AGNDA MSB IOUTA VREFA RFBA Amplifier Compensation Capacitor VSS AGNDB VDD CLK GND IOUTB DGND LDAC Compensation Capacitor IOUT A VREFB VOUT B DAC GND CS Power Capacitors RFBB IOUT A RS VOUT A SDI VCC REF B REF A Digital Interface Figure 38. DAC8812 Layout Example Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 21 DAC8812 SBAS349D – AUGUST 2005 – REVISED JANUARY 2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation DAC8811 16-Bit, Serial Input Multiplying Digital-to-Analog Converter, SLAS411 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. 22 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: DAC8812 PACKAGE OPTION ADDENDUM www.ti.com 21-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC8812IBPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 DAC8812IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 DAC8812IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 DAC8812IBPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 DAC8812ICPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 DAC8812ICPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 DAC8812ICPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 DAC8812ICPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC8812 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 21-Jan-2016 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8812IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC8812ICPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8812IBPWR TSSOP PW 16 2000 367.0 367.0 38.0 DAC8812ICPWR TSSOP PW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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