Renesas M5M5W816TP-55HI 8388608-bit (524288-word by 16-bit) cmos static ram Datasheet

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FEATURES
DESCRIPTION
The M5M5W816TP is a f amily of low v oltage 8-Mbit static
RAMs organized as 524288-words by 16-bit, f abricated by
Mitsubishi's high-perf ormance 0.18µm CMOS technology .
The M5M5W816TP is suitable f or memory applications
where a simple interf acing , battery operating and battery
backup are the important design objectiv es.
The M5M5W816TP is packaged in a 44pin thin small
outline mount dev ice, with the outline of 400mil TSOP
TY PE(II). It giv es the best solution f or a compaction of
mounting area as well as f lexibility of wiring pattern of
printed circuit boards.
Version,
Operating
temperature
I-version
-40~+85°C
Power
Supply
Part name
M5M5W816TP -55HI
M5M5W816TP -70HI
M5M5W816TP -85HI
2.7~3.6V
Access time
max.
55ns
70ns
85ns
-
Single 2.7~3.6V power supply
Small stand-by current: 0.1µA (2.0V, ty p.)
No clocks, No ref resh
Data retention supply v oltage =2.0V
All inputs and outputs are TTL compatible.
Easy memory expansion by S#, BC1# and BC2#
Common Data I/O
Three-state outputs: OR-tie capability
OE# prev ents data contention in the I/O bus
Process technology : 0.18µm CMOS
Package: 44pin 400mil TSOP TYPE(II)
Activ e
current
Icc1
25°C 40°C 25°C 40°C 70°C 85°C *(3.0V ty p.)
Stand-by c urrent
Ratings (max. @3.6V)
* Typ. (@ 3.0V)
0.5
1.0
5.0
8.0
20
40
30mA
(10MHz)
5mA
(1MHz)
* Typical parameter indicates the value for the
center of distribution, and not 100% tested.
PIN CONFIGURATION
A4
A3
A2
A1
A0
S#
DQ1
DQ2
DQ3
DQ4
V CC
11
34
A5
A6
A7
OE#
BC2#
BC1#
DQ16
DQ15
DQ14
DQ13
GND
GND
DQ5
DQ6
DQ7
DQ8
W#
A15
A14
A13
A12
A16
12
33
V CC
13
32
DQ12
DQ11
DQ10
DQ9
A18
A8
A9
A10
A11
A17
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
Pin
A0 ~ A18
Function
Address input
DQ1 ~ DQ16 Data input / output
44Pin 400mil TSOP
S#
W#
OE#
Chip select input
BC1#
Lower By te (DQ1 ~ 8)
BC2#
Upper By te (DQ9 ~ 16)
Vcc
Power supply
GND
Ground supply
Write control input
Output enable input
Outline: 44P3W
1
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W816TP is organized as 524288-words by 16bit. These dev ices operate on a single +2.7~3.6V power
supply , and are directly TTL compatible to both input and
output. Its f ully s t atic circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S# , W# and
OE#. Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S#. The address(A0~A18) must be set up bef ore the
write cy c le and must be stable during the entire cy c le.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S# are in an activ e state(S#=L).
When setting BC1# at the high lev el and other pins are
in an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-by t e
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a
non-selectable mode.
When setting BC1# and BC2# at a high lev el or S# at a high
lev el, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with other
chips and memory expansion by BC1#, BC2# and S#.
The power supply c urrent is reduced as low as 0.1µA(25°C,
ty pical), and the memory data can be held at +2.0V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S#
H
X
L
L
L
L
L
L
L
L
L
BC1# BC2#
X
H
L
L
L
H
H
H
L
L
L
X
H
H
H
H
L
L
L
L
L
L
W# OE#
X
X
L
H
H
L
H
H
L
H
H
X
X
X
L
H
X
L
H
X
L
H
Mode
Non selection
Non selection
Write
Read
Write
Read
Write
Read
Icc
DQ1~8 DQ9~16
High-Z
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
High-Z Standby
High-Z Standby
High-Z Activ e
High-Z Activ e
High-Z Activ e
Din
Activ e
Dout
Activ e
High-Z Activ e
Din
Activ e
Dout
Activ e
High-Z Activ e
(note) "H" and "L" in this table mean VIH or VIL , respectiv ely .
"X" in this table should be "H"or "L".
BLOCK DIAGRAM
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
524288 WORDS
x 16 BITS
A 17
-
DQ
9
A 18
CLOCK
GENERATOR
S#
DQ
16
BC1#
BC2#
Vcc
W#
GND
OE#
2
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc
VI
VO
Pd
Power dissipation
Ta
Operating
temperature
T stg
Conditions
Supply v oltage
Input v oltage
With respect to GND
Output v oltage
With respect to GND
-0.3 * ~ +4.6
-0.3 * ~ Vcc + 0.3 (max. 4.6V)
0 ~ Vcc
700
With respect to GND
Ta=
Units
Ratings
25°C
Storage temperature
V
mW
- 40 ~ +85
°C
- 65 ~ +150
°C
* -3.0V in case of AC (Pulse width < 30ns)
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Symbol
V IH
V IL
V OH
V OL
II
IO
Parameter
Limits
Conditions
Min
Max
High-lev el input v oltage
2.2
Vcc+0.2V
Low-lev el input v oltage
-0.2 *
2.4
0.6
High-lev el output v oltage I OH= - 0.5mA
Low-lev el output v oltage I OL=2mA
Input leakage current
Output leakage current
f = 10MHz
-
30
5
30
0.4
±1
±1
50
15
50
f = 1MHz
-
5
15
~ +25°C
0.5
5
~ +40°C
-
1.0
8
~ +70°C
-
-
20
~ +85°C
-
-
40
-
-
2
V I =0 ~ Vcc
BC1# and BC2#=VIH or S#=VIH or OE#=VIH, VI/O=0 ~ Vcc
Icc 1 Activ e supply c urrent
BC1# and BC2# < 0.2V, S# < 0.2V
other inputs < 0.2V or > Vcc-0.2V
Output - open (duty 100%)
f = 10MHz
Activ e supply c urrent
Icc 2
( AC,TTL lev el )
BC1# and BC2#=V IL , S#=V IL
other pins =V IH or V IL
Output - open (duty 100%)
(1) S# > Vcc - 0.2V,
other inputs = 0 ~ Vcc
( AC,MOS lev el )
Icc 3 Stand by s upply current
( AC,MOS lev el )
Icc 4
Ty p
Stand by s upply current
( AC,TTL lev el )
(2) BC1# and BC2# > Vcc - 0.2V
S# < 0.2V
other inputs = 0 ~ Vcc
f = 1MHz
BC1# and BC2# = VIH or S# = VIH
Other inputs= 0 ~ Vcc
Note 1: Direction for current flowing into IC is indicated as positive (no mark).
* -1.0V in case of AC (Pulse width
Units
V
µA
mA
µA
mA
< 30ns)
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
CAPACITANCE
Symbol
CI
CO
Parameter
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Conditions
Min
Input capacitance
V I =GND, VI =25mVrms, f =1MHz
Output capacitance
V O = GND,VO =25mVrms, f =1MHz
Limits
Ty p
Max
10
10
Units
pF
3
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
1TTL
2.7~3.6V
Input pulse
V IH=2.4V, V IL=0.4V
Input rise time and f all time 5ns
Supply v oltage
DQ
CL
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Ref erence lev el
V OH=V OL=1.50V
Output loads
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Limits
Parameter
Symbol
Min
t CR
t a(A)
t a(S)
t a(BC1)
t a(BC2)
t a(OE)
t dis (S)
t dis (BC1)
t dis (BC2)
t dis (OE)
t en(S)
t en(BC1,2)
t en(OE)
t V(A)
Read cy cle time
Address access time
Chip select 1 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S# high
Output disable time af t er BC1# high
Output disable time af t er BC2# high
Output disable time af t er OE# high
Output enable time af ter S# low
Output enable time af ter BC1#,BC2# low
Output enable time af ter OE# low
Data v alid time after address
85HI
70HI
55HI
Max
55
Min
Max
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
70
70
70
70
70
35
25
25
25
25
55
55
55
55
30
20
20
20
20
85
85
85
85
45
30
30
30
30
10
5
5
10
10
5
5
10
10
5
5
10
Min
Units
(3) WRITE CYCLE
Limits
Symbol
t CW
t w(W)
t su(A)
t su(A-WH)
t su(BC1)
t su(BC2)
t su(S)
t su(D)
t h(D)
t rec (W)
t dis (W)
t dis (OE)
t en(W)
t en(OE)
55HI
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W# low
Output disable time f rom OE# high
Output enable time f rom W# high
Output enable time f rom OE# low
Min
55
45
0
50
50
50
50
30
0
0
70HI
Max
Min
70
55
0
65
65
65
65
35
0
0
20
20
85HI
Max
Min
85
60
0
70
70
70
70
45
0
0
Units
Max
30
30
25
25
5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
t CR
A 0~18
t v (A)
t a(A)
t a(BC1) or t a(BC2)
BC1#,BC2#
(Note3)
t dis (BC1) or t dis (BC2)
(Note3)
t dis (S)
(Note3)
t dis (OE)
(Note3)
t a(S)
S#
(Note3)
t a (OE)
OE#
(Note3)
t en (OE)
W# = "H" lev el
t en (BC1)
t en (BC2)
t en (S)
DQ 1~16
Write cycle ( W# control mode )
VALID DATA
t CW
A 0~18
t su (BC1) or t su (BC2)
BC1#,BC2#
(Note3)
(Note3)
t su (S)
S#
(Note3)
(Note3)
OE#
t su (A)
t su (A-WH)
t w (W)
t rec (W)
t dis (W)
W#
t en (OE)
t en (W)
t dis (OE)
DQ 1~16
DATA IN
STABLE
t su (D)
t h (D)
5
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
t CW
A 0~18
t su (A)
t su (BC1) or
t su (BC2)
t rec (W)
BC1#,BC2#
S#
(Note3)
(Note3)
(Note5)
W#
(Note4)
(Note3)
(Note3)
t su (D)
DQ 1~16
t h (D)
DATA IN
STABLE
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S# low ov erlaps BC1# and/or BC2# low and W# low.
Note 5: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of
S#, the outputs are maintained in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S# control mode)
t CW
A 0~18
BC1#, BC2#
(Note3)
t su (A)
t su (S)
t rec (W)
(Note3)
S#
(Note5)
W#
(Note4)
(Note3)
DQ 1~16
t su (D)
t h (D)
(Note3)
DATA IN
STABLE
7
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Symbol
Vcc
Parameter
Test conditions
Min
Byte control input BC1# & BC2#
Icc
(PD)
2.2
V
Vcc(PD)
2.0V < Vcc(PD) < 2.2V
Power down
supply c urrent
V
Vcc(PD)
2.2V < Vcc(PD)
Chip select input S#
Vcc=2.0V
~ +25°C
1.5
~ +40°C
-
0.1
(1) S# > Vcc - 0.2V,
0.2
3
~ +70°C
-
-
15
~ +85°C
-
-
30
other inputs = 0 ~ Vcc
(2) BC1# and BC2# > Vcc - 0.2V
S# < 0.2V
other inputs = 0 ~ Vcc
Units
V
2.2
2.2V < Vcc(PD)
2.0V < Vcc(PD) < 2.2V
V I (S)
Max
2.0
(PD) Power down supply voltage
V I (BC)
Limits
Ty p
µA
Note 7: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 2.0V, and not 100% tested.
(2) TIMING REQUIREMENTS
Symbol
t su (PD)
t rec (PD)
Limits
Parameter
Test conditions
Min
Ty p
0
5
Power down set up time
Power down recov ery t ime
Max
Units
ns
ms
(3) TIMING DIAGRAM
BC# control mode
On the BC# control mode, the lev el of S# must be f ixed at S# > Vcc-0.2V or S# < 0.2V.
Vcc
t su (PD)
2.7V
2.7V
t rec (PD)
2.2V
2.2V
BC1#
BC2#
BC1# , BC2# > Vcc-0.2V
S# control mode
Vcc
t su (PD)
2.7V
2.7V
2.2V
2.2V
S#
t rec (PD)
S# > Vcc-0.2V
8
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric
Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs,
algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs
and algorithms represents information on products at the time of publication of these materials, and
are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or
an authorized Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various
means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from
the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake. Please
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
Similar pages