AD ADuM1441ARQZ Micropower quad-channel digital isolator Datasheet

Micropower
Quad-Channel Digital Isolators
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
FEATURES
FUNCTIONAL BLOCK DIAGRAM
General-purpose, low power multichannel isolation
1 MHz, low power peripheral interface (SPI)
4 mA to 20 mA loop process controls
GENERAL DESCRIPTION
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM14471 are micropower, 4-channel digital
isolators based on the Analog Devices, Inc., iCoupler® technology.
Combining high speed, complementary metal oxide semiconductor
(CMOS) and monolithic air core transformer technologies,
these isolation components provide outstanding performance
characteristics superior to the alternatives, such as optocoupler
devices. As shown in Figure 2, in standard operating mode,
when ENx = 0 (internal refresh enabled), the current per channel is
less than 10 µA. When ENx = 1 (internal refresh disabled), the
current per channel drops to less than 1 µA.
ADuM144x
QSOP
16 VDD2
15 GND2
VIA 3
ENCODE
DECODE
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VIC/VOC 5
ENCODE
DECODE
12 VOC/VIC
VID/VOD 6
ENCODE
DECODE
11 VOD/VID
EN1 7
10 EN2
GND1 8
9 GND2
Figure 1.
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 family of quad 2.5 kV digital isolation
devices are packaged in a small 16-lead QSOP, freeing almost
70% of board space compared to isolators packages in wide
body SOIC packages. The devices withstand high isolation
voltages and meet regulatory requirements, such as UL and
CSA standards (pending). In addition to the space savings, the
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 operate with supplies as low as 2.25 V.
Despite the low power consumption, all models of the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
provide low, pulse width distortion at <8 ns. In addition, every
model has an input glitch filter to protect against extraneous
noise disturbances.
1000
100
10
ENx = 0
ENx = 1
1
0.1
0.1
1
10
100
1000
10000
DATA RATE (Mbps)
11845-001
APPLICATIONS
VDD1 1
GND1 2
CURRENT PER CHANNE L (µA)
Ultralow power operation
3.3 V operation (typical)
5.6 µA per channel quiescent current, refresh enabled
0.3 µA per channel quiescent current, refresh disabled
148 µA/Mbps per channel typical dynamic current
2.5 V operation (typical)
3.1 µA per channel quiescent current, refresh enabled
0.1 µA per channel quiescent current, refresh disabled
117 µA/Mbps per channel typical dynamic current
Small, 16-lead QSOP
Bidirectional communication
Up to 2 Mbps data rate (NRZ)
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL 1577 Component Recognition Program (pending)
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A (pending)
VDE Certificate of Conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 VPEAK
11845-002
Data Sheet
Figure 2. Typical Total Supply Current per Channel (VDDx = 3.3 V)
1
Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending.
Rev. 0
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ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 10
Applications ....................................................................................... 1
Absolute Maximum Ratings ......................................................... 11
General Description ......................................................................... 1
ESD Caution................................................................................ 11
Functional Block Diagram .............................................................. 1
Pin Configurations and Function Descriptions ......................... 12
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 15
Specifications..................................................................................... 3
Applications Information .............................................................. 18
Electrical Characteristics—3.3 V Operation ............................ 3
Printed Circuit Board (PCB) Layout ....................................... 18
Electrical Characteristics—2.5 V Operation ............................ 5
Propagation Delay-Related Parameters................................... 18
Electrical Characteristics—VDD1 = 3.3 V, VDD2 = 2.5 V
Operation....................................................................................... 7
DC Correctness ............................................................................ 18
Electrical Characteristics—VDD1 = 2.5 V, VDD2 = 3.3 V
Operation....................................................................................... 8
Power Consumption .................................................................. 20
Package Characteristics ............................................................... 9
Regulatory Information ............................................................... 9
Insulation and Safety-Related Specifications ............................ 9
Magnetic Field Immunity............................................................. 19
Insulation Lifetime ..................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics ............................................................................ 10
REVISION HISTORY
10/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
Table 1.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Change vs. Temperature
Minimum Pulse Width
Pulse-Width Distortion
Propagation Delay Skew 1
Channel Matching
Codirectional
Opposing Direction
1
Symbol
Min
tPHL, tPLH
PW
PWD
tPSK
Typ
80
200
Max
Unit
Test Conditions/Comments
2
180
Within pulse-width distortion (PWD) limit
50% input to 50% output
8
10
Mbps
ns
ps/°C
ns
ns
ns
10
15
ns
ns
500
tPSKCD
tPSKOD
Within PWD limit
|tPLH − tPHL|
tPSK is the magnitude of the worst-case difference in tPHL and tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 2.
Parameter
SUPPLY CURRENT
ADuM1440/ADuM1445
ADuM1441/ADuM1446
ADuM1442/ADuM1447
Symbol
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
Min
Typ
Max
Unit
732
492
672
552
612
612
1000
750
900
900
900
900
µA
µA
µA
µA
µA
µA
Rev. 0 | Page 3 of 24
Test Conditions/Comments
2 Mbps, no load
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Data Sheet
Table 3. For All Models
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Output Voltages
Logic High
Logic Low
Input Current per Channel
Input Switching Thresholds
Positive Threshold Voltage
Negative Going Threshold
Input Hysteresis
Undervoltage Lockout, VDD1 or VDD2
Supply Current per Channel
Quiescent Current
Input Supply
Output Supply
Input (Refresh Off )
Output (Refresh Off )
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise Time/Fall Time
Common-Mode Transient Immunity 2
Refresh Rate
1
2
Symbol
Min
VIH
VIL
0.7 VDDx 1
VOH
VDDx1 − 0.1
VDDx1 − 0.4
VOL
II
−1
Typ
3.0
2.8
0.0
0.2
+0.01
Max
Unit
0.3 VDDx1
V
V
0.1
0.4
+1
V
V
V
V
µA
VT+
VT−
ΔVT
UVLO
1.8
1.2
0.6
1.5
IDDI (Q)
IDDO (Q)
IDDI (Q)
IDDO (Q)
4.8
0.8
0.12
0.13
IDDI (D)
IDDO (D)
88
60
µA/Mbps
µA/Mbps
2
40
ns
kV/µs
14
kbps
tR/tF
|CM|
fr
25
Test Conditions/Comments
IOUTx = −20 µA, VIx = VIxH
IOUTx = −4 mA, VIx = VIxH
IOUTx = 20 µA, VIx = VIxL
IOUTx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDx1
V
V
V
V
10
3.3
µA
µA
µA
µA
ENX low
ENX low
ENX high
ENX high
10% to 90%
VIx = VDDx1, VCM = 1000 V,
transient magnitude = 800 V
VDDx = VDD1 or VDD2.
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
Rev. 0 | Page 4 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operating range of 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
Table 4.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Change vs. Temperature
Pulse-Width Distortion
Minimum Pulse Width
Propagation Delay Skew 1
Channel Matching
Codirectional
Opposing Direction
1
Symbol
Min
tPHL, tPLH
PWD
PW
tPSK
Typ
112
280
Max
Unit
Test Conditions/Comments
2
180
Within PWD limit
50% input to 50% output
10
Mbps
ns
ps/°C
ns
ns
ns
10
30
ns
ns
12
500
tPSKCD
tPSKOD
|tPLH − tPHL|
Within PWD limit
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 5.
Parameter
SUPPLY CURRENT
ADuM1440/ADuM1445
ADuM1441/ADuM1446
ADuM1442/ADuM1447
Symbol
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
Min
Typ
Max
Unit
623
337
552
409
480
480
800
500
750
750
750
750
µA
µA
µA
µA
µA
µA
Rev. 0 | Page 5 of 24
Test Conditions/Comments
2 Mbps, no load
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Data Sheet
Table 6. For All Models
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Output Voltages
Logic High
Logic Low
Input Current per Channel
Input Switching Thresholds
Positive Threshold Voltage
Negative Going Threshold
Input Hysteresis
Undervoltage Lockout, VDD1 or VDD2
Supply Current per Channel
Quiescent Current
Input Supply
Output Supply
Input (Refresh Off )
Output (Refresh Off )
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise Time/Fall Time
Common-Mode Transient Immunity 2
Refresh Rate
1
2
Symbol
Min
VIH
VIL
0.7 VDDx 1
VOH
VDDx1 − 0.1
VDDx1 − 0.4
VOL
II
−1
Typ
2.5
2.35
0.0
0.1
+0.01
Max
Unit
0.3 VDDx1
V
V
0.1
0.4
+1
V
V
V
V
µA
VT+
VT−
ΔVT
UVLO
1.5
1.0
0.5
1.5
IDDI (Q)
IDDO (Q)
IDDI (Q)
IDDO (Q)
2.6
0.5
0.05
0.05
IDDI (D)
IDDO (D)
76
41
µA/Mbps
µA/Mbps
2
40
ns
kV/µs
14
kbps
tR/tF
|CM|
fr
25
Test Conditions/Comments
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDx1
V
V
V
V
3.3
1.8
µA
µA
µA
µA
ENX low
ENX low
ENX high
ENX high
10% to 90%
VIx = VDDx1, VCM = 1000 V,
transient magnitude = 800 V
VDDx = VDD1 or VDD2.
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
Rev. 0 | Page 6 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
ELECTRICAL CHARACTERISTICS—VDD1 = 3.3 V, VDD2 = 2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and.VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire
recommended operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 3 for Side 1 and see Table 6 for Side 2.
Table 7.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Side 1 to Side 2
Side 2 to Side 1
Change vs. Temperature
Pulse-Width Distortion
Pulse Width
Propagation Delay Skew 1
Channel Matching
Codirectional
Opposing Direction
1
Symbol
Min
tPHL, tPLH
tPHL, tPLH
PWD
PW
tPSK
Typ
84
120
280
Max
Unit
Test Conditions/Comments
2
Mbps
Within PWD limit
180
180
50% input to 50% output
50% input to 50% output
10
ns
ns
ps/°C
ns
ns
ns
10
60
ns
ns
12
500
tPSKCD
tPSKOD
|tPLH − tPHL|
Within PWD limit
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 8.
Parameter
SUPPLY CURRENT
ADuM1440/ADuM1445
ADuM1441/ADuM1446
ADuM1442/ADuM1447
Symbol
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
Min
Typ
Max
Unit
732
337
672
409
612
480
1000
750
900
750
900
750
µA
µA
µA
µA
µA
µA
Rev. 0 | Page 7 of 24
Test Conditions/Comments
2 Mbps, no load
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Data Sheet
ELECTRICAL CHARACTERISTICS—VDD1 = 2.5 V, VDD2 = 3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 2.5, and VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire
recommended operating range of 2.25 V ≤ VDD1 ≤ 2.75 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 6 for Side 1 and see Table 3 for Side 2.
Table 9.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Side 1 to Side 2
Side 2 to Side 1
Change vs. Temperature
Pulse-Width Distortion
Pulse Width
Propagation Delay Skew 1
Channel Matching
Codirectional
Opposing Direction
1
Symbol
Min
tPHL, tPLH
tPHL, tPLH
PWD
PW
tPSK
Typ
120
84
200
Max
Unit
Test Conditions/Comments
2
Mbps
Within PWD limit
180
180
50% input to 50% output
50% input to 50% output
10
ns
ns
ps/°C
ns
ns
ns
10
60
ns
ns
12
500
tPSKCD
tPSKOD
|tPLH − tPHL|
Within PWD limit
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 10.
Parameter
SUPPLY CURRENT
ADuM1440/ADuM1445
ADuM1441/ADuM1446
ADuM1442/ADuM1447
Symbol
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
Min
Typ
Max
Unit
623
492
552
552
480
612
1000
750
750
900
750
900
µA
µA
µA
µA
µA
µA
Rev. 0 | Page 8 of 24
Test Conditions/Comments
2 Mbps, no load
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
ENX = 0 V, VIH = VDD, VIL = 0 V
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
PACKAGE CHARACTERISTICS
Table 11.
Parameter
Resistance (Input-to-Output) 1
Capacitance (Input-to-Output)1
Input Capacitance 2
IC Junction-to-Ambient Thermal Resistance
1
2
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1013
2
4.0
76
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 are pending approval by the organizations listed in Table 12.
See Table 17 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross-isolation waveforms
and insulation levels.
Table 12.
UL (Pending)
Recognized under UL 1577 Component
Recognition Program 1
Single protection, 2500 V rms isolation
voltage
File E214100
1
2
CSA (Pending)
Approved under CSA Component Acceptance
Notice #5A
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms (566 VPEAK) maximum
working voltage
File 205078
VDE (Pending)
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Reinforced insulation, 565 VPEAK
File 2471900-4880-0001
In accordance with UL 1577, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test voltage of
≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
In accordance with DIN V VDE V 0884-10, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test
voltage ≥1050 VPEAK for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 13.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Tracking and Air Gap (Creepage and
Clearance)
Minimum Clearance in the Plane of the Printed Circuit Board
(PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
Symbol
L(I02)
Value
2500
3.1
Unit
V rms
mm min
L(I01)
3.8
mm min
CTI
0.017
>400
II
mm min
V
Rev. 0 | Page 9 of 24
Test Conditions/Comments
1-minute duration
Measured from input terminals to output
terminals, shortest distance path along body
Measured from input terminals to output
terminals, shortest distance through air, line
of sight, in the PCB mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.
Table 14.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Test Conditions/Comments
VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
Case Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 3)
VIO = 500 V
1.8
Symbol
Characteristic
Unit
VIORM
Vpd(m)
I to IV
I to III
I to II
40/105/21
2
560
1050
VPEAK
VPEAK
Vpd(m)
840
VPEAK
Vpd(m)
672
VPEAK
VIOTM
VIOSM
3500
4000
VPEAK
VPEAK
TS
IS1
RS
150
1.64
>109
°C
W
Ω
RECOMMENDED OPERATING CONDITIONS
SAFE LIMITING POWER (W)
1.6
Table 15.
1.4
Parameter
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times
1.2
1.0
0.8
1
0.6
50
100
150
AMBIENT TEMPERATURE (°C)
200
11845-003
0.2
0
Value
−40°C to +125°C
2.25 V to 3.6 V
1.0 ms
All voltages are relative to their respective grounds. See the DC Correctness
section for information on immunity to external magnetic fields.
0.4
0
Symbol
TA
VDD1, VDD2
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. 0 | Page 10 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
ABSOLUTE MAXIMUM RATINGS
Table 17. Maximum Continuous Working Voltage1
TA = 25°C, unless otherwise noted.
Parameter
AC Voltage
60 Hz Bipolar Waveform
60 Hz Unipolar Waveform
Basic Insulation
DC Voltage
Basic Insulation
Table 16.
Parameter
Supply Voltages (VDD1, VDD2)
Input Voltages (VIA, VIB )
Output Voltages (VOA, VOB)
Average Output Current per Pin1
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients2
Storage Temperature (TST) Range
Ambient Operating Temperature
(TA) Range
1
2
Rating
−0.5 V to +3.6 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDD2 + 0.5 V
−10 mA to +10 mA
−10 mA to +10 mA
−100 kV/µs to +100 kV/µs
−65°C to +150°C
−40°C to +125°C
1
Value
Constraint
565 VPEAK
50-year minimum lifetime
975 VPEAK
50-year minimum lifetime
975 VPEAK
50-year minimum lifetime
Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
See Figure 3 for maximum safety power values for various temperatures.
Refers to common-mode transients across the insulation barrier. Common-mode
transients exceeding the absolute maximum ratings can cause latch-up or
permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 18. Truth Table (Positive Logic) for all Models
VIx Input 1, 2
H
L
H
L
L
VDDI State 3
Powered
Powered
Powered
Powered
Unpowered
VDDO State 4
Powered
Powered
Powered
Powered
Powered
ENx Input1
L
L
H
H
L
VOx Output1
H
L
H
L5
Default
L
Unpowered
Powered
H
Hold
X
Powered
Unpowered
X
Z
Description
Normal operation; data is high and refresh is enabled.
Normal operation; data is low and refresh is enabled.
Output is high, and refresh is disabled.
Output is low, and refresh is disabled.
Input unpowered. Outputs are in the default state, high for
ADuM1440, ADuM1441, and ADuM1442, and low
ADuM1445, ADuM1446, and ADuM1447. Outputs return to
input state within 150 µs of VDDI power restoration. See the
pin function descriptions (Table 19 through Table 21) for
more details.
Input unpowered. Outputs are the last state before input
power is shut down.
Output unpowered. Output pins are in high impedance
state. Outputs return to input state within 34 µs of VDDO power
restoration. See the pin function descriptions (Table 19
through Table 21) for more details.
H = high, L = low, X = don’t care, and Z = high impedance.
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).
4
VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
5
Low input must follow a falling edge; otherwise, it can be in the default low state.
1
2
3
Rev. 0 | Page 11 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16 VDD2
VDD1 1
15 GND22
GND11 2
VIA 3
VIB 4
ADuM1440/
ADuM1445
VIC 5
TOP VIEW
(Not to Scale)
14 VOA
13 VOB
12 VOC
VID 6
11 VOD
EN1 7
10 EN2
GND11 8
9
GND22
TO GND1 IS RECOMMENDED.
2PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING
BOTH TO GND2 IS RECOMMENDED.
11845-004
1PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
Figure 4. ADuM1440/ADuM1445 Pin Configuration
Table 19. ADuM1440/ADuM1445 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1
2, 8
GND1
3
4
5
6
7
VIA
VIB
VIC
VID
EN1
9, 15
GND2
10
EN2
11
12
13
14
16
VOD
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range
between VDD1 (Pin 1) and GND1 (Pin 2).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and watchdog functionality for
Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables refresh and watchdog functionality for
lowest power operation, see the Applications Information section for a detailed description of this mode. EN1 and
EN2 must be set to the same logic state.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and watchdog functionality
for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2 disables refresh and watchdog functionality
for lowest power operation, see the Applications Information section for a detailed description of this mode. EN1
and EN2 must be set to the same logic state.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range
between VDD2 (Pin 16) and GND2 (Pin 15).
Rev. 0 | Page 12 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
16 VDD2
VDD1 1
15 GND22
GND11 2
VIA 3
VIB 4
ADuM1441/
ADuM1446
VIC 5
TOP VIEW
(Not to Scale)
14 VOA
13 VOB
12 VOC
VOD 6
11 VID
EN1 7
10 EN2
GND11 8
9
GND22
TO GND1 IS RECOMMENDED.
2PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING
BOTH TO GND2 IS RECOMMENDED.
11845-005
1PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
Figure 5. ADuM1441/ADuM1446 Pin Configuration
Table 20. ADuM1441/ADuM1446 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1
2, 8
GND1
3
4
5
6
7
VIA
VIB
VIC
VOD
EN1
9, 15
GND2
10
EN2
11
12
13
14
16
VID
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range
between VDD1 (Pin 1) and GND1 (Pin 2).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and watchdog functionality for
Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables refresh and watchdog functionality for
lowest power operation, see the Applications Information section for a detailed description of this mode. EN1 and
EN2 must be set to the same logic state.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and watchdog functionality
for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2 disables refresh and watchdog functionality
for lowest power operation, see the Applications Information section for a detailed description of this mode. EN1
and EN2 must be set to the same logic state.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range
between VDD2 (Pin 16) and GND2 (Pin 15).
Rev. 0 | Page 13 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
16 VDD2
VDD1 1
15 GND22
GND11 2
VIA 3
Data Sheet
VIB 4
ADuM1442/
ADuM1447
VOC 5
TOP VIEW
(Not to Scale)
14 VOA
13 VOB
12 VIC
VOD 6
11 VID
EN1 7
10 EN2
GND11 8
9
GND22
TO GND1 IS RECOMMENDED.
2PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING
BOTH TO GND2 IS RECOMMENDED.
11845-006
1PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
Figure 6. ADuM1442/ADuM1447 Pin Configuration
Table 21. ADuM1442/ADuM1447 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1
2, 8
GND1
3
4
5
6
7
VIA
VIB
VOC
VOD
EN1
9, 15
GND2
10
EN2
11
12
13
14
16
VID
VIC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range
between VDD1 (Pin 1) and GND1 (Pin 2).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and watchdog functionality for
Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables refresh and watchdog functionality for
lowest power operation, see the Applications Information section for detailed description of this mode. EN1 and EN2
must be set to the same logic state.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and watchdog functionality
for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2 disables refresh and watchdog functionality
for lowest power operation, see the Applications Information section for a detailed description of this mode. EN1
and EN2 must be set to the same logic state.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01 µF to 0.1 µF range
between VDD2 (Pin 16) and GND2 (Pin 15).
Rev. 0 | Page 14 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
TYPICAL PERFORMANCE CHARACTERISTICS
15
10
250
5
0
200
0
20
40
150
100
50
VDDx INPUT CURRENT
0
500
1500
1000
2000
DATA RATE (kbps)
0
20
40
60
40
20
VDDx OUTPUT CURRENT
1000
500
0
1500
2000
Figure 10. Current Consumption per Output vs. Data Rate for 3.3 V,
ENx = Low Operation
CURRENT CONSUMPTION PER INPUT (µA)
160
80
4
2
60
0
50
0
20
40
40
30
20
10
0
500
1000
1500
2000
DATA RATE (kbps)
1.0
120
0.5
100
0
0
5
10
80
60
40
20
VDDx INPUT CURRENT
VDDx OUTPUT CURRENT
0
140
0
0
500
1500
1000
2000
DATA RATE (kbps)
Figure 8. Current Consumption per Output vs. Data Rate for 2.5 V,
ENx = Low Operation
11845-011
70
11845-008
CURRENT CONSUMPTION PER OUTPUT (µA)
0
80
DATA RATE (kbps)
90
Figure 11. Current Consumption per Input vs. Data Rate for 2.5 V,
ENx = High Operation
400
350
CURRENT CONSUMPTION PER OUTPUT (µA)
90
15
10
300
5
0
250
0
20
40
200
150
100
50
VDDx INPUT CURRENT
0
500
1000
1500
2000
DATA RATE (kbps)
11845-009
CURRENT CONSUMPTION PER INPUT (µA)
2
100
0
Figure 7. Current Consumption per Input vs. Data Rate for 2.5 V,
ENx = Low Operation
0
4
Figure 9. Current Consumption per Input vs. Data Rate for 3.3 V,
ENx = Low Operation
80
1.0
70
0.5
60
0
0
5
10
50
40
30
20
10
VDDx OUTPUT CURRENT
0
0
500
1000
DATA RATE (kbps)
1500
2000
11845-012
0
120
11845-010
300
CURRENT CONSUMPTION PER OUTPUT (µA)
140
11845-007
CURRENT CONSUMPTION PER INPUT (µA)
350
Figure 12. Current Consumption per Output vs. Data Rate for 2.5 V,
ENx = High Operation
Rev. 0 | Page 15 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
300
FALLING
RISING
180
1.0
250
160
0.5
0
120
0
5
IDDx CURRENT (µA)
140
10
100
80
60
40
150
100
50
500
1000
1500
2000
DATA RATE (kbps)
0
Figure 13. Current Consumption per Input vs. Data Rate for VDDX = 3.3 V,
ENx = High Operation
0.5
1.0
1.5
2.0
2.5
Figure 16. IDDx Current per Input vs. Data Input Voltage for VDDx = 2.5 V
10
9
0.5
100
0
0
5
10
80
60
40
20
8
7
6
5
4
3
2
1
OUTPUT
INPUT
VDDx OUTPUT CURRENT
500
1000
1500
2000
DATA RATE (kbps)
11845-014
0
0
–40
–20
0
20
40
60
80
100
Figure 14. Current Consumption per Output vs. Data Rate for VDDx = 3.3 V,
ENx = High Operation
140
Figure 17. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 2.5 V, Data Rate = 100 kbps
600
10
FALLING
RISING
9
SUPPLY CURRENT/CHANNEL (µA)
500
400
300
200
100
8
7
6
5
4
3
2
1
0
1
2
3
DATA INPUT VOLTAGE (V)
4
0
–40
11845-015
0
120
TEMPERATURE (°C)
11845-117
SUPPLY CURRENT/CHANNEL (µA)
1.0
120
0
3.0
DATA INPUT VOLTAGE (V)
140
IDDx CURRENT (µA)
0
11845-016
VDDx INPUT CURRENT
0
OUTPUT
INPUT
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 15. Typical IDDx Current per Input vs.
Data Input Voltage for VDDx = 3.3 V
100
120
140
11845-118
0
CURRENT CONSUMPTION PER OUTPUT (µA)
200
20
11845-013
CURRENT CONSUMPTION PER INPUT (µA)
200
Data Sheet
Figure 18. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 3.3 V, Data Rate = 100 kbps
Rev. 0 | Page 16 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
100
120
100
GLITCH FILTER WIDTH (ns)
80
70
60
50
40
30
80
60
40
20
0
–40
OUTPUT
INPUT
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
0
2.0
2.5
3.0
3.5
4.0
TRANSMITTER VDDx (V)
Figure 19. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 2.5 V, Data Rate = 1000 kbps
11845-017
20
10
11845-119
SUPPLY CURRENT/CHANNEL (µA)
90
Figure 22. Typical Glitch Filter Operation Threshold
100
140
120
80
REFRESH PERIOD (µs)
SUPPLY CURRENT/CHANNEL (µA)
90
70
60
50
40
30
100
80
60
40
20
20
VDDx = 2.5V
VDDx = 3.3V
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
0
–40
11845-120
0
–40
OUTPUT
INPUT
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 20. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 3.3 V, Data Rate = 1000 kbps
Figure 23. Typical Refresh Period vs. Temperature for
3.3 V and 2.5 V Operation
140
120
120
100
REFRESH PERIOD (µs)
100
80
60
40
80
60
40
20
20
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
0
2.0
2.5
3.0
3.5
VDDx VOLTAGE (V)
Figure 24. Typical Refresh Period vs. VDDX Voltage
Figure 21. Typical Propagation Delay vs. Temperature for
VDDx = 3.3 V or VDDx = 2.5 V
Rev. 0 | Page 17 of 24
4.0
11845-123
0
–40
VDDx = 2.5V
VDDx = 3.3V
11845-121
PROPAGATION DELAY (ns)
–20
11845-122
10
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Data Sheet
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at both input and output supply pins:
VDD1 and VDD2 (see Figure 25). Choose a capacitor value between
0.01 µF and 0.1 µF. The total lead length between both ends of the
capacitor and the input power supply pin must not exceed 20 mm.
VDD2
GND2
VOA
VOB
VOC/VIC
VOD/VID
EN2
GND2
VDD1
GND1
VIA
VIB
VIC/VOC
VID/VOD
EN1
GND1
11845-018
Using proper PCB design choices, the ADuM1440/ADuM1441/
ADuM1442/ADuM1445/ADuM1446/ADuM1447 readily meets
CISPR 22 Class A (and FCC Class A) emissions standards, as
well as the more stringent CISPR 22 Class B (and FCC Class B)
standards in an unshielded environment. Refer to the AN-1109
Application Note, Recommendations for Control of Radiated
Emissions with iCoupler Devices, for PCB-related EMI mitigation
techniques, including board layout and stack-up issues.
PROPAGATION DELAY-RELATED PARAMETERS
These products are optimized for minimum power consumption
by eliminating as many internal bias currents as possible. As a
result, the timing characteristics are more sensitive to operating
voltage and temperature than in standard iCoupler products.
Refer to Figure 17 through Figure 24 for the expected variation
of these parameters.
Propagation delay is a parameter defined as the time it takes a
logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition can
differ from the propagation delay time of a low-to-high transition.
50%
tPHL
11845-019
OUTPUT (VOx)
In edge-based systems, it is critical to reject pulses that are too
short to be handled by the encode and decode circuits. The
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 implement a glitch filter to reject pulses less than
the glitch filter operating threshold. This threshold depends on
the operating voltage, as shown in Figure 22. Any pulse shorter
than the glitch filter does not pass to the output. When the refresh
circuit is enabled, pulses that match the glitch filter width have a
small probability of being stretched until corrected by the next
refresh cycle, or by the next valid data through that channel. To
avoid issues with pulse stretching, observe the minimum pulse
width requirements listed in the switching specifications.
Standard Operating Mode
For applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
tPLH
Propagation delay skew is the maximum amount of time the
propagation delay differs between multiple ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
components operating under the same conditions.
DC CORRECTNESS
Figure 25. Recommended Printed Circuit Board Layout
INPUT (VIx)
Channel-to-channel matching is the maximum amount of time
the propagation delay differs between channels within a single
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 component.
50%
Figure 26. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. When
refresh and watchdog functions are enabled by pulling EN1 and
EN2 low, in the absence of logic transitions at the input for more
than ~140 µs, a periodic set of refresh pulses indicative of the
correct input state is sent to ensure dc correctness at the output. If
the decoder receives no internal pulses of more than approximately
200 µs, the input side is assumed unpowered or nonfunctional,
in which case, the isolator watchdog circuit forces the output to
a default state. The default state is either high as in the ADuM1440,
ADuM1441, and ADuM1442 versions, or low as in the ADuM1445,
ADuM1446, and ADuM1447 versions.
Low Power Operating Mode
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 allow the refresh and watchdog
functions to be disabled by pulling EN1 and EN2 to logic high for
the lowest power consumption. These control pins must be set to
the same value on each side of the component for proper operation.
In this mode, the current consumption of the chip drops to the
microamp range. However, be careful when using this mode
because dc correctness is no longer guaranteed at startup. For
example, if the following sequence of events occurs:
1.
2.
3.
Rev. 0 | Page 18 of 24
Power is applied to Side 1
A high level is asserted on the VIA input
Power is applied to Side 2
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
To achieve optimum power consumption with the
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447, always drive the inputs as near to VDDx or GNDx levels
as possible. Figure 15 and Figure 16 illustrate the shoot through
leakage of an input; therefore, whereas the logic thresholds of the
input are standard CMOS levels, optimum power performance
is achieved when the input logic levels are driven within 0.5 V
of either VDDx or GNDx levels.
MAGNETIC FIELD IMMUNITY
The magnetic field immunity of the ADuM1440/ADuM1441/
ADuM1442/ADuM1445/ADuM1446/ADuM1447 is determined
by the changing magnetic field, which induces a voltage in the
receiving coil of the transformer large enough to either falsely
set or reset the decoder. The following analysis defines the
conditions under which this can occur. The 3.3 V operating
condition of the ADuM1440/ADuM1441/ADuM1442/
ADuM1445/ADuM1446/ADuM1447 is examined because it
represents the most typical mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
100
10
1
0.1
0.01
0.001
1k
10k
10M
100k
1M
MAGNETIC FIELD FREQUENCY (Hz)
100M
11845-020
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 implement Schmitt trigger input
buffers so that the devices operate cleanly in low data rate or
noisy environments. Schmitt triggers allow a small amount of
shoot through current when their input voltage is not
approximate to either VDDx or GNDx levels. This is because the
two transistors are both slightly on when input voltages are in
the middle of the supply range. For many digital devices, this
leakage is not a large portion of the total supply current and
may not be noticed; however, in the ultralow power ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447,
this leakage can be larger than the total operating current of the
device and cannot be ignored.
1000
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurred during a transmitted pulse
(and was of the worst-case polarity), it would reduce the received
pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
transformers. Figure 28 shows these allowable current magnitudes
as a function of frequency for selected distances. As shown, the
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 are extremely immune and can be affected only by
extremely large currents operating at a high frequency very near
to the component. For the 1 MHz example noted previously, a
1.2 kA current would have to be placed 5 mm away from the
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 to affect the operation of the component.
1000
100
10
1
0.1
DISTANCE = 5mm
DISTANCE = 100mm
DISTANCE = 1m
0.01
Given the geometry of the receiving coil in the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
and an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
Rev. 0 | Page 19 of 24
1k
10k
10M
100k
1M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 28. Maximum Allowable Current for
Various Current-to-ADuM144x Spacings
100M
11845-021
Recommended Input Voltage for Low Power Operation
magnetic field at a given frequency can be calculated. The result
is shown in Figure 27.
MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss)
The high on VIA is not automatically transferred to the Side 2
VOA, and there can be a level mismatch that is not corrected until a
transition occurs at VIA. After power is stable on each side and a
transition occurs on the input of the channel, that channel’s input
and output state is correctly matched. This contingency can be
addressed in several ways, such as sending dummy data, or toggling
refresh on for a short period to force synchronization after turn on.
MAXIMUM ALLOWABLE CURRENT (kA)
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
The supply current at a given channel of the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
isolator is a function of the supply voltage, the data rate of the
channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q)
f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5 fr
For each output channel, the supply current is given by
f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
−3
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 7 through
Figure 14 show per channel supply currents as a function of
data rate for an unloaded output condition.
INSULATION LIFETIME
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 17 can be applied while maintaining the
50-year minimum lifetime provided the voltage conforms to
either the unipolar ac or dc voltage case. Treat any cross-insulation
voltage waveform that does not conform to Figure 30 or Figure 31
as a bipolar ac waveform, and limit its peak voltage to the 50-year
lifetime voltage value listed in Table 17.
Note that the voltage presented in Figure 30 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447.
RATED PEAK VOLTAGE
0V
Figure 29. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 30. Unipolar AC Waveform
RATED PEAK VOLTAGE
11845-024
IDDO = IDDO (Q)
The insulation lifetime of the ADuM1440/ADuM1441/
ADuM1442/ADuM1445/ADuM1446/ADuM1447 depends on
the voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 29, Figure 30, and Figure 31 illustrate these
different isolation voltage waveforms.
11845-022
POWER CONSUMPTION
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 17 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA approved working voltages.
In many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life, in some cases.
11845-023
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large enough to trigger the thresholds of
succeeding circuitry. Take care in the layout of such traces to
avoid this possibility.
Data Sheet
0V
Figure 31. DC Waveform
Rev. 0 | Page 20 of 24
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
OUTLINE DIMENSIONS
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
9
1
8
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.010 (0.25)
0.006 (0.15)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
COPLANARITY
0.004 (0.10)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
0.025 (0.64)
BSC
SEATING
PLANE
0.012 (0.30)
0.008 (0.20)
8°
0°
0.020 (0.51)
0.010 (0.25)
0.050 (1.27)
0.016 (0.41)
0.041 (1.04)
REF
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
01-28-2008-A
16
Figure 32. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
(Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model 1, 2
ADuM1440ARQZ
ADuM1441ARQZ
ADuM1442ARQZ
ADuM1445ARQZ
ADuM1446ARQZ
ADuM1447ARQZ
1
2
Number
of Inputs,
VDD1 Side
4
3
2
4
3
2
Number
of Inputs,
VDD2 Side
0
1
2
0
1
2
Maximum
Data Rate
(Mbps)
2
2
2
2
2
2
Default
Output
State
High
High
High
Low
Low
Low
Maximum
Propagation
Delay, 3.3 V (ns)
180
180
180
180
180
180
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
Tape and reel is available. The addition of the –RL7 suffix indicates that the product is shipped on 7” tape and reel.
Rev. 0 | Page 21 of 24
Package
Description
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Package
Option
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
NOTES
Rev. 0 | Page 22 of 24
Data Sheet
Data Sheet
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
NOTES
Rev. 0 | Page 23 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11845-0-10/13(0)
Rev. 0 | Page 24 of 24
Data Sheet
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