AD ADSP-21MSP58BST-104 Dsp microcomputer Datasheet

a
FEATURES
38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz
Crystal
ADSP-2100 Family Code and Function Compatible with
New Instruction Set Enhanced for Bit Manipulation
Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
2K 3 24 Words of On-Chip Program Memory RAM
2K 3 16 Words of On-Chip Data Memory RAM
4K 3 24 Words of On-Chip Program Memory ROM
(ADSP-21msp59 Only)
8-Bit Parallel Host Interface Port
Analog Interface Provides:
16-Bit Sigma-Delta ADC and DAC
Programmable Gain Stages
On-Chip Anti-Aliasing & Anti-Imaging Filters
8 kHz Sampling Frequency
65 dB ADC, SNR and THD
72 dB DAC, SNR and THD
425 mW Typical Power Dissipation @ 5.0 V @ 38 ns
<1 mW Powerdown Mode with 100 Cycle Recovery
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides:
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware, One Serial Port (SPORT0) has Automatic
Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (ADSP-21msp59 Only)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
100-Lead TQFP
DSP Microcomputers
ADSP-21msp58/59
FUNCTIONAL BLOCK DIAGRAM
POWERDOWN
CONTROL
LOGIC
MEMORY
ADSP-21msp59
DATA
ADDRESS
GENERATORS
DAG 1
PROGRAM
SEQUENCER
DAG 2
PROGRAM
MEMORY
4K x 24
(ROM)
ADSP-21msp58/59
PROGRAM
MEMORY
2K x 24
DATA
MEMORY
2K x 16
FLAG
ANALOG
INTERFACE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
TIMER
SHIFTER
SERIAL PORTS
ADSP-2100 BASE
ARCHITECTURE
SPORT 0
SPORT 1
HOST
INTERFACE
PORT
GENERAL DESCRIPTION
The ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Processors (MSProcessor® DSPs) are fully integrated, single-chip
DSPs complete with a high performance analog front end. The
ADSP-21msp58/59 Family is optimized for voice band applications such as Speech Compression, Speech Processing, Speech
Recognition, Text-to Speech, and Speech-to-Text conversion.
The ADSP-21msp58/59 combines the ADSP-2100 base architecture (three computation units, data address generators, and
program sequencer) with two serial ports, a host interface port,
an analog front end, a programmable timer, extensive interrupt
capability, and on-chip program and data memory.
The ADSP-21msp58 provides 2K words (24-bit) of program
RAM and 2K words (16-bit) of data memory. The ADSP21msp59 provides an additional 4K words (24-bit) of program
ROM. The ADSP-21msp58/59 integrates a high performance
analog codec based on a single chip, voice band codec, the
AD28msp02. Powerdown circuitry is also provided to meet the
low power needs of battery operated portable equipment. The
ADSP-21msp58/59 is available in a 100-pin TQFP package
(thin quad flat package).
In addition, the ADSP-21msp58/59 supports new instructions,
which include bit manipulations–bit set, bit clear, bit toggle,
bit test–new ALU constants, new multiplication instruction
(x squared), biased rounding, and global interrupt masking.
MSProcessor is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADSP-21msp58/59
DIGITAL ARCHITECTURE OVERVIEW
The two address buses (PMA, DMA) share a single external address bus, allowing memory to be expanded off chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space the external buses are being used for.
Figure 1 is an overall block diagram of the ADSP-21msp58/59.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs singlecycle multiply, multiply/add, and multiply/subtract operations.
The shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive exponent operations. The shifter
can be used to efficiently implement numeric format control including multiword floating-point representations.
Program memory can store both instructions and data, permitting the ADSP-21msp58/59 to fetch two operands in a single
cycle, one from program memory and one from data memory.
The ADSP-21msp58/59 can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation.
External devices can gain control of the processors’ buses with
the use of the bus request/grant signals (BR and BG). Bus grant
has two modes of operation. If GoMode is enabled in the MSTAT
register, instruction execution continues from internal memory.
If GoMode is disabled, the processor stops instruction execution
and waits for deassertion of BR.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21msp58/59 executes looped code with
zero overhead—no explicit jump instructions are required to
maintain the loop.
In addition to the address and data bus for external memory
connection, the ADSP-21msp58/59 has a host interface port
(HIP) for easy connection to a host processor. The HIP is made
up of 8 data/address pins and 10 control pins. The HIP is extremely flexible and provides a simple interface to a variety of
host processors. For example, the Motorola 68000 series, the
Intel 80C51 series, and the Analog Devices ADSP-2101 can be
easily connected to the HIP. The host processor can boot the
ADSP-21msp58/59 on-chip memory through the HIP.
Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four
modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for circular
buffers. The circular buffering feature is also used by the serial
ports for automatic data transfers to (and from) on-chip
memory.
The ADSP-21msp58/59 can respond to eleven interrupts. There
can be up to three external interrupts, configured as edge- or
level-sensitive, and seven internal interrupts generated by the
Timer, the Serial Ports (SPORTs), the HIP, the powerdown circuitry, and the analog interface. There is also a master RESET
signal.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of
operation. Each port can generate an internal programmable serial clock or accept an external serial clock.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
INSTRUCTION
REGISTER
PROGRAM
SRAM
2K x 24
PROGRAM
SEQUENCER
PROGRAM
ROM
4K x 24
(ADSP-21msp59)
14
PMA BUS
14
DMA BUS
24
PMD BUS
16
DMD BUS
1
FLAG
DATA
SRAM
2K x 16
BOOT
ADDRESS
GENERATOR
7
ADC, DAC
AND
FILTERS
14
EXTERNAL
ADDRESS
BUS
24
EXTERNAL
DATA
BUS
MUX
MUX
COMPANDING
CIRCUITRY
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
INPUT REGS
MAC
SHIFTER
OUTPUT REGS
16
OUTPUT REGS
CONTROL
LOGIC
TRANSMIT REG
TRANSMIT REG
RECEIVE REG
RECEIVE REG
SERIAL
PORT 0
SERIAL
PORT 1
5
5
R BUS
HIP
CONTROL
10
TIMER
HIP
REGISTER
POWER
DOWN
CONTROL
LOGIC
8
HIP
DATA
BUS
1
Figure 1. ADSP-21msp58/59 Block Diagram
–2–
REV. 0
ADSP-21msp58/59
seven wait states are automatically generated. This allows, for
example, a 38 ns ADSP-21msp58/59 to use a 250 ns EPROM
as external boot memory. Multiple programs can be selected
and loaded from the EPROM with no additional hardware. The
on-chip program memory can also be initialized through the
HIP.
Pin Descriptions
The ADSP-21msp58 and ADSP-21msp59 are available in a
100-lead TQFP package. Table I contains the pin descriptions.
Table I. ADSP-21msp58/59 Pin List
The ADSP-21msp58/59 features a general purpose flag output
whose state is controlled through software. You can use this
output to signal an event to an external device. In addition, the
data input and output pins on SPORT1 can be alternatively
configured as an input and an output flag.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
The ADSP-21msp58/59 instruction set provides flexible data
moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a
single processor cycle. The ADSP-21msp58/59 uses an algebraic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Serial Ports
The ADSP-21msp58/59 processors include two synchronous serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-21msp58/59
SPORTs. Refer to the ADSP-2100 Family User’s Manual for further details.
• SPORTs are bidirectional with a separate, double-buffered
transmit and receive section.
• SPORTs can use an external serial clock or generate their own
clock internally.
• SPORTs have independent framing for the transmit and
receive sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally generated. Frame sync signals are programmed to be active high or
low, with either of two pulse widths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORTs receive and transmit sections generate separate
interrupts when the SPORTs are ready to read or write new
data.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word (Autobuffering
Mode). An interrupt is generated after a complete data buffer
transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed
serial bit stream.
• SPORT1 can be reconfigured as two external interrupt inputs
(IRQ0 and IRQ1) and the Flag In and Flag Out signals (FI,
FO). The internally generated serial clock may still be used in
this configuration.
REV. 0
Pin
Group
Name
#
of
Input/
Pins Output Function
Digital Pins
Address
14
O
Data
24
I/O
RESET
IRQ2
BR
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN,
XTAL
1
1
1
1
1
1
1
1
1
1
I
I
I
O
O
O
O
O
O
I
2
I
CLKOUT
HACK
HSEL
BMODE
1
1
1
1
O
O
I
I
HMD0
1
I
HMD1
1
I
HRD/HRW
1
I
HWR/HDS
1
I
HD7–0/
HAD7–0
8
I/O
HA2/ALE
1
I
HA1–0/
(unused)
SPORT0
2
5
I
I/O
SPORT1
5
I/O
or
–3–
Address output for program,
data and boot memory spaces
Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
Processor reset input
External interrupt request #2
External bus request input
External bus grant output
External program memory select
External data memory select
Boot memory select
External memory read enable
External memory write enable
Memory map select
External clock or quartz crystal
input
Processor clock output
HIP acknowledge output
HIP select input
Boot mode select (0 = Standard
EPROM Booting, 1 = HIP
Booting)
Bus strobe select (0 = RD/WR,
1 = RW/DS)
HIP address/data mode select
(0 = Separate, 1 = Multiplexed)
HIP read strobe or read/write
select
HIP write strobe or host data
strobe select
HIP data or HIP data and
address
Host address 2 or address latch
enable
Host address 1 and 0 inputs
Serial port 0 pins (TFS0, RFS0,
DT0, DR0, SCLK0)
Serial port 1 pins (TFS1, RFS1,
DT1, DR1, SCLK1)
ADSP-21msp58/59
Pin
Group
Name
#
of
Input/
Pins Output Function
IRQ0 (RFS1)
IRQ1 (TFS1)
SCLK1
FI (DR1)
FO (DT1)
FL0
VDD
GND
PWD
Analog Pins
VINNORM
1
1
1
1
1
1
4
5
1
I
I
O
I
O
O
1
I
VINAUX
1
I
Decouple
1
I
VOUTP
1
O
VOUTN
1
O
VREF
REF_
FILTER
1
O
1
O
VCC
GNDA
1
2
I
Tying these pins to appropriate values configures the ADSP21msp58/59 for straight-wire interface to a variety of industrystandard microprocessors and microcomputers.
When the host processor writes an 8-bit value to the HIP, the
upper eight bits of the HIP registers are all zeros. For additional
information, refer to the ADSP-2100 Family User’s Manual,
Chapter 7, for information about 8-bit configuration.
External interrupt request #0
External interrupt request #1
Programmable clock output
Flag input pin
Flag output pin
General purpose flag output pin
Digital power supply pins
Ground pins
Powerdown pin
HIP Operation
The HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. The HIP
data registers are memory-mapped in the internal data memory
of the ADSP-21msp58/59. HIP transfers can be managed using
either interrupts or polling. These registers are shown in the section “ADSP-21msp58/59 Registers.” The two status registers
provide status information to both the ADSP-21msp58/59 and
the host processor. HSR7 contains a software reset bit that can
be set by the ADSP-21msp58/59 and the host.
Input terminal of the NORM
amplifier for the encoder section
(ADC)
Input terminal of the AUX
amplifier for the encoder section
(ADC)
Ground reference of the NORM
and AUX amplifiers for the
encoder section (ADC)
Noninverting output terminal of
the differential amplifier from
the decoder section (DAC)
Inverting output terminal of the
differential amplifier from the
decoder section (DAC)
Output voltage reference
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-21msp58/59 cycles.
The HIP generates an interrupt whenever an HDR register receives data from a host processor write. It also generates an interrupt when the host processor has performed a successful read
of any HDR. The read/write status of the HDRs is also stored in
the HSR registers.
The HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the HDR4 Write bit in
HMASK and the HIP Write interrupt enable bit in IMASK are
set.
Voltage reference external bypass filter node
Analog power supply
Analog ground
The HIP provides a second method of booting the ADSP21msp58/59 in which the host processor loads instructions into
the HIP. The ADSP-21msp58/59 automatically transfers the
data, in this case opcodes, to internal program memory. The
BMODE pin determines whether the ADSP-21msp58/59 boots
from the host processor through the HIP or from external
EPROM over the data bus.
Host Interface Port
The ADSP-21msp58/59 host interface port (HIP) is a parallel
I/O port that allows for an easy connection to a host processor.
Through the HIP, the ADSP-21msp58/59 can be used as a
memory-mapped peripheral to a host computer. The HIP can
be thought of as an area of dual-ported memory, or mailbox registers, that allows communication between the computational
core of the ADSP-21msp58/59 and the host computer.
Interrupts
The interrupt controller lets the processor respond to interrupts
and reset with a minimum of overhead. The ADSP-21msp58/59
provides up to three external interrupt input pins, IRQ0, IRQ1,
and IRQ2. IRQ2 is always available as a dedicated pin;
SPORT1 may be reconfigured for IRQ1 and IRQ0 and the flag.
The ADSP-21msp58/59 also supports internal interrupts from
the timer, the host interface port, the serial ports, the analog interface, and the powerdown control circuit. The interrupts are
internally prioritized and individually maskable (except for
powerdown and RESET). The input pins can be programmed
for either level- or edge-sensitivity. The priorities and vector addresses for the interrupts are shown in Table II; the interrupt
registers are shown in Figure 2.
The host interface port is completely asynchronous. The host
processor can write data into the HIP while the ADSP21msp58/59 is operating at full speed.
The HIP can be configured with the following pins:
• BMODE (when MMAP = 0) determines whether the ADSP21msp58/59 boots from the host processor (through the HIP)
or external EPROM (through the data bus).
• HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
• HMD1 selects separate address (3-bit) and data (8-bit) buses,
or a multiplexed 8-bit address/data bus with address latch
enable.
–4–
REV. 0
ADSP-21msp58/59
IMASK
ICNTL
4
3
2
1
0
0
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Analog Receive
Analog Transmit
1 = enable, 0 = disable
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
1 = edge
0 = level
Interrupt Nesting
1 = enable, 0 = disable
IFC
15 14 13 12 11 10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
INTERRUPT FORCE
INTERRUPT CLEAR
IRQ2
SPORT0 Transmit
Timer
SPORT1 Receive or IRQ0
SPORT0 Receive
Analog Transmit
SPORT1 Transmit or IRQ1
Analog Receive
Analog Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Analog Transmit
SPORT0 Receive
SPORT0 Transmit
IRQ2
1 = enable, 0 = disable
Figure 2. Interrupt Registers
The following instructions allow global enable or disable servicing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
Table II. Interrupt Priority & Interrupt Vector Addresses
Source of Interrupt
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Analog Interface Transmit
Analog Interface Receive
SPORT1 Transmit or (IRQ1)
SPORT1 Receive or (IRQ0)
Timer
Interrupt Vector
Address (Hex)
ENA INTS;
DIS INTS;
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupt servicing is enabled on processor reset.
System Interface
Figure 3 shows a basic system configuration with the ADSP21msp58/59, two serial devices, a host processor, a boot
EPROM, optional external program and data memories, and an
analog interface. Up to 15K words of data memory and 16K
words of program memory can be supported. Programmable
wait state generation allows the processor to interface easily to
slow memories. The ADSP-21msp58/59 also provides one external interrupt and two serial ports or three external interrupts
and one serial port.
Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected. The powerdown interrupt is non-maskable.
Clock Signals
The ADSP-21msp58/59 CLKIN input may be driven by a crystal or by a TTL-compatible external clock signal.
The interrupt control register, ICNTL, allows the external interrupts to be set as either edge- or level-sensitive. Interrupt service routines can either be nested (with higher priority interrupts
taking precedence) or be processed sequentially (with only one
interrupt service active at a time).
The CLKIN input may not be halted, changed in frequency
during operation, or operated at any frequency other the one
specified. Operating the ADSP-21msp58/59 at any other frequency changes the analog performance, which is not tested or
supported.
The interrupt force and clear register, IFC, is a write-only register used to force an interrupt or clear a pending edge-sensitive
interrupt.
If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stack is twelve
levels deep to allow interrupt nesting.
The ADSP-21msp58/59 uses an input clock with a frequency
equal to half the instruction rate; a 13 MHz input clock yields a
38.46 ns processor cycle (which is equivalent to 26 MHz). Normally, instructions are executed in a single processor cycle.
Register bit values shown in Figure 2 are the default bit values
after reset. If no values are shown, the bits are indeterminate at
reset. Reserved bits are shown in gray; these bits should always
be written with zeros.
REV. 0
All device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled. The
–5–
ADSP-21msp58/59
ANALOG
INPUT
ANALOG
OUTPUT
HIP CONTROL
CLOCK OR
CRYSTAL
HOST
PROCESSOR
HIP DATA/ADDR
1
2
3
4
4
CLKIN XTAL VCC GNDA
3
5
HOST
MODE
VDD GND
CLKOUT
7
HIP
SCLK
RFS
SERIAL
PORT 0
RESET
(OPTIONAL)
8
TFS
SERIAL DEVICE
DT
(OPTIONAL)
DR
IRQ2
ADSP-21msp58/59
BR
SCLK
BG
RFS OR IRQ0
MMAP
TFS OR IRQ1
SERIAL
PORT 1
FL0
PMS
RD
WR
ADDRESS
DATA DMS
14
SERIAL DEVICE
DT OR FO
(OPTIONAL)
DR OR FI
BMS
24
D 23-22
D 23-8
14
24
2
D 15-8
8
16
A
D
A
CS
PROGRAM
MEMORY
OE
OE
WE
WE
(OPTIONAL)
D
CS
A
OE
DATA
MEMORY &
PERIPHERALS
D
CS
BOOT
MEMORY
e.g., EPROM
27C64
27C128
27C256
27C512
(OPTIONAL)
NOTE: The two MSBs of the Boot EPROM Address are also the two MSBs of the Data Bus.
This is only for the 27C256 and 27C512.
Figure 3. ADSP-21msp58/59 Basic System Configuration
2000 CLKIN cycles will ensure that the PLL has locked (this
does not, however, include the crystal oscillator start-up time).
During this power-up sequence, the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, tRSP.
CLKOUT signal is enabled and disabled by the CLKODIS bit
in the SPORT0 Autobuffer Control Register, DM[0x3FF3].
Because the ADSP-21msp58/59 includes an on-chip oscillator
circuit, an external crystal may also be used. The crystal should
be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 4. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
CLKIN
XTAL
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended.
The master RESET sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the
boot loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000 and execution begins.
CLKOUT
ADSP-21msp58/59
Program Memory Interface
Figure 4. External Crystal Connections
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the onchip data memory buses (DMA, DMD), creating a single external data bus and a single external address bus. The data and
address busses are three-stated when the DSP runs from internal memory. Refer to the ADSP-2100 Family User’s Manual,
Chapter 10, “Memory Interface” for a detailed explanation. The
14-bit address bus directly addresses up to 16K words. See
“Program Memory Maps” for details on program memory
addressing.
Reset
The RESET signal initiates a master reset of the ADSP21msp58/59. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the
processor’s internal clock to stabilize. If RESET is asserted at
any time after power-up, the clock continues to run and does
not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
The program memory data lines are bidirectional. The program
memory select (PMS) signal indicates access to program
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and is used as a write strobe.
–6–
REV. 0
ADSP-21msp58/59
The read (RD) signal indicates a read operation and is used as a
read strobe or output enable signal. An external program
memory access should always be qualified with the PMS signal.
When MMAP = 1, 14K words of external program memory begin at address 0x0000 and internal RAM is located in the upper
2K words, beginning at address 0x3800. In this configuration,
the boot loading sequence does not take place; execution begins
immediately after RESET.
The ADSP-21msp58/59 writes data from its 16-bit registers to
24-bit program memory using the PX register to provide the
lower eight bits. When the processor reads data (not instructions) from 24-bit program memory to a 16-bit data register, the
lower eight bits are placed in the PX register. The program
memory interface can generate zero to seven wait states for external memory devices; the default is seven wait states after
RESET.
ADSP-21msp59
The ADSP-21msp59 is functionally identical to the ADSP21msp58. The ADSP-21msp59 includes an additional 4K by
24-bit mask programmable ROM (see Figure 6). The ROM
can be used to hold program instructions or data and can be
accessed twice in one instruction cycle if necessary. The ROM
always resides at locations PM[0x0800] through PM[0x17FF]
regardless of the state of the MMAP pin. Sixteen addresses at
the end of ROM (0x17F0–0x17FF) are reserved for Analog
Devices’ use. The ROM is enabled by setting the ROMENABLE
bit in the Data Memory Wait State control register, DM[0x3FFE].
When the ROMENABLE bit is set to 1, addressing program
memory in this range will access the on-chip ROM. When set
to 0, addressing program memory in this range will access external program memory. The ROMENABLE bit is set to 0 on
chip reset.
Program Memory Maps
ADSP-21msp58
ADSP-21msp58 Program memory can be mapped in two ways,
depending on the state of the MMAP pin. Figure 5 shows the
two configurations. When MMAP = 0, internal RAM occupies
2K words beginning at address 0x0000; external program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration, the boot loading sequence (described in “Boot Memory Interface”) is automatically initiated
when RESET is released.
0000
Data Memory Interface
0000
The data memory address bus (DMA) is 14 bits wide. The bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
INTERNAL
RAM
LOADED FROM
EXTERNAL
BOOT
MEMORY
EXTERNAL
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
07FF
0800
EXTERNAL
The ADSP-21msp58/59 supports memory-mapped I/O, with
the peripherals memory mapped into the data or program
memory address spaces and accessed by the processor in the
same manner.
37FF
3800
INTERNAL
RAM
NOT LOADED
3FFF
MMAP=0
Data Memory Map
The on-chip data memory RAM resides in the 2K words beginning at address 0x3000, as shown in Figure 7. In addition, data
memory locations from 0x3800 to the end of data memory at
0x3FFF are reserved. Control registers for the system, timer,
3FFF
MMAP=1
Figure 5. ADSP-21msp58 Program Memory Maps
0000
INTERNAL
MASK
PROGRAMMED
ROM
17F0 – 17FF
RESERVED
0000
INTERNAL
RAM
LOADED FROM
EXTERNAL
BOOT
MEMORY
INTERNAL
RAM
LOADED FROM
EXTERNAL
BOOT
MEMORY
07FF
0800
17FF
1800
0000
0000
EXTERNAL
07FF
0800
INTERNAL
MASK
PROGRAMMED
ROM
17F0 – 17FF
RESERVED
EXTERNAL
EXTERNAL
07FF
0800
17FF
1800
37FF
3800
EXTERNAL
EXTERNAL
INTERNAL
RAM
NOT LOADED
ROM ENABLE = 1
MMAP = 0
3FFF
INTERNAL
RAM
NOT LOADED
3FFF
3FFF
ROM ENABLE = 0
MMAP = 0
37FF
3800
ROM ENABLE = 1
MMAP = 1
3FFF
ROM ENABLE = 0
MMAP = 1
Figure 6. ADSP-21msp59 Program Memory Maps
REV. 0
–7–
ADSP-21msp58/59
HIP Booting
wait-state configuration, host interface port, codec, and serial
port operations are located in this region of memory.
The ADSP-21msp58/59 can also boot programs through the
Host Interface Port. If BMODE = 1 and MMAP = 0, the
ADSP-21msp58/59 boots from the HIP. If BMODE = 0, the
ADSP-21msp58/59 boots through the data bus (in the same
way as the ADSP-2101), as described above in “Boot Memory
Interface.” For additional information about HIP booting, refer
to the ADSP-2100 Family User’s Manual, Chapter 7, “Host Interface Port.”
The remaining 12K of data memory is external. External data
memory is divided into three zones, each associated with its own
wait-state generator. By mapping peripherals into different
zones, you can accommodate peripherals with different waitstate requirements. All zones default to seven wait states after
RESET.
For compatibility with other ADSP-2100 Family processors, bit
definitions for DWAIT3 and DWAIT4 are shown in the Data
Memory Wait State Control register, but they are not used by
the ADSP-21msp58/59.
0000
0000
DWAIT0
(1K EXTERNAL)
DWAIT1
(1K EXTERNAL)
The ADSP-2100 Family Development Software includes a
utility program called the HIP Splitter. This utility allows the
creation of programs that can be booted through the ADSP21msp58/59 HIP, in a similar fashion as EPROM-bootable
programs generated by the PROM Splitter utility.
Bus Request and Bus Grant
03FF
0400
07FF
0800
The ADSP-21msp58/59 can relinquish control of the data and
address buses to an external device. When the external device
requires access to memory, it asserts the bus request signal
(BR). If the ADSP-21msp58/59 is not performing an external
memory access, it responds to the active BR input in the following processor cycle by
• three-stating the data and address buses and the PMS, DMS,
BMS, RD, and WR output drivers,
• asserting the bus grant (BG) signal, and
• halting program execution.
12K
EXTERNAL
DWAIT2
(10K EXTERNAL)
2FFF
3000
2FFF
3000
2K
INTERNAL
NO WAIT STATES
1K
RESERVED
MEMORY MAPPED
REGISTERS
AND RESERVED
3BFF
3C00
If GoMode is enabled, the ADSP-21msp58/59 will not halt program execution until it encounters an instruction that requires
an external memory access.
3FFF
3FFF
WAIT STATES
37FF
3800
DATA MEMORY
If the ADSP-21msp58/59 is performing an external memory access when the external device asserts the BR signal, then it will
not three-state the memory interfaces or assert the BG signal
until the cycle after the access is completed, which can be up to
eight cycles later depending on the number of wait states. The
instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory
accesses, the bus will be granted between the two accesses.
Figure 7. ADSP-21msp58/59 Data Memory Maps
Boot Memory Interface
The ADSP-21msp58/59 can load on-chip memory from external boot memory space. The boot memory space consists of
64K by 8-bit space, divided into eight separate 8K by 8-bit
pages. Three bits in the System Control Register select which
page is loaded by the boot memory interface. Another bit in the
System Control Register allows the user to force a boot loading
sequence under software control. Boot loading from Page 0 after
RESET is initiated automatically if MMAP = 0.
When the BR signal is released, the processor releases the BG
signal, which reenables the output drivers, and continues program execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The boot memory interface can generate zero to seven wait
states; it defaults to seven wait states after RESET. This allows
the ADSP-21msp58/59 to boot from a single low cost EPROM
such as a 27C256. Program memory is booted one byte at a
time and converted to 24-bit program memory words.
LOW POWER OPERATION
The ADSP-21msp58/59 has three low power modes that significantly reduce the power dissipation when the device operates
under standby conditions. These modes are:
The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8–D15. To accommodate addressing up to eight
pages of boot memory, the two MSBs of the data bus are used
in the boot memory interface as the two MSBs of the boot
memory address.
• Powerdown
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation. The CLKOUT pin is controlled by Bit 14 of
SPORT0 Autobuffer Control Register, DM[0x3FF3].
The ADSP-2100 Family Assembler and Linker support the creation of programs and data structures requiring multiple boot
pages during execution.
Powerdown
RD and WR must always be qualified by PMS, DMS, or BMS
to ensure the correct program, data, or boot memory accessing.
The ADSP-21msp58/59 has a low power feature that lets the
processors enter a very low power dormant state through hardware or software control. Here is a brief list of powerdown features. Refer to the ADSP-2100 Family User’s Manual, Chapter 9,
–8–
REV. 0
ADSP-21msp58/59
“System Interface” for detailed information about the powerdown feature.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
• Powerdown mode holds the processor in CMOS standby with
a maximum current of less than 100 µA in some modes.
• Quick recovery from powerdown. In some modes, the processor can begin executing instructions in less than 100 CLKIN
cycles.
Standalone ROM Execution (ADSP-21msp59 Only)
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLKIN cycle recovery.
When the MMAP and BMODE pins both are set to 1, the
ROM is automatically enabled and execution commences from
program memory location 0x0800 at the start of ROM. This
feature lets an embedded design operate without external
memory components. To operate in this mode, the ROM coded
program must copy an interrupt vector table to the appropriate
locations in program memory RAM. In this mode, the ROM
enable bit defaults to 1 during reset.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and
letting the oscillator run to allow 100 CLKIN cycle start-up.
• Powerdown is initiated by either the powerdown pin (PWD)
or the software powerdown force bit.
Table III. Boot Summary Table
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The powerdown interrupt also can be used as a non-maskable, edgesensitive interrupt.
• Context clear/save control lets the processor continue where it
left off or start with a clean context when leaving the powerdown state.
• The RESET pin also can be used to terminate powerdown,
and the host software reset feature can be used to terminate
powerdown under certain conditions.
BMODE = 0
BMODE = 1
MMAP = 0
Boot from EPROM,
then execution starts
at internal RAM
location 0x0000
Boot from HIP, then
execution starts at
internal RAM location
0x0000
MMAP = 1
No booting, execution
Stand Alone Mode,
starts at external memory execution starts at
location 0x0000
internal ROM location
0x0800
• Setting the CLKODIS bit (Bit 14 of the SPORT0 Autobuffer
Control Register [0x3FF3]) disables the CLKOUT pin during
powerdown.
Ordering Procedure For ADSP-21msp59 ROM Processors
Idle
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
To place an order for a custom ROM-coded ADSP-21msp59
processor, you must:
When the ADSP-21msp58/59 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruction.
ADSP-21msp59 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Preproduction ROM Products
Slow Idle
The IDLE instruction is enhanced on the ADSP-21msp58/59 to
let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering changes (NRE) associated with ROM product
development.
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, and timer clock, are reduced by the same ratio.
CLKOUT remains at the normal rate; it is not reduced. The default form of the instruction, when no clock divisor is given, is
the standard IDLE instruction.
After this information is received, it is entered into Analog
Devices’ ROM Manager System that assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts––the 1-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-21msp58/59 remains in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
REV. 0
–9–
ADSP-21msp58/59
Bit 10 of the Analog Control Register (0x3FEE) may be set to
add an offset to the input of the ADC sigma-delta converter.
This offset moves ADC sigma-delta idle tones out of the 4.0
kHz speech band range. This added offset must be removed by
the ADC high-pass filter. Therefore, the high-pass filter must be
inserted when you use the offset feature.
A signed ROM Verification Form and a purchase order for production units are required prior to any product being manufactured. Prototype units may be applied toward the minimum
order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for production units. An invoice against your purchase order for the
NRE charges is issued at this time.
D/A Conversion
The D/A conversion circuitry of the analog interface consists of
a sigma-delta digital-to-analog converter (DAC), an analog
smoothing filter, a programmable gain amplifier (DAC PGA),
and a differential output amplifier.
There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
Digital-to-Analog Converter
ANALOG INTERFACE
The analog interface contains encoding circuitry (ADC), decoding circuitry (DAC), and processor interface logic. A block diagram of the ADSP-21msp58/59 analog section is shown in
Figure 8.
The analog interface is configured through the Analog Control
Register and the Analog Autobuffer/Powerdown Register (refer
to “ADSP-21msp58/59 Registers”). The Analog Control Register DM[0x3FEE] configures the programmable gain stages, the
analog input multiplexer, and the analog interface powerdown
state. Note that the unused bits must be cleared to zero.
VIN NORM
MUX
ADC
PGA
VINAUX
Analog Smoothing Filter and Programmable Gain Amplifier
The analog smoothing filter consists of a 3rd-order switched capacitor filter with a 3 dB point at approximately 25 kHz.
The DAC’s programmable gain amplifier (DAC PGA) can be
used to adjust the output signal level by –15 dB to +6 dB in
3 dB increments. This gain is selected by bits 2–4 (OG0, OG1,
OG2) of the analog control register.
16-BIT
SIGMADELTA
ADC
Differential Output Amplifier
The analog output signal (VOUTP, VOUTN) is produced by a
differential amplifier. The differential amplifier meets specifications for loads greater than 2 kΩ and has a maximum differential output swing of ± 3.156 V peak-to-peak (3.17 dBm0). The
DAC will drive loads smaller than 2 kΩ, but with degraded
performance.
DECOUPLE
VOLTAGE
REFERENCE
REF_FILTER
VREF
VOUTP
VOUTN
PROCESSOR
INTERFACE
BUF
DAC
PGA
ANALOG
SMOOTHING
FILTER
The digital-to-analog converter consists of an optional digital
high-pass filter, an anti-imaging interpolation filter, and a
sigma-delta modulator. The digital filters and the sigma-delta
modulator have the same characteristics as the filters and
modulator of the ADC. For detailed description of the DAC
components, refer to the ADSP-2100 Family User’s Manual,
Chapter 8, “Analog Interface.”
16
16-BIT
SIGMADELTA
DAC
The output signal is dc-biased to the on-chip voltage reference
(VREF) and can be ac-coupled directly to a load or dc-coupled to
an external amplifier.
OUTPUT
DIFFERENTIAL AMP
Figure 8. Analog Interface Block Diagram
The VOUTP, VOUTN output must be used as a differential signal otherwise performance will be severely compromised. Do
not use either pin as a single-ended output.
A/D Conversion
The A/D conversion circuitry of the analog interface consists of
an analog multiplexer, a programmable gain amplifier (ADC
PGA), and a 16-bit sigma-delta analog-to-digital converter
(ADC).
OPERATING THE ANALOG INTERFACE
Analog Input Multiplexer and Amplifiers
The analog multiplexer selects either the NORM or AUX input
to the ADC’s sigma-delta modulator. The inputs should be ac
coupled.
The ADC PGA may be used to additionally increase the signal
level by +6 dB, +20 dB, or +26 dB. This gain is selected by bit
9 and bit 0 (IG0, IG1) of the analog control register. Input signal level to the sigma-delta ADC should not exceed the VINMAX
specification.
Analog-To-Digital Converter
The analog interface’s analog-to-digital converter consists of a
4th-order analog sigma-delta modulator, an anti-aliasing decimation filter, and an optional digital high-pass filter. For a detailed
description of the ADC components, refer to the ADSP-2100
Family User’s Manual, Chapter 8, “Analog Interface.”
The analog interface is operated with several memory-mapped
control and data registers. The ADC and DAC I/O data is received and transmitted through two memory-mapped data registers. The data can also be autobuffered directly into (or from)
on-chip memory. In both cases, the I/O processing is interrupt
driven; two interrupts are dedicated to the analog interface, one
for the ADC receive data and one for the DAC transmit data.
The ADSP-21msp58/59 must have an input clock frequency of
13 MHz. At this frequency, analog-to-digital and digital-to-analog converted data is transmitted at an 8 kHz rate with a single
16-bit word transmitted every 125 µs.
For detailed information about the analog interface, refer to the
ADSP-2100 Family User’s Manual, Chapter 8, “Analog Interface.”
–10–
REV. 0
ADSP-21msp58/59
Autobuffering
APWD bits (Bits 5 and 6) to one in the analog control register.
Because both interrupts occur simultaneously, only one should
be enabled (in IMASK) to vector to a single service routine that
handles transmit and receive data. However, when using
autobuffer transfers, both interrupts should be enabled.
In some applications, it is advantageous to perform block data
transfers between the analog converters and processor memory.
Analog interface autobuffering enables the automatic transfer of
data blocks directly from the ADC to on-chip processor data
memory or from on-chip processor data memory directly to the
DAC.
ADSP-21msp58/59 REGISTERS
Figure 9 summarizes the ADSP-21msp58/59 registers. Some
registers store values. For example, AX0 stores an ALU operand; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the number of wait states for different zones of data
memory.
ADC and DAC Interrupts
The analog interface generates two interrupts that signal either:
(1) a 16-bit, 8 kHz analog-to-digital or digital-to-analog conversion has been completed, or (2) an autobuffer block transfer
has been completed (i.e., the data buffer contents have been
received or transferred).
When an analog interrupt occurs, the processor vectors to the
addresses listed in Table II, Interrupt Priority & Interrupt Vector
Addresses.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The ADC receive and DAC transmit interrupts occur at an
8 kHz rate, indicating when the data registers should be accessed. On the receive side, the ADC interrupt is generated each
time an A/D conversion cycle is completed and the 16-bit data
word is available in the ADC receive register. On the transmit
side, the DAC interrupt is generated each time an D/A conversion cycle is completed and the DAC transmit register is ready
for the next 16-bit data word.
Both interrupts are generated simultaneously at an 8 kHz rate,
occurring every 3250 instruction cycles with a 13 MHz internal
processor clock. The interrupts are generated continuously,
starting when the analog interface is powered up by setting the
The bit and field definitions for control and status registers are
given in the rest of this section, except IMASK, ICNTL, and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory locations; that is, you access these
registers by reading and writing data memory locations rather
than register names. The particular data memory address is
shown with each memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeterminate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
PROGRAM SEQUENCER
ICNTL
IFC
SSTAT
DAG 1
I0
I1
I2
I3
M0
M1
M2
M3
L0
L1
L2
L3
DAG 2
I4
I5
I6
I7
M4
M5
M6
M7
OWRCNTR
MSTAT
ASTAT
COUNT
STACK
4 x 14
STATUS
STACK
12 x 25
CNTR
L4
L5
L6
L7
LOOP
STACK
4 x 18
IMASK
PC
STACK
16 x 14
AX0 AX1 AY0 AY1
MX0 MX1 MY0 MY1
ALU
MAC
SHIFTER
MR0 MR1 MR2 MF
SR0 SR1
AR
AF
SI
SE
SB
PROGRAM
SRAM
2K x 24
0x3FFF SYSTEM CONTROL
0x3FFE DM WAIT CONTROL
14
PMA BUS
14
DMA BUS
24
PMD BUS
16
DMD BUS
0x3FEC
0x3FED
ADC
DAC
0x3FEE-0x3FEF
CONTROL REGISTERS
ANALOG INTERFACE
PROGRAM
ROM
4K x 24
ADSP-21msp59
ONLY
HOST
INTERFACE
PORT
0x3FE0-0x3FE5 DATA
0x3FE6-0x3FE7 STATUS
0x3FE8
HMASK
PX
RX0 TX0
RX1 TX1
TIMER
0x3FFA-0x3FF3
CONTROL REGISTERS
0x3FF2-0x3FEF
CONTROL REGISTERS
SPORT 0
SPORT 1
0x3FFD TPERIOD
0x3FFC TCOUNT
0x3FFB TSCALE
Figure 9. ADSP-21msp58/59 Registers
REV. 0
DATA
SRAM
2K x 16
–11–
FLAG
POWERDOWN
CONTROL
LOGIC
ADSP-21msp58/59
SSTAT (Read -Only)
ASTAT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
AZ ALU Result Zero
AN ALU Result Negative
AV ALU Overflow
AC ALU Carry
AS ALU X Input Sign
AQ ALU Quotient
MV MAC Overflow
SS Shifter Input Sign
PC Stack Empty
PC Stack Overflow
Count Stack Empty
Count Stack Overflow
Status Stack Empty
Status Stack Overflow
Loop Stack Empty
Loop Stack Overflow
MSTAT
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Data Register Bank Select
0 = primary, 1 = secondary
Bit Reverse Mode Enable (DAG1)
ALU Overflow Latch Mode Enable
AR Saturation Mode Enable
MAC Result Placement
0 = fractional, 1 = integer
Timer Enable
Go Mode Enable
System Control Register
0x3FFF
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
SPORT0 Enable
1 = enabled, 0 = disabled
PWAIT
Program Memory
Wait States
SPORT1 Enable
1 = enabled, 0 = disabled
BWAIT
Boot Wait States
SPORT1 Configure
1 = serial port
0 = FI, FO, IRQ0, IRQ1, SCLK
BPAGE
Boot Page Select
BFORCE
Boot Force Bit
Timer Registers
15
0
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
3
2
1
0
TPERIOD Period Register
0x3FFD
TCOUNT Counter Register
0x3FFC
0
0
0
TCOUNT Scaling Register
0x3FFB
Control Registers
–12–
REV. 0
ADSP-21msp58/59
ROM Enable/Data Memory Wait State
Control Register
0x3FFE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DWAIT3
DWAIT4
DWAIT2
DWAIT1
DWAIT0
ROM enable (ADSP-21msp59)
1 = enable
0 = disable
SPORT0 Multichannel Receive Word Enable Registers
SPORT0 Multichannel Transmit Word Enable Registers
1 = Channel Enabled
0 = Channel Ignored
1 = Channel Enabled
0 = Channel Ignored
0x3FF8
0x3FFA
31 30
29 28 27
15 14
13 12
26 25
24 23
22 21
20 19
6
4
18 17 16
31 30
29 28 27
26 25
15 14
13 12 11 10
9
8
7
22 21
20 19
18 17 16
0x3FF7
0x3FF9
11 10
24 23
5
3
2
1
0
9
8
7
6
5
4
3
2
1
0
SPORT0 Control Register
0x3FF6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SLEN Serial Word Length
Multichannel Enable MCE
DTYPE Data Format
Internal Serial Clock Generation ISCLK
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using µ-law
11 = compand using A-law
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
INVRFS Invert Receive Frame Sync
Multichannel Frame Delay MFD
Only If Multichannel Mode Enabled
INVTFS Invert Transmit Frame Sync
(or INVTDV Invert Transmit Data Valid
Only If Multichannel Mode Enabled )
Transmit Frame Sync Required TFSR
Transmit Frame Sync Width TFSW
IRFS Internal Receive Frame Sync Enable
ITFS Internal Transmit Frame Sync Enable
(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words
Only If Multichannel Mode Enabled )
Control Registers
REV. 0
–13–
ADSP-21msp58/59
SPORT0 SCLKDIV
Serial Clock Divide Modulus
0x3FF5
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
2
1
0
0
0
SPORT0 RFSDIV
Receive Frame Sync Divide Modulus
0x3FF4
15
14
13
12
11
10
9
8
7
6
5
4
3
SPORT0 Autobuffer Control Register
0x3FF3
15
14
13
12
0
0
0
0
11
10
9
8
7
6
5
4
3
RBUF
Receive Autobuffering Enable
CLKODIS
CLKOUT Disable Control Bit
TBUF
Transmit Autobuffering Enable
BIASRND
MAC Biased Rounding Control Bit
RMREG
Receive Autobuffer M Register
TIREG
Transmit Autobuffer I Register
RIREG
Receive Autobuffer I Register
TMREG
Transmit Autobuffer M Register
SPORT1 Control Register
0x3FF2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flag Out (Read Only)
SLEN Serial Word Length
DTYPE Data Format
Internal Serial Clock Generation ISCLK
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using µ-law
11 = compand using A-law
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
INVRFS Invert Receive Frame Sync
Transmit Frame Sync Required TFSR
INVTFS Invert Transmit Frame Sync
Transmit Frame Sync Width TFSW
IRFS Internal Receive Frame Sync Enable
ITFS Internal Transmit Frame Sync Enable
Control Registers
–14–
REV. 0
ADSP-21msp58/59
SPORT1 SCLKDIV
Serial Clock Divide Modulus
0x3FF1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
1
0
0
0
SPORT1 RFSDIV
Receive Frame Sync Divide Modulus
0x3FF0
15
14
13
12
11
10
9
8
7
6
5
4
3
Analog Autobuffer/Powerdown Control Register
0x3FEF
15
14
13
12
0
0
0
0
11
10
9
8
7
6
5
4
3
2
ARBUF
ADC Receive Autobuffer Enable
XTALDIS
XTAL Pin Disable During Powerdown
1 = disabled, 0 = enabled
(XTAL pin should be disabled when
no external crystal is connected)
ATBUF
DAC Transmit Autobuffer Enable
ARMREG
Receive M Register
XTALDELAY
Delay Startup From Powerdown 4096 Cycles
1 = delay, 0 = no delay
(use delay to let internal phase locked
loop or external oscillator stabilize)
ARIREG
Receive I Register
ATMREG
Transmit M Register
PDFORCE
Powerdown Force
1 = force processor to vector to
powerdown interrupt
ATIREG
Transmit I Register
PUCR
Powerup Context Reset
1 = soft reset, 0 = resume execution
HMASK Register
0x3FE8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Host HDR5 Read
Host HDR0 Write
Host HDR4 Read
Host HDR1 Write
Host HDR3 Read
Host HDR2 Write
Host HDR2 Read
Host HDR3 Write
Host HDR1 Read
Host HDR4 Write
Host HDR5 Write
Host HDR0 Read
Interrupt Enables
1 = Enable
0 = Disable
Control Registers
REV. 0
–15–
ADSP-21msp58/59
Analog Control Register
0x3FEE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OG2
OG1
OG0
ADC Offset
IG0
ADC Input Gain
IG0, IG1
ADC Input Gain (for PGA)
Gain
0dB
+6dB
+20dB
+26dB
IG1 IG0
0
0
0
1
1
0
1
1
IG1
ADC Input Gain
DABY
DAC High Pass Filter Bypass
1 = bypass, 0 = insert
IMS
ADC Input Multiplexer Select
1 = AUX input, 0 = NORM input
ADBY
ADC High Pass Filter Bypass
1 = bypass, 0 = insert
OG2, OG1, OG0
DAC Output Gain (for PGA)
APWD
Analog Interface Powerdown
0 = powerdown, 1 = enable
(set both bits to 1
to enable analog interface)
Gain
+6dB
+3dB
0dB
–3dB
–6dB
–9dB
–12dB
–15dB
All bits are set to 0 at processor reset.
(Reserved bits 11–15 must always be set to 0)
IG2 IG1 IG1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
ADC Receive
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM(0x3FED)
DAC Transmit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM(0x3FEC)
HIP Data Registers
HDR5
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x3FE5
HDR4
0x3FE4
HDR3
0x3FE3
HDR2
0x3FE2
HDR1
0x3FE1
HDR0
0x3FE0
Control Registers
–16–
REV. 0
ADSP-21msp58/59
HSR6
0x3FE6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADSP-21msp58/59 HDR5 Write
Host HDR0 Write
ADSP-21msp58/59 HDR4 Write
Host HDR1 Write
ADSP-21msp58/59 HDR3 Write
Host HDR2 Write
ADSP-21msp58/59 HDR2 Write
Host HDR3 Write
ADSP-21msp58/59 HDR1 Write
Host HDR4 Write
ADSP-21msp58/59 HDR0 Write
Host HDR5 Write
HSR7
0x3FE7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
ADSP-21msp58/59 HDR0 Write
ADSP-21msp58/59 HDR1 Write
ADSP-21msp58/59 HDR2 Write
ADSP-21msp58/59 HDR3 Write
ADSP-21msp58/59 HDR4 Write
ADSP-21msp58/59 HDR5 Write
Overwrite Mode
Software Reset
Control Registers
INSTRUCTION SET DESCRIPTION
ADSP-21msp58/59 EXTENDED INSTRUCTION SET
The ADSP-21msp58/59 assembly language instruction set has
an algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage
of the processor’s unique architecture, offers the following
benefits:
The ADSP-21msp58/59 has a number of additional instructions beyond the standard ADSP-2100 Family instruction set.
These additional instructions and mathematical operations are
described below.
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
Slow IDLE allows slowing the processor’s internal clock by a
factor of 16, 32, 64, or 128 during IDLE. The instruction
source code is specified as follows:
Syntax:
IDLE (n);
Permissible Values for n
16, 32, 64, 128
Examples:
IDLE;
IDLE (16);
Description: The IDLE instruction causes the processor to
wait indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with
the instruction following the IDLE instruction.
The optional value provides a “slow idle” feature; slowing the clock down by the factor set
with the value.
• Every instruction assembles into a single 24-bit word and
executes in a single cycle.
•The syntax is a superset of the ADSP-2100 Family assembly
language and is completely source and object code compatible
with other family members. Programs may, however, need to
be relocated to utilize internal memory and conform to the
ADSP-21msp58/59 interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches and one write to
processor memory space during a single instruction cycle.
Consult the ADSP-2100 Family User’s Manual for a complete
description of the syntax and an instruction set reference.
REV. 0
Slow IDLE
Interrupt Enable and Disable Instructions
The ADSP-21msp58/59 supports an interrupt enable instruction and interrupt disable instruction. Interrupts are enabled by
default at reset. The interrupt enable instruction source code is
specified as follows:
–17–
ADSP-21msp58/59
1024, 1025, 2047, 2048, 2049, 4095, 4096, 4097, 8191, 8192,
8193, 16383, 16384, 16385, 32766, 32767, –1, –2, –3, –4, –5,
–6, –8, –9, –10, –16, –17, –18, –32, –33, –34, –64, –65, –66, –128,
–129, –130, –256, –257, –258, –512, –513, –514, –1024, –1025,
–1026, –2048, –2049, –2050, –4096, –4097, –4098, –8192, –8193,
–8194, –16384, –16385, –16386, –32767, –32768
Syntax:
ENA INTS;
Description: Executing the ENA INTS instruction allows all
unmasked interrupts to be serviced again.
The interrupt disable instruction source code is specified as
follows:
Syntax:
DIS INTS;
Examples:
Description: Reset enables interrupt servicing. Executing the
DIS INTS instruction causes all interrupts to be
masked without changing the contents of the
IMASK register. Disabling interrupts does not
affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
Extended ALU and Multiplier Operations
The following extended computation operations are available
only on the ADSP-21msp58/59 processor. The term “base instruction set” refers to the computations and instructions available on all ADSP-21xx processors.
Additional Constants for ALU Operations
A new set of numerical constants may be used in all nonmultifunction ALU operations (except DIVS and DIVQ) using both
X and Y operands. The instruction source code is specified as
follows:
Syntax: [IF condition]  AR  = xop function  yop

 AF 
 constant 
Permissible xops
AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1
Permissible functions
ADD/ADD with CARRY, SUBTRACT X–Y/SUBTRACT X–
Y with BORROW, SUBTRACT Y–X/SUBTRACT Y–X with
BORROW, AND, OR, XOR
Permissible yops (base instruction set)
AY0, AY1, AF
Permissible yops and constants (extended instruction set)
AY0, AY1, AF, 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024,
2048, 4096, 8192, 16384, 32767, –2, –3, –5, –9, –17, –33, –65,
–129, –257, –513, –1025, –2049, –4097, –8193, –16385, –32768
Examples:
AR = AR+1;
AR = MR1 - 33;
IF GT AF = AX1 OR 16;
Description: Test the optional condition and, if true, perform
the specified function. If false then perform a nooperation. Omitting the condition performs the
function unconditionally. The operands are contained in the data registers specified in the instruction or optionally a constant may be used.
Additional Constants for ALU PASS Operation
A new set of numerical constants may be used in the PASS instruction. The instruction source code is specified as follows:
Syntax: [IF condition]  AR  = pass  yop

 AF 
 constant 
Permissible yops (base instruction set)
AY0, AY1, AF
Permissible yops and constants (extended instruction set)
AY0, AY1, AF, 0, 1, 2, 3, 4, 5, 7, 8, 9, 15, 16, 17, 31, 32, 33,
63, 64, 65, 127, 128, 129, 255, 256, 257, 511, 512, 513, 1023,
IF GE AR = PASS AY0;
IF EQ AF = PASS –1025;
Description: Test the optional condition and, if true, pass the
source operand unmodified through the ALU
block and store in the destination location. If the
condition is not true, perform a no-operation.
Omitting the condition performs the pass unconditionally. The source operand is contained in
the data registers specified in the instruction or
optional constant.
The PASS instruction performs the transfer to the
AR register and affect the status flag; this instruction is different from a register move operation
which does not affect any status flags. PASS 0 is
one method of clearing AR. PASS 0 can also be
combined in a multifunction instruction in conjunction with memory reads and writes to clear AR.
Note:
The ALU status flags (in the ASTAT register)
are not defined for the execution of this instruction when using the constant values other than 0,
1, and –1.
ALU Bit Operations
The additional constants for ALU operations allow you to code
bit test, set, clear, and toggle operations through careful choice
of the constant and ALU function. For streamlined programming,
the source code for these operations can also be specified as:
Syntax: [IF condition]  AR 
 AF 
= 



TSTBIT n of xop; 
SETBIT n of xop; 
CLBIT n of xop; 
TGBIT n of xop; 
Permissible xops
AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1
Permissible n Values (0 = LSB)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
Examples:
AF=TSTBIT 5 of AR;
IF NE JUMP SET;
/* JUMP TO SET IF BIT IS SET */
Definitions of Operations
TSTBIT is an AND operation with a 1 in the selected bit
SETBIT is an OR operation with a 1 in the selected bit
CLBIT is an AND operation with a 0 in the selected bit
TGBIT is an XOR operation with a 1 in the selected bit
Result-Free ALU Operations
The result-free ALU operations allow the generation of condition flags based on an ALU operation but discard the result.
The source code for the instruction is specified as follows:
Syntax:
NONE = <ALU>;
where <ALU> is any unconditional ALU operation of the 21xx
base instruction set (except DIVS or DIVQ). (Note that the additional constant ALU operations of the ADSP-2171/2181 extended instruction set are not allowed.)
–18–
REV. 0
ADSP-21msp58/59
be masked without changing the contents of the
IMASK register. Disabling interrupts does not affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
Examples:
NONE = AX0 – AY0;
NONE = PASS SR0;
Description: Perform the designated ALU operation, set the
condition flags, then discard the result value.
This allows the testing of register values without
disturbing the AR or AF register values.
MAC Operations
CIRCUIT DESIGN CONSIDERATIONS
A modified MAC operation allows additional type 9 instructions. The conditional ALU/MAC instruction has been modified to allow the X operand to be used as the Y operand as well.
This allows a single cycle X2, and also ∑X2 operations.
The new MAC instructions allow the use of any xop as both the
X and Y operands. The instructions source code is specified as
follows:
The following sections discuss interfacing analog signals to the
ADSP-21msp58/59.
Analog Signal Input
Figure 10 shows the recommended input circuit for the analog input pin (either VINNORM or VINAUX). The circuit of Figure 10
implements a first-order low-pass filter (R1C1) with a 3 dB point
less than 40 kHz. This is the only filter required external to the
processor to prevent aliasing of the sampled signal. Since the
ADSP-21msp58/59’s sigma-delta ADC uses a highly oversampled
approach that transfers the bulk of the anti-aliasing filtering into the
digital domain, the off-chip anti-aliasing need only be of low order.
Syntax: [IF condition]  MR  =  [MR +]  xop * yop (UU);
 MF 
 [MR –] 
xop (SS) ;
(RND);
Permissible xops
AR, MR0, MR1, MR2, MX0, MX1, SR0, SR1
Example:
IF LT MR=MR+ SR0 * SR0 (SS);
Note:
Both X operators must be the same register.
Biased Rounding
A new mode has been added to allow biased rounding in addition to the normal unbiased rounding. When the BIASRND bit
is set to 0 the normal unbiased rounding operations occur.
When the BIASRND bit is set to 1, biased rounding occurs instead of the normal unbiased rounding. When operating in biased rounding mode all rounding operations with MR0 set to
0x8000 will round up, rather than only rounding odd MR1
values up. For example:
MR value before RND
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
biased RND result
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
C3
STAR
GROUND
VIN NORM
VINAUX
C1
INPUT
SOURCE
MUX
PGA
DECOUPLE
ADSP-21msp58/59
Figure 10. Recommend Analog Input Circuit
The on-chip ADC PGA can be used when there is not enough
gain in the input circuit. The PGA gain is set by bits 9 and 0
(IG1, IG0) of the processor’s analog control register. The gain
must be chosen to ensure that a full-scale input signal (at R1 in
Figure 10) produces a signal level at the input to the sigma-delta
modulator of the ADC that does not exceed VINMAX (refer to
the “Analog Interface Electrical Characteristics” specifications).
unbiased RND result
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000, all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit specified algorithms which specify biased rounding such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note:
BIASRND bit is bit twelve of the SPORT0
Autobuffer Control register.
Interrupt Enable
The ADSP-21msp58/59 supports an interrupt enable instruction. Interrupts are enabled by default at reset. The instruction
source code is specified as follows:
Syntax:
ENA INTS;
Description:
Executing the ENA INTS instruction allows
all unmasked interrupts to be serviced again.
VINNORM and VINAUX are biased at the Internal Reference Voltage (nominal of 2.5 V) of the ADSP-21msp58/59, which lets the
analog section of the processor operate from a single supply.
The input signal should be ac-coupled with an external capacitor (C2). The value of C2 is determined by the input resistance
of the analog input (VINNORM, VINAUX) (200 kΩ) and the desired cutoff frequency. The cutoff frequency should be ≤30 Hz.
The following equation should be used to determine the values
of R1, C1, and C2; R1 should be ≤2.2 kΩ. C2 should be ≥0.027
µF; C3 should be equal to C2.
1
C2 =
2 π f1 RIN
RIN = ADSP-21msp58/59 input resistance (200 kΩ)
f1 = cutoff frequency <30 Hz
1
R1 =
2 π f2 C1
R1 ≤ 2.2 kΩ
f2 > 20 kHz < 40 kHz*
1
C1 =
2 π f2 R1
Interrupt Disable
The ADSP-21msp58/59 supports an interrupt disable instruction. The instruction source code is specified as follows:
Syntax:
DIS INTS;
Description: Reset enables interrupt servicing. Executing the
DIS INTS instruction causes all interrupts to
REV. 0
C2
R1
For optimum ADC performance, C1 should be an NPO type
capacitor.
*If minimum (<0.1 dB) rolloff at 4 kHz is desired, f2 should be set to 40 kHz.
–19–
ADSP-21msp58/59
Analog Signal Output
APPLICATION EXAMPLES
The differential analog output (VOUTP, VOUTN) is produced
by an on-chip differential amplifier which is part of the processor’s
analog interface. The differential amplifier will meet dynamic
specifications for loads greater than 2 kΩ (RL ≥ 2 kΩ) and has a
maximum differential output voltage swing of ±3.156 V peak-topeak (3.17 dBm0). The DAC will drive loads smaller than 2 kΩ,
but with degraded dynamic performance. The differential output can be ac-coupled directly to a load or dc-coupled to an external amplifier.
Figure 11 shows a simple circuit providing a differential output
with ac coupling. The capacitor of this circuit (COUT) is optional; if used, its value can be chosen as follows:
The ADSP-21msp58/59 is ideal for speech processing applications where high performance for analog and digital circuitry is
required, but board space is severely limited. The cellular radio
handset is one application. Here the ADSP-21msp58/59 can
digitize the speech, then perform compression algorithms that
sufficiently reduce the bit rate for transmission in a limited radio
bandwidth.
COUT =
1
(60 π) RL
VOUTP
ADSP-21msp58/59
COUT
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured with a 1.0 kHz sine wave at 0 dBm0.
The absolute gain specification is used as a reference for the
gain tracking error specification.
Gain Tracking Error
COUT
RL
DEFINITION OF SPECIFICATIONS
Absolute Gain
VOUTN
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 1.0 kHz at 0 dBm0. Gain tracking error
at 0 dBm0 is 0 dB by definition.
SNR + THD
Figure 11. Example Circuit for Differential Output with
AC Coupling
The VOUTP and VOUTN outputs must be used as differential
outputs (do not use either as a single-ended output). Figure 12
shows an example circuit which can be used to convert the differential output to a single-ended output. The circuit uses a differential-to-single-ended amplifier, the Analog Devices SSM2141.
+12V
0.1µF
ADSP-21msp58/59
7
GNDA
5
VOUT
SSM2141
VOUTP
4
GNDA
–12V
Crosstalk
Figure 12. Example Circuit for Single-Ended Output
Voltage Reference Filter Capacitance
Figure 13 shows the recommended reference filter capacitor
connections. The capacitor grounds should be connected to the
same star ground point shown in Figure 10.
VREF
REF_FILTER
10µF
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those which
neither m nor n are equal to zero. The second order terms include (fa + fb) and (fa – fb), while the third order terms include
(2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (measured in the frequency range 300 Hz–3400 Hz).
0.1µF
GNDA
Intermodulation Distortion
Idle Channel Noise
VOUTN
1
Signal-to-noise ratio plus total harmonic distortion is defined to
be the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.
BUF
VOLTAGE
REFERENCE
0.1µF
ADSP-21msp58/59
STAR
GROUND
Figure 13. Voltage Reference Filter Capacitor
Crosstalk is defined as the ratio of the rms value of a full-scale
signal appearing on one channel to the rms value of the same
signal that couples onto the adjacent channel. Crosstalk is expressed in dB.
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
a signal on the power supply. Power supply rejection is measured by modulating a signal on the power supply and measuring the signal at the output (relative to 0 dB). Power supply
rejection is defined as the ratio of the rms value of the modulation signal to the rms value of the same signal in the ADC/DAC
channel.
Group Delay
Group delay is defined as the derivative of radian phase with respect to radian frequency, ∂φ(ω)/∂ω. Group delay is a measure
of the average delay of a system as a function of frequency. A
linear system with a constant group delay has a linear phase response. The deviation of group delay away from a constant indicates the degree of nonlinear phase response of the system.
–20–
REV. 0
ADSP-21msp58/59–SPECIFICATIONS
ADSP-21msp58/59
RECOMMENDED OPERATING CONDITIONS
B Grade
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
Min
Max
Unit
4.50
–40
5.50
+85
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
1, 2
Hi-Level Input Voltage
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Tristate Leakage Current7
IOZL
Tristate Leakage Current7
IDD
Digital Supply Current (Idle)6, 9
IDD
Digital Supply Current (Dynamic)9, 10
IDD
Digital Supply Current (Powerdown)9
ICC
CI
Analog Supply Current (Dynamic)9
Input Pin Capacitance3, 11, 12
CO
Output Pin Capacitance7, 11, 12
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min,
IOH = –0.5 mA
@ VDD = min,
IOH = –100 µA6
@ VDD = min,
IOL = 2 mA
@ VDD = max,
VIN = VDD max
@ VDD = max,
VIN = 0 V
@ VDD = max,
VIN = VDD max8
@ VDD = max,
VIN = 0 V8
@ VDD = max,
Codec Inactive
@ VDD = max,
VCC = max
@ VDD = max, See
ADSP-2100 Family User’s
Manual, Chapter 9
Codec Active
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C
2.0
2.2
Max
Unit
0.8
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
µA
18
mA
92
mA
100
18
µA
mA
8
pF
8
pF
NOTES
1
Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, HD0-HD7/HAD0-HAD7.
2
Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
3
Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
4
Output pins: BG, PMS, DMS, BMS, RD, WR, A0-A13, DT0, DT1, CLKOUT, HACK, FL0.
5
Although specified for TTL outputs, all ADSP-21msp58/59 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Idle refers to ADSP-21msp58/59 state of operation during IDLE instruction. Deasserted pins are driven to either V DD or GND. Refer to chart in back for lower
IDLE currents.
7
Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD7/HAD0-HAD7.
8
0 V on BR, CLKIN Active (to force three-state condition).
9
Current reflects the digital portion of device operating with no output loads and a 2 k Ω load on the analog output (VOUT P, VOUTN).
10
tCK = 76.92 ns, CODEC active, 80% execution type 1 instructions, with random data. For typical figures for digital and analog supply currents, refer to “Power
Dissipation” section.
11
Guaranteed but not tested.
12
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
REV. 0
–21–
ADSP-21msp58/59
ABSOLUTE MAXIMUM RATINGS *
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280°C
*
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
The ADSP-21msp58/59 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges
readily accumulate on the human body and equipment and can discharge without detection.
Permanent damage may occur to devices subjected to high energy electrostatic discharges.
WARNING!
The ADSP-21msp58/59 features proprietary ESD protection circuitry to dissipate high energy
discharges (Human Body Model).
Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.
ESD SENSITIVE DEVICE
TIMING PARAMETERS
GENERAL NOTES
MEMORY REQUIREMENTS
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
This chart links common memory device specification
names and ADSP-21msp58/59 timing parameters for your
convenience.
TIMING NOTES
tASW
Switching characteristics specify how the processor changes its
signals. You have no control over this timing; it is dependent on
the internal design. Timing requirements apply to signals that
are controlled outside the processor, such as the data input for a
read operation.
Timing requirements guarantee that the processor operates correctly with another device. Switching characteristics tell you
what the device will do under a given circumstance. Also, use the
switching characteristics to ensure any timing requirement of a
device connected to the processor (such as memory) is satisfied.
Parameter
Name
Function
tAW
tWRA
tDW
tDH
tRDD
tAA
–22–
A0-A13, DMS, PMS
Setup before WR Low
A0-A13, DMS, PMS Setup
before WR Deasserted
A0-A13, DMS, PMS
Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0-A13, DMS, PMS,
BMS to Data Valid
Common
Memory Device
Specification Name
Address Setup to
Write Start
Address Setup
to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
REV. 0
ADSP-21msp58/59
FREQUENCY RESPONSE
Frequency
(Hz)
ADC
Max
(dB)
ADC
Min
(dB)
DAC
Max
(dB)
DAC
Min
(dB)
0+
75
150
300
1000
2000
3000
3400
3700
3850
4000
–60.00
–25.00
+0.266
+0.272
+0.000
+0.050
–0.200
–0.300
–0.375
–25.00
–60.00
N/A
N/A
–0.134
–0.128
+0.000
–0.350
–0.600
–0.700
–0.775
N/A
N/A
–60.00
–25.00
+0.015
+0.030
+0.000
+0.050
–0.050
–0.090
–0.120
–25.00
–60.00
N/A
N/A
–0.185
–0.170
+0.000
–0.200
–0.300
–0.340
–0.370
N/A
N/A
NOTES
All specifications relative to absolute gain @ 1.0 kHz.
ADC and DAC high-pass filters inserted.
ADC specifications do not include RC filter attenuation and assumes an ac coupled input (see “Analog Test Conditions”
for RC filter details).
NOISE & DISTORTION
Parameter
Min
Max
Unit
Test Condition
–60
–70
m, n = 1 and 2; fa = 984; fb = 1047
m, n = 1 and 2; fa = 984; fb = 1047
–65
dB
dB
dBm0
dBm0
dB
DAC Crosstalk1
–65
dB
ADC Power Supply Rejection1
–55
dB
DAC Power Supply Rejection1
–55
dB
ADC Group Delay1
DAC Group Delay1
ADC SNR and THD
DAC SNR and THD
1
1
ms
ms
dB
dB
ADC Intermodulation Distortion
DAC Intermodulation Distortion
ADC Idle Channel Noise
DAC Idle Channel Noise
ADC Crosstalk1
65
72
65
72
ADC input signal level: 1.0 kHz, 0 dBm0
DAC input at idle.
ADC input signal level: analog ground
DAC output signal level: 1.0 kHz, 0 dBm0
Input signal level at VCC and VDD pins:
1.0 kHz, 100 mV p-p sine wave
Input signal level at VCC and VDD pins:
1.0 kHz, 100 mV p-p sine wave
300 Hz–3000 Hz
300 Hz–3000 Hz
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
NOTE
1
Guaranteed but not tested.
100
100
ADC SNR + THD
DAC SNR + THD
PEAK @
72dB
80
PEAK @
65dB
SNR + THD – dB
SNR + THD – dB
80
60
40
60
40
20dB
SLOPE =
20dBm0
SLOPE =
20
0
–60
–50
–40
–30
–20
VIN – dBm0
–10
0
0
–60
10
–50
3.17
Figure 14. SNR + THD vs. VIN
REV. 0
20dB
20dBm0
20
–23–
–40
–30
–20
VIN – dBm0
–10
0
10
3.17
ADSP-21msp58/59
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
ADC
RI
VINMAX
DAC:
RO
VOOFF
VO
RL
Reference Buffer:
Voltage Reference (VREF)
Output Impedence1
Capacitive Load1
PSRR1
Parameter
Min
Input Resistance1, 2 at VINNORM, VINAUX
Maximum Input Range1, 3
Output Resistance1, 4
Output DC Offset5
Maximum Voltage Output Swing (p-p) Across RL
Single-Ended1
Differential1
Load Resistance1, 4
Typ
Max
Unit
3.156
kΩ
V p-p
400
Ω
mV
200
2.5
–400
3.156
6.312
V
V
kΩ
2.75
V
Ω
nf
dB
2
2.25
250
10
55
NOTES
Test conditions for all analog interface tests: ADC PGA bypassed, DAC PGA set to 0 dB gain, with 2 k Ω load on analog output (VOUT P, VOUTN), VCC = 5.0 V.
1
Guaranteed but not tested.
2
Varies with PGA setting.
3
At input to sigma-delta modulator of ADC.
4
At VOUT P, VOUTN.
5
Between VOUT P and VOUTN.
GAIN
Parameter
Min
Typ
Max
Unit
Test Conditions
ADC Absolute Gain
ADC Gain Tracking Error
ADC PGA Relative Gain
DAC Absolute Gain
DAC Gain Tracking Error
DAC PGA Relative Gain
–0.7
–0.1
–0.6
–0.75
–0.1
–0.6
0
0
0
0
0
0
0.7
0.1
0.6
0.75
0.1
0.6
dBm0
dBm0
dBm0
dBm0
dBm0
dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 to –50 dBm0
1.0 kHz
1.0 kHz, 0 dBm0
1.0 kHz, +3 to –50 dBm0
1.0 kHz
–24–
REV. 0
ADSP-21msp58/59
Parameter
Min
Max
Unit
76.92
20
20
125
ns
ns
ns
Clock Signals
tCK is defined as 0.5 tCKI. The ADSP-21msp58/59 uses
an input clock with a quency equal to half the instruction
rate; a 13 MHz input clock (which is equivalent to 76.92 ns)
yields a 38.46 ns processor cycle (equivalent to 26 MHz).
tCK values within the range of 0.5 tCKI period should be
substituted for all relevant timing parameters to obtain
specification value. Example: tCKH = 0.5tCK – 7 ns
= 0.5 (38.46 ns) – 7 ns = 12.23 ns.
Timing Requirement:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
Switching Characteristic:
CLKOUT Width Low
tCKL
tCKH
CLKOUT Width High
tCKOH
CLKIN High to CLKOUT High
0.5tCK – 7
0.5tCK – 7
0
Control Signals
Timing Requirement:
tRSP
5tCK1
RESET Width Low
20
ns
NOTES
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including
crystal oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 15. Clock Signals
REV. 0
–25–
ns
ns
ns
ADSP-21msp58/59
Parameter
Min
Max
Unit
Interrupts and Flags
Timing Requirement:
tIFS
IRQx or FI Setup before CLKOUT Low1, 2, 3
tIFH
IRQx or FI Hold after CLKOUT High1, 2, 3
0.25tCK + 15
0.25tCK
Switching Characteristics:
Flag Output Hold after CLKOUT Low4
tFOH
tFOD
Flag Output Delay from CLKOUT Low4
ns
ns
0.5tCK – 7
0.5tCK + 5
ns
ns
NOTES
1
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, and IRQ2.
4
Flag Output = FL0 and FO.
CLKOUT
t FOD
t FOH
FLAG
OUTPUTS
t I FH
IRQ x
FI
t I FS
Figure 16. Interrupts and Flags
–26–
REV. 0
ADSP-21msp58/59
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirement:
tBH
BR Hold after CLKOUT High1
tBS
BR Setup before CLKOUT Low1
0.25tCK + 2
0.25tCK + 17
Switching Characteristic:
tSD
CLKOUT High to DMS, PMS, BMS,
RD, WR Disable
tSDB
DMS, PMS, BMS, RD, WR
Disable to BG Low
tSE
BG High to DMS, PMS, BMS,
RD, WR Enable
tSEC
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
ns
ns
0.25tCK + 10
ns
0
ns
0
ns
0.25tCK – 7
ns
NOTES
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
t BH
CLKOUT
BR
t BS
CLKOUT
PMS, DMS,
BMS,RD,
WR
tSEC
t SD
BG
t SDB
t SE
Figure 17. Bus Request–Bus Grant
REV. 0
–27–
ADSP-21msp58/59
Parameter
Min
Max
Unit
0.5tCK – 11 + w
0.75tCK – 12 + w
ns
ns
ns
Memory Read
Timing Requirement:
tRDD
RD Low to Data Valid
tAA
A0-A13, PMS, DMS, BMS to Data Valid
tRDH
Data Hold from RD High
0
Switching Characteristic:
tRP
RD Pulse Width
tCRD
CLKOUT High to RD Low
tASR
A0-A13, PMS, DMS, BMS Setup before RD Low
tRDA
A0-A13, PMS, DMS, BMS Hold after RD Deasserted
tRWR
RD High to RD or WR Low
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 6
0.25tCK – 3
0.5tCK – 5
0.25tCK + 7
ns
ns
ns
ns
NOTE
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS,
BMS
t RDA
RD
t RP
tASR
tCRD
t RWR
D
tROD
tRDH
tAA
WR
Figure 18. Memory Read
–28–
REV. 0
ADSP-21msp58/59
Parameter
Min
Max
Unit
Memory Write
Switching Characteristic:
tDW
Data Setup before WR High
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE
WR Low to Data Enabled
tASW
A0-A13, DMS, PMS Setup before WR Low
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
tAW
A0-A13, DMS, PMS, Setup before WR Deasserted
tWRA
A0-A13, DMS, PMS Hold after WR Deasserted
tWWR
WR High to RD or WR Low
0.5tCK – 7 + w
0.25tCK – 2
0.5tCK – 5 + w
0
0.25tCK – 6
0.25tCK – 6
0.25tCK – 5
0.75tCK – 9 + w
0.25tCK – 3
0.5tCK – 5
0.25tCK + 7
NOTE
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
t WRA
WR
t WWR
t WP
tASW
t AW
t DH
tCWR
D
tWDE
t DW
RD
Figure 19. Memory Write
REV. 0
–29–
t DDR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21msp58/59
Parameter
Min
Max
Unit
Serial Ports
Timing Requirement:
tSCK
SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH
DR/TFS/RFS Hold after SCLK Low
tSCP
SCLKin Width
50
4
7
20
Switching Characteristic:
CLKOUT High to SCLKout
tCC
tSCDE
SCLK High to DT Enable
tSCDV
SCLK High to DT Valid
tRH
TFS/RFSout Hold after SCLK High
tRD
TFS/RFSout Delay from SCLK High
tSCDH
DT Hold after SCLK High
tTDE
TFS(Alt) to DT Enable
tTDV
TFS(Alt) to DT Valid
tSCDD
SCLK High to DT Disable
tRDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
ns
ns
ns
ns
0.25tCK
0
0.25tCK + 10
15
0
15
0
0
14
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
t CC
t CC
t SCK
SCLK
t SCP
t SCS
t SCH
t SCP
DR
RFSIN
TFSIN
t RD
t RH
RFSOUT
TFSOUT
t SCDV
t SCDD
t SCDH
t SCDE
DT
t TDE
t TDV
TFS
alternate
frame mode
t RDV
RFS
multichannel
mode, frame
delay 0 (MFD = 0)
Figure 20. Serial Ports
–30–
REV. 0
ADSP-21msp58/59
Parameter
Min
Max
Unit
Host Interface Port
Separate Data and Address (HMD1 = 0)
Read Strobe and Write Strobe (HMD0 = 0)
Timing Requirement:
tHSU
HA2-0 Setup before Start of Write or Read1, 2
tHDSU
Data Setup before End of Write3
tHWDH
Data Hold after End of Write3
tHH
HA2-0 Hold after End of Write or Read3, 4
tHRWP
Read or Write Pulse Width5
5
5
3
3
20
Switching Characteristic:
HACK Low after Start of Write or Read1, 2
tHSHK
tHKH
HACK Hold after End of Write or Read3, 4
tHDE
Data Enabled after Start of Read2
tHDD
Data Valid after Start of Read2
tHRDH
Data Hold after End of Read4
tHRDD
Data Disabled after End of Read4
ns
ns
ns
ns
ns
0
0
0
15
15
18
0
7
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
HA2–0
ADDRESS
tHRWP
HSEL
tHSU
HOST WRITE CYCLE
tHH
HWR
HACK
tHKH
tHSHK
DATA
HD7–0
tHWDH
tHDSU
HA2–0
ADDRESS
tHRWP
HSEL
tHSU
HOST READ CYCLE
tHH
HRD
HACK
tHSHK
tHKH
DATA
HD7–0
tHDE
tHDD
tHRDH
t HRDD
Figure 21. Host Interface Port (HMD1 = 0, HMD0 = 0)
REV. 0
–31–
ns
ns
ns
ns
ns
ns
ADSP-21msp58/59
Parameter
Min
Max
Unit
Host Interface Port
Separate Data and Address (HMD1 = 0)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
tHSU
HA2-0, HRW Setup before Start of Write or Read1
tHDSU
Data Setup before End of Write2
tHWDH
Data Hold after End of Write2
tHH
HA2-0, HRW Hold after End of Write or Read2
tHRWP
Read or Write Pulse Width3
5
5
3
3
20
Switching Characteristic:
HACK Low after Start of Write or Read1
tHSHK
tHKH
HACK Hold after End of Write or Read2
tHDE
Data Enabled after Start of Read1
tHDD
Data Valid after Start of Read1
tHRDH
Data Hold after End of Read2
tHRDD
Data Disabled after End of Read2
ns
ns
ns
ns
ns
0
0
0
15
15
18
0
7
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High and HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
HA2–0
ADDRESS
t HRWP
HSEL
t HSU
HOST WRITE CYCLE
HRW
t HH
HDS
HACK
t HSHK
t HKH
DATA
HD7–0
t HWDH
t HDSU
HA2–0
ADDRESS
t HRWP
HSEL
t HSU
HRW
HOST READ CYCLE
t HH
HDS
HACK
t HSHK
t HKH
DATA
HD7–0
t HDE
t HDD
t HRDH
t HRDD
Figure 22. Host Interface Port (HMD1 = 0, HMD0 =1)
–32–
REV. 0
ADSP-21msp58/59
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 0)
Timing Requirement:
tHALP
ALE Pulse Width
tHASU
HAD15-0 Address Setup, before ALE Low
tHAH
HAD15-0 Address Hold after ALE Low
tHALS
Start of Write or Read after ALE Low1, 2
tHDSU
HAD15-0 Data Setup before End of Write3
tHWDH
HAD15-0 Data Hold after End of Write3
tHRWP
Read or Write Pulse Width5
10
5
2
10
5
3
20
Switching Characteristic:
tHSHK
HACK Low after Start of Write or Read1, 2
tHKH
HACK Hold after End of Write or Read3, 4
tHDE
HAD15-0 Data Enabled after Start of Read2
tHDD
HAD15-0 Data Valid after Start of Read2
tHRDH
HAD15-0 Data Hold after End of Read
tHRDD
HAD15-0 Data Disabled after End of Read4
ns
ns
ns
ns
ns
ns
ns
0
0
0
15
15
18
0
7
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
ALE
tHALP
HSEL
HOST WRITE CYCLE
t H R WP
tHALS
HWR
tHKH
tHSHK
HACK
HAD7–0
tHASU tHAH
ADDRESS
DATA
tHDSU
t H WD H
ALE
tHALP
t H R WP
HSEL
tHALS
HOST READ CYCLE
HRD
t HSHK
HACK
HAD7–0
tHASU tHAH
tHKH
t HDE
ADDRESS
t HRDH
DATA
t HDD
t HRDD
Figure 23. Host Interface Port (HMD1 = 1, HMD0 = 0)
REV. 0
–33–
ns
ns
ns
ns
ns
ns
ADSP-21msp58/59
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
tHALP
ALE Pulse Width
tHASU
HAD15-0 Address Setup before ALE Low
tHAH
HAD15-0 Address Hold after ALE Low
tHALS
Start of Write or Read after ALE Low1
tHSU
HRW Setup before Start of Write or Read1
tHDSU
HAD15-0 Data Setup before End of Write2
tHWDH
HAD15-0 Data Hold after End of Write2
tHH
HRW Hold after End of Write or Read2
tHRWP
Read or Write Pulse Width3
10
5
2
10
5
5
3
3
20
Switching Characteristic:
tHSHK
HACK Low after Start of Write or Read1
tHKH
HACK Hold after End of Write or Read2
tHDE
HAD15-0 Data Enabled after Start of Read1
tHDD
HAD15-0 Data Valid after Start of Read1
tHRDH
HAD15-0 Data Hold after End of Read2
tHRDD
HAD15-0 Data Disabled after End of Read2
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
15
15
18
0
7
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High and HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
ALE
t HALP
t HRWP
HSEL
t HALS
HOST WRITE CYCLE
t HH
HRW
t HSU
HDS
t HKH
t HSHK
HACK
HAD7–0
t HASU t HAH
ADDRESS
DATA
t HDSU
t HWDH
ALE
t HALP
t HRWP
HSEL
t HALS
HRW
t HH
t HSU
HOST READ CYCLE
HDS
t HKH
t HSHK
HACK
t HASU t HAH
t HDE
HAD7–0
ADDRESS
t HRDH
DATA
t HDD
t HRDD
Figure 24. Host Interface Port (HMD1 = 1, HMD0 = 1)
–34–
REV. 0
ADSP-21msp58/59
ENVIRONMENTAL CONDITIONS
frequency, the codec performance changes and the performance
specifications cannot be guaranteed. The codec filter characteristics, however, scale approximately linearly with frequency.
Ambient Temperature Rating:
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
Package
θJA
If the codec is disabled, then the processor can be used at any
allowed input frequency. The power consumption of the ADSP21msp58/59 at these frequencies is shown in Figure 25.
POWER, INTERNAL
θJC
θCA
550
INTERNAL
(80% NOMINAL LOADING)
CODEC INACTIVE
MAX VALUES
500
450
50°C/W
2°C/W
48°C/W
POWER (PINT) – mW
TQFP
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
C = load capacitance, f = output switching frequency.
•
•
2
6
100
10
× 26 MHz
× 13 MHz
× 13 MHz
× 26 MHz
14
18
1/tCK – MHz
22
26
30
50
100mW
IDLE 0
CODEC INACTIVE
MAX VALUES
83mW
VDD = 5.5V
.0V
70
V DD
=5
60
69mW
57mW
50
49mW
40
42mW
2
6
VDD = 4.5V
10
×f
14
18
1/tCK – MHz
22
26
30
3
=
=
=
=
52 mW
30 mW
4 mW
6 mW
92 mW
POWER, IDLE n MODES
70
IDLEs @ 5.0V
CODEC INACTIVE
TYPICAL VALUES
60
Total power dissipation for this example is PINT + 92 mW.
Typical Power Consumption
The typical power consumption can be calculated from the following data, taken at 5.0 V and +25°C. Dynamic VDD data was
taken while executing 80% type 1 multifunction instructions, on
random data.
Parameter
IDD Digital Supply Current (Idle, Codec Powered Up)
IDD Digital Supply Current (Idle)
IDD Digital Supply Current (Dynamic, Codec Powered Up)
IDD Digital Supply Current (Dynamic)
IDD Digital Supply Current (Powerdown)
Typ
19 mA
13 mA
83 mA
78 mA
10 µA
ICC Analog Supply Current (Dynamic)
15 mA
65mW
50
40
IDLE (16)
37mW IDLE (32)
35mW IDLE (64)
IDLE (128)
30
29mW
21mW
20mW
20
10
2
6
10
14
18
1/tCK – MHz
22
26
30
VALID FOR ALL TEMPERATURE GRADES.
1
2
Analog Devices recommends that the ADSP-21msp58/59
is used with a 13 MHz input clock. Below this input clock
REV. 0
150
118mW
80
30
× 52 V
× 52 V
× 52 V
× 52 V
VDD = 4.5V
90
POWER (PIDLEN) – mW
× 10 pF
× 10 pF
× 10 pF
× 10 pF
250
200
191mW
154mW
100
Total Power Dissipation = PINT + (C × VDD2 × f )
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 25).
(C × VDD2 × f ) is calculated for each output:
8
9
1
1
200
300
2
The application operates at VDD = 5.0 V and tCK = 76.92 ns.
Address, DMS
Data Output, WR
RD
CLKOUT
250
350
POWER, IDLE
Each address and data pin has a 10 pF total load at the pin.
× VDD
V DD
.0
=5
110
External data memory writes occur every other cycle with
50% of the data pins switching.
2
400
310mW
V
300
50
External data memory is accessed every cycle with 50% of the
address pins switching.
# of
Pins × C
350
POWER (PIDLE) – mW
•
450
391mW
VDD = 5.5V
100
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
480mW 500
400
150
Example:
•
1
550
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-21msp58/59 STATE OF OPERATION DURING EXECUTION OF
IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.
3 TYPICAL POWER DISSIPATION AT 5.0V V
DD DURING EXECUTION OF IDLE n
INSTRUCTION (CLOCK FREQUENCY REDUCTION). POWER REFLECTS DEVICE
OPERATING WITH CLKOUT DISABLED.
Figure 25. Power vs. Internal Processor Frequency
–35–
ADSP-21msp58/59
CAPACITIVE LOADING
TEST CONDITIONS
Digital
Figures 26 and 27 show the capacitive loading characteristics of
the ADSP-21msp58/59.
Figure 28 shows the voltage reference levels and Figure 29
shows the equivalent device loading for the ac measurements.
28
RISE TIME (0.4V – 2.4V) – ns
3.0V
1.5V
0.0V
INPUT
24
VDD = 4.5V
20
2.0V
1.5V
0.8V
OUTPUT
16
12
Figure 28. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
8
4
IOL
0
25
50
75
100
CL – pF
125
150
175
TO
OUTPUT
PIN
Figure 26. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
+1.5V
50pF
VALID OUTPUT DELAY OR HOLD – ns
+14
IOH
+12
+10
Figure 29. Equivalent Device Loading for AC Measurements (Including All Fixtures)
+8
+6
Analog
+4
Figure 30 shows the analog test conditions.
+2
2.2kΩ
1.0µF
1.0µF
2200pF
NPO
–2
–4
DECOUPLE
VINNORM
NOMINAL
25
50
75
100
CL – pF
125
150
175
2.2kΩ
1.0µF
REF_CAP
VINAUX
10µF
0.1µF
2200pF
NPO
Figure 27. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
Figure 30. Analog Test Conditions
–36–
REV. 0
ADSP-21msp58/59
Output Disable Time
Output Enable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitative load, CL, and the current load, iL, on the output pin. It can be approximated by the
following equation:
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
t DECAY
REFERENCE
SIGNAL
t M EASURED
C • 0.5V
= L
iL
tENA
tDIS
VOH (MEASURED)
from which
OUTPUT
t DIS = t MEASURED – t DECAY
VOL (MEASURED)
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
VOH
(MEASURED)
VOH (MEASURED) –0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOL
(MEASURED)
tDECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
HERE
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 31. Output Enable/Disable
REV. 0
–37–
ADSP-21msp58/59
PIN CONFIGURATION
VOUTP
VREF
VCC
BR
PWD
BMODE
GNDA
VOUTN
D3
D2
D1
D0
BG
GND
D7
D6
D5
D4
D12
D11
D10
D9
D8
D14
D13
100-Lead Thin Plastic Quad Flatpack (TQFP)
100
76
1
75
D15
D16
D17
VINNORM
DECOUPLE
VINAUX
D18
D19
D20
D21
REF_FILTER
GNDA
MMAP
RESET
D22
D23
VDD
GND
PMS
DMS
BMS
RD
WR
HD7
HD6
HD5
HD4
IRQ2
HMD0
HMD1
HACK
FL0
SCLK1
DR1/FI
RFS1/IRW0
TOP VIEW
(PINS DOWN)
TFS1/IRQ1
DT1/FO
GND
SCLK0
DR0
FRS0
TFS0
DT0
VDD
HD3
HD2
HD1
HD0
HA2/ALE
A13
25
51
–38–
A10
A11
A12
A6
A7
A8
A9
A1
A2
A3
A4
A5
VDD
A0
GND
XTAL
CLKIN
GND
HSEL
HWR/HDS
HRD/HRW
CLKOUT
VDD
50
HA1
HA0
26
REV. 0
ADSP-21msp58/59
100-Lead Thin Plastic Quad Flatpack (TQFP) Pinout
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D15
D16
D17
D18
D19
D20
D21
D22
D23
VDD
GND
PMS
DMS
BMS
RD
WR
HD7
HD6
HD5
HD4
HD3
HD2
HD1
HD0
HA2/ALE
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
HA1
HA0
HSEL
HWR/HDS
HRD/HRW
CLKOUT
VDD
GND
XTAL
CLKIN
GND
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
A13
VDD
DT0
TFS0
RFS0
DR0
SCLK0
GND
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
DR1/FI
SCLK1
FL0
HACK
HMD1
HMD0
IRQ2
RESET
MMAP
GNDA
REF_FILTER
VINAUX
DECOUPLE
VINNORM
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VCC
VREF
VOUTP
VOUTN
GND
BMODE
PWD
BR
BG
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
REV. 0
–39–
ADSP-21msp58/59
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches)
100-Lead Metric Thin Plastic Quad Flat Pack (TQFP)
0.75 (0.030)
0.50 (0.019)
100
1
C2030–4–4/95
16.25 (0.640)
SQ
15.75 (0.620)
14.05 (0.553)
SQ
13.95 (0.549)
1.60 (0.063)
MAX
76
75
SEATING
PLANE
TOP VIEW
(PINS DOWN)
25
0.1 (0.004)
51
50
26
0.15 (0.006)
0.05 (0.002)
0.56 (0.022)
0.44 (0.018)
0.057 (1.45)
0.053 (1.35)
0.27 (0.011)
0.17 (0.007)
12.06 (0.475) SQ
ORDERING GUIDE*
Part Number
Ambient
Temperate
Range
Instruction
Rate
(MIPS)
Package
Description
Package
Option
ADSP-21msp58BST-104
–40°C to +85°C
26
100-Lead TQFP
ST-100
PRINTED IN U.S.A.
*Refer to the section titled “Ordering Procedure for ADSP-21msp59 ROM Processors” for information about ordering ROM coded parts.
–40–
REV. 0
Similar pages