ON CM1213A-04SO 4-channel low capacitance esd protection array Datasheet

CM1213A-04SO,
SZCM1213A-04SO
4-Channel
Low Capacitance
ESD Protection Array
Product Description
CM1213A−04SO has been designed to provide ESD protection for
electronic components or subsystems requiring minimal capacitive
loading. This device is ideal for protecting systems with high data and
clock rates or for circuits requiring low capacitive loading. Each ESD
channel consists of a pair of diodes in series which steer the positive or
negative ESD current pulse to either the positive (VP) or negative (VN)
supply rail. A Zener diode is embedded between VP and VN, offering
two advantages. First, it protects the VCC rail against ESD strikes, and
second, it eliminates the need for a bypass capacitor that would
otherwise be needed for absorbing positive ESD strikes to ground.
This device will protect against ESD pulses up to 8 kV per the
IEC 61000−4−2 standard.
This device is particularly well-suited for protecting systems using
high-speed ports such as USB 2.0, IEEE1394 (Firewire®, iLinkt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
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SC−74
SO SUFFIX
CASE 318F
MARKING DIAGRAM
VP
CH1
CH2
CH3
CH4
VN
CM1213A−04SO
Features
• Four Channels of ESD Protection
• Provides ESD Protection to IEC61000−4−2 Level 4
•
•
•
•
•
•
•
MARKING DIAGRAM
±8 kV Contact Discharge
Low Channel Input Capacitance of 0.85 pF Typical
Minimal Capacitance Change with Temperature and Voltage
Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for
Differential Dignals
Zener Diode Protects Supply Rail and Eliminates the Need for
External By-pass Capacitors
Each I/O Pin Can Withstand Over 1000 ESD Strikes*
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb-Free and RoHS Compliant
♦
Applications
• USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals
• IEEE1394 Firewire® Ports at 400 Mbps/800 Mbps
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
234MG
G
1
234
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
CM1213A−04SO
SC−74
(Pb−Free)
3,000 /
Tape & Reel
SZCM1213A−04SO
SC−74
(Pb−Free)
3,000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
**Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 1
1
Publication Order Number:
CM1213A−04SO/D
CM1213A−04SO, SZCM1213A−04SO
PACKAGE/PINOUT DIAGRAMS
Table 1. PIN DESCRIPTIONS
Pin
Name
Type
1
CH1
I/O
Description
Top View
ESD Channel
Negative Voltage Supply Rail
CH1
1
VN
GND
3
CH2
I/O
ESD Channel
VN
2
4
CH3
I/O
ESD Channel
CH2
3
5
VP
PWR
6
CH4
I/O
Positive Voltage Supply Rail
234
2
6
CH4
5
VP
4
CH3
6−Lead SC−74
ESD Channel
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
6.0
V
Operating Temperature Range
–40 to +85
°C
Storage Temperature Range
–65 to +150
°C
(VN − 0.5) to (VP + 0.5)
V
Operating Supply Voltage (VP − VN)
DC Voltage at any channel input
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Package Power Rating
Rating
Units
–40 to +85
°C
225
mW
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
3.3
5.5
V
8.0
mA
VP
Operating Supply Voltage (VP−VN)
IP
Operating Supply Current
(VP−VN) = 3.3 V
VF
Diode Forward Voltage
IF = 8 mA; TA = 25°C
0.90
Channel Leakage Current
TA = 25°C; VP = 5 V, VN = 0 V
±0.1
Channel Input Capacitance
At 1 MHz, VIN = 0 V (Note 2)
ILEAK
CIN
DCIO
Channel I/O ti I/O Capacitance
VESD
ESD Protection
Peak Discharge
Voltage at any channel input, in system
Contact discharge per
IEC 61000−4−2 standard
VCL
RDYN
1.5
V
±1.0
mA
2.0
pF
pF
kV
TA = 25°C (Notes 2 and 3)
Channel Clamp Voltage
Positive Transients
Negative Transients
TA = 25°C, IPP = 1A, tP = 8/20 mS
(Note 2)
Dynamic Resistance
Positive Transients
Negative Transients
TA = 25°C, IPP = 1A, tP = 8/20 mS
(Note 2)
±8
V
+9.9
–1.6
W
0.96
0.5
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All parameters specified at TA = –40°C to +85°C unless otherwise noted.
2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.
3. These measurements performed with no external capacitor on VP (VP floating).
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2
CM1213A−04SO, SZCM1213A−04SO
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)
Figure 2. Typical Variation of CIN vs. Temp
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)
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3
CM1213A−04SO, SZCM1213A−04SO
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)
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4
CM1213A−04SO, SZCM1213A−04SO
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power
supply is represented by L1 and L2. The voltage VCL on the line being protected is:
VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be
approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1213A has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance
L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip
capacitor be connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.
L2
POSITIVE SUPPLY RAIL
VP
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
D1
0.22 mF
ONE
CHANNEL
D2 OF
CM1213
VN
VCC
PATH OF ESD CURRENT PULSE IESO
LINE BEING
PROTECTED
L1
0A
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
CHANNEL
INPUT
25 A
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
VCL
GROUND RAIL
CHASSIS GROUND
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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5
CM1213A−04SO, SZCM1213A−04SO
PACKAGE DIMENSIONS
SC−74
CASE 318F−05
ISSUE N
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. 318F−01, −02, −03, −04 OBSOLETE. NEW
STANDARD 318F−05.
D
6
5
4
2
3
E
HE
1
DIM
A
A1
b
c
D
E
e
L
HE
b
e
0.05 (0.002)
C
A
L
A1
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.37
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10°
−
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
INCHES
NOM
0.039
0.002
0.015
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
SOLDERING FOOTPRINT*
2.4
0.094
0.95
0.037
1.9
0.074
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
FireWire is a registered trademark of Apple Computer, Inc.
iLink is a trademark of S. J. Electro Systems, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Sales Representative
CM1213A−04SO/D
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