TI1 CDCV304PW 200-mhz general-purpose clock buffer, pci-x compliant Datasheet

CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
www.ti.com
200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT
Check for Samples: CDCV304
FEATURES
•
•
1
•
•
•
•
•
•
General-Purpose and PCI-X 1:4 Clock Buffer
Operating Frequency
– 0 MHz to 200 MHz General-Purpose
Low Output Skew: <100 ps
Distributes One Clock Input to One Bank of
Four Outputs
Output Enable Control that Drives Outputs
Low when OE is Low
Operates from Single 3.3-V Supply or 2.5-V
Supply
PCI-X Compliant
8-Pin TSSOP Package
TSSOP
PW PACKAGE
(TOP VIEW)
1
2
3
4
CLKIN
OE
1Y0
GND
8
7
6
5
1Y3
1Y2
VDD
1Y1
DESCRIPTION
The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one
input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X
applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X
specifications.
The CDCV304 is characterized for operation from –40°C to 85°C for automotive and industrial applications.
FUNCTIONAL BLOCK DIAGRAM
OE
CLKIN
2
Logic
Control
3
1
1Y0
5
1Y1
7
1Y2
8
1Y3
Table 1. FUNCTION TABLE
INPUTS
OUTPUTS
CLKIN
OE
1Y[0:3]
L
L
L
H
L
L
L
H
L
H
H
H
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2000–2011, Texas Instruments Incorporated
CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TERMINAL FUNCTIONS
TERMINAL
I/O
NAME
NO.
1Y[0:3]
3, 5, 7, 8
CLKIN
GND
DESCRIPTION
O
Buffered output clocks
1
I
Input reference frequency
4
Power
OE
2
I
VDD
6
Power
Ground
Output enable control
Supply
THERMAL INFORMATION (1)
THERMAL AIR FLOW (CFM)
CDCV304PW 8-PIN TSSOP
0
150
250
500
RθJA
High K
149
142
138
132
RθJA
Low K
230
185
170
150
RθJB
High K
102.0
RθJC
High K
43.7
ψ
JT
High K
1.8
ψ
JB
High K
100.2
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
–0.5 V to 4.3 V
Supply voltage range, VDD
Input voltage range, VI
(2) (3)
Output voltage range, VO
–0.5 V to VDD + 0.5 V
(2) (3)
–0.5 V to VDD + 0.5 V
Input clamp current, IIK (VI < 0 or VI> VDD)
±50 mA
Output clamp current, IOK (VO < 0 or VO > VDD)
±50 mA
Continuous total output current, IO (VO = 0 to VDD)
±50 mA
Package thermal impedance, θJA: PW package
230.5°C/W
–65°C to 150°C
Storage temperature range Tstg
(1)
(2)
(3)
2
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
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CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
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RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VDD
NOM
MAX
2.3
Low-level input voltage, VIL
High-level input voltage, VIH
V
V
0
Low-level output current, IOL
V
0.3 x VDD
0.7 x VDD
Input voltage, VI
High-level output current, IOH
UNIT
3.6
VDD
VDD = 2.5 V
–12
VDD = 3.3 V
–24
VDD = 2.5 V
12
VDD = 3.3 V
24
–40
Operating free-air temperature, TA
V
mA
mA
°C
85
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fclk
TEST CONDITIONS
Clock frequency
MIN
TYP
0
MAX
UNIT
200
MHz
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
VOL
Input voltage
High-level output voltage
Low-level output voltage
IOH
High-level output current
IOL
Low-level output current
II
Input current
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
–1.2
V
VDD = 3 V,
II = –18 mA
VDD = 2.3 V,
IOH = –8 mA
VDD = 2.3 V,
IOH = –16 mA
VDD = min to max,
IOH = –1 mA
VDD = 3 V,
IOH = –24 mA
2
VDD = 3 V,
IOH = –12 mA
2.4
VDD = 2.3 V,
IOL = 8 mA
0.5
VDD = 2.3 V,
IOL = 16 mA
0.7
VDD = min to max,
IOL = 1 mA
0.2
VDD = 3 V,
IOL = 24 mA
0.8
VDD = 3 V,
IOL = 12 mA
0.55
VDD = 3 V,
VO = 1 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3 V,
VO = 2 V
VDD = 3.3 V,
VO = 1.65 V
1.8
1.5
VDD – 0.2
V
–50
mA
–55
60
mA
70
±5
VI = VO or VDD
V
f = 67 MHz,
VDD = 2.7 V
28
f = 67 MHz,
VDD = 3.6 V
37
μA
IDD
Dynamic current, see Figure 5
CI
Input capacitance
VDD = 3.3 V,
VI = 0 V or VDD
3
pF
CO
Output capacitance
VDD = 3.3 V,
VI = 0 V or VDD
3.2
pF
(1)
mA
All typical values are with respect to nominal VDD and TA = 25°C.
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CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
www.ti.com
SWITCHING CHARACTERISTICS
VDD = 2.5 V ± 10%, CL= 10 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
2
2.9
4.5
2
3
4.5
UNIT
tPLH
Low-to-high propagation delay
tPHL
High-to-low propagation delay
tsk(o)
Output skew (2)
50
150
tr
Output rise slew rate
1.5
2.2
4
V/ns
tf
Output fall slew rate
1.5
2.2
4
V/ns
MIN
TYP (1)
MAX
UNIT
1.8
2.4
3
1.8
2.5
3
50
100
(1)
(2)
See Figure 1 and Figure 2
See Figure 3
ns
ps
All typical values are with respect to nominal VDD.
The tsk(o) specification is only valid for equal loading of all outputs.
SWITCHING CHARACTERISTICS
VDD = 3.3 V ± 10%, CL= 10 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Low-to-high propagation delay
tPHL
High-to-low propagation delay
tsk(o)
Output skew (2)
tjitter
Additive phase jitter from input to output 1Y0
tsk(p)
Pulse skew
tsk(pr)
Process skew
tsk(pp)
Part-to-part skew
Clock high time, see Figure 4
tlow
Clock low time, see Figure 4
tr
Output rise slew rate (3)
(1)
(2)
(3)
4
Output fall slew rate
12 kHz to 5 MHz, fout = 30.72 MHz
63
12 kHz to 20 MHz, fout = 125 MHz
56
VIH = VDD, VIL = 0 V
thigh
tf
See Figure 1 and Figure 2
(3)
66 MHz
6
140 MHz
3
66 MHz
6
140 MHz
3
ns
ps
fs rms
150
ps
0.2
0.3
ns
0.25
0.4
ns
ns
ns
VO = 0.4 V to 2 V
1.5
2.7
4
V/ns
VO = 2 V to 0.4 V
1.5
2.7
4
V/ns
All typical values are with respect to nominal VDD.
The tsk(o) specification is only valid for equal loading of all outputs.
This symbol is according to PCI-X terminology.
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CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
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PARAMETER MEASUREMENT INFORMATION
VDD
140 Ω
Yn
10 pF
140 Ω
Figure 1. Test Load Circuit
VDD
50% VDD
CLKIN
0V
tPLH
tPHL
0.6 VDD
0.6 VDD
50% VDD
50% VDD
0.2 VDD
1Y0 − 1Y3
VOH
0.2 VDD
tr
VOL
tf
Figure 2. Voltage Waveforms Propagation Delay (tpd) Measurements
50% VDD
Any Y
50% VDD
Any Y
tsk(0)
Figure 3. Output Skew
tcyc
PARAMETER
VIH(Min)
VIL(Max)
Vtest
VALUE
0.5 VDD
thigh
UNIT
V
0.35 VDD
V
VIH(Min)
0.4 VDD
V
Vtest
0.6 VDD
VIL(Max)
tlow
0.2 VDD
0.4 VDD
Peak to Peak (Minimum)
A.
All parameters in Figure 4 are according to PCI-X 1.0 specifications.
Figure 4. Clock Waveform
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CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
www.ti.com
SUPPLY CURRENT
vs
FREQUENCY
60
ICC − Supply Current − mA
TA = 85°C
Output Load: as in Figure 1
50
VDD = 3.6V
40
VDD = 2.7V
30
20
0
20
40
60
80
100
120
140
160
f − Frequency − MHz
Figure 5.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH − High-Level Output Voltage − V
3.5
3.0
VDD = 3.3 V
TA = 25°C
2.5
2.0
1.5
1.0
0.5
0.0
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
IOH − High-Level Output Current − mA
Figure 6.
6
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CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
www.ti.com
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
3.5
3.0
VDD = 3.3 V
TA = 25°C
2.5
2.0
1.5
1.0
0.5
0.0
−20
0
20
40
60
80
100
120
IOL − Low-Level Output Current − mA
Figure 7.
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CDCV304
SCAS643H – SEPTEMBER 2000 – REVISED FEBRUARY 2011
www.ti.com
REVISION HISTORY
Changes from Revision F (April 2009) to Revision G
•
Added ψ JT and ψ JB specs to the Thermal Information Table and changed RθJB and RθJC specs from 65 and
69 °C/W respectively. ........................................................................................................................................................... 2
Changes from Revision G (January 2011) to Revision H
•
8
Page
Page
Added missing characteristics graphs. ................................................................................................................................. 6
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CDCV304PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCV304PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCV304PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCV304PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCV304PWR
Package Package Pins
Type Drawing
TSSOP
PW
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
7.0
B0
(mm)
K0
(mm)
P1
(mm)
3.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCV304PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
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