AMIS-42665 High-Speed Low Power CAN Transceiver Description The AMIS−42665 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both 12 V and 24 V systems. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. Due to the wide common−mode voltage range of the receiver inputs, the AMIS−42665 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. The AMIS−42665 is a new addition to the CAN high−speed transceiver family and offers the following additional features: http://onsemi.com MARKING DIAGRAM 8 1 1 XXXXX A L Y W G Features • Wake−up (WU) Over Bus • Voltage Source via VSPLIT Pin for Stabilizing the Recessive Bus • • • • • • • • • • • • • © Semiconductor Components Industries, LLC, 2010 April, 2010 − Rev. 8 1 XXXXX ALYW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN ASSIGNMENT TxD 1 8 STB GND 2 7 CANH VCC 3 6 CANL RxD 4 5 VSPLIT AMIS− 42665 • • Level (Further EMC Improvement) Ideal Passive Behavior when Supply Voltage is Removed Extremely Low Current Standby Mode Compatible with the ISO 11898 Standard (ISO 11898−2, ISO 11898−5 and SAE J2284) High Speed (up to 1 Mbps) Ideally Suited for 12 V and 24 V Industrial and Automotive Applications Extremely Low Current Standby Mode with Wake−up via the Bus Low EME Common−Mode Choke is No Longer Required Differential Receiver with Wide Common−Mode Range ($35 V) for High EMS Transmit Data (TxD) Dominant Time−out Function Thermal Protection Bus Pins Protected against Transients in an Automotive Environment Power Down Mode in which the Transmitter is Disabled Bus and VSPLIT Pins Short Circuit Proof to Supply Voltage and Ground Logic Level Inputs Compatible with 3.3 V Devices These are Pb−Free Devices SOIC−8 CASE 751 8 (Top View) PC20040829.1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Publication Order Number: AMIS−42665/D AMIS−42665 Table 1. TECHNICAL CHARACTERISTICS Symbol Parameter Conditions Min Max Unit VCC Power Supply Voltage 4.75 5.25 V VSTB DC Voltage at Pin STB −0.3 VCC V VTxD DC Voltage at Pin TxD −0.3 VCC V VRxD DC Voltage at Pin RxD −0.3 VCC V VCANH DC Voltage at Pin CANH 0 < VCC < 5.25 V; No Time Limit −35 +35 V VCANL DC Voltage at Pin CANL 0 < VCC < 5.25 V; No Time Limit −35 +35 V VSPLIT DC Voltage at Pin VSPLIT 0 < VCC < 5.25 V; No Time Limit −35 +35 V VO(dif)(bus_dom) Differential Bus Output Voltage in Dominant State 42.5 W < RLT < 60 W 1.5 3 V CM−range Input Common−Mode Range for Comparator Guaranteed Differential Receiver Threshold and Leakage Current −35 +35 V VCM−peak Common−Mode Peak −500 500 mV Cload Load Capacitance on IC Outputs 10 pF tpd(rec−dom) Propagation Delay TxD to RxD See Figure 7 90 230 ns tpd(dom−rec) Propagation Delay TxD to RxD See Figure 7 90 245 ns TJ Junction Temperature −40 150 °C See Figures 11 and 12 VCC 3 VCC AMIS−42665 POR 7 1 TxD Timer Thermal Shutdown VCC VCC 8 STB 4 RxD GND VSPLIT Mode & Wake−up Control 5 CANL + COMP − + 2 COMP − Figure 1. Block Diagram http://onsemi.com 2 VSPLIT 6 Driver Control Wake−up Filter CANH PC20050211.1 AMIS−42665 TYPICAL APPLICATION VBAT IN 5V−reg OUT VCC VCC 3 STB 7 8 RxD CAN 4 Controller AMIS− 42665 TxD RLT = 60 W VSPLIT CLT = 47 nF 5 CANL R 2 GND GND PC20040829.3 Figure 2. Application Diagram Table 2. PIN LIST AND DESCRIPTIONS Pin Name Description 1 TxD Transmit Data Input; Low Input → Dominant Driver; Internal Pullup Current 2 GND Ground 3 VCC Supply Voltage 4 RxD Receive Data Output; Dominant transmitter → Low Output 5 VSPLIT Common−Mode Stabilization Output 6 CANL Low−Level CAN Bus Line (Low in Dominant Mode) 7 CANH High−Level CAN Bus Line (High in Dominant Mode) 8 STB Standby Mode Control Input http://onsemi.com 3 CAN BUS 6 1 CANH AMIS−42665 Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Min. Max. Unit −0.3 +7 V VCC Supply Voltage VCANH DC Voltage at Pin CANH 0 < VCC < 5.25 V; No Time Limit −50 +50 V VCANL DC Voltage at Pin CANL 0 < VCC < 5.25 V; No Time Limit −50 +50 V VSPLIT DC Voltage at Pin VSPLIT 0 < VCC < 5.25 V; No Time Limit −50 +50 V VTxD DC Voltage at Pin TxD −0.3 VCC + 0.3 V VRxD DC Voltage at Pin RxD −0.3 VCC + 0.3 V VSTB DC Voltage at Pin STB −0.3 VCC + 0.3 V Vtran(CANH) Transient Voltage at Pin CANH Note 1 −300 +300 V Vtran(CANL) Transient voltage at Pin CANL Note 1 −300 +300 V Vtran(VSPLIT) Transient Voltage at Pin VSPLIT Note 1 −300 +300 V Vesd(CANL/ CANH/VSPLIT) Electrostatic Discharge Voltage at CANH and CANL Pin Note 2 Note 4 −8 −500 +8 +500 kV V Vesd Electrostatic Discharge Voltage at All Other Pins Note 2 Note 4 −5 −500 +5 +500 kV V Latch−up Static Latch−up at all Pins Note 3 120 mA Tstg Storage Temperature −55 +150 °C Tamb Ambient Temperature −40 +125 °C TJ Maximum Junction Temperature −40 +170 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 5). 2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7. 3. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78. 4. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3−1993. Table 4. THERMAL CHARACTERISTICS Symbol Parameter Conditions Value Unit Rth(vj−a) Thermal Resistance from Junction−to−Ambient in SOIC−8 Package In free air 145 K/W Rth(vj−s) Thermal Resistance from Junction−to−Substrate of Bare Die In free air 45 K/W FUNCTIONAL DESCRIPTION AMIS−42665 provides two modes of operation as illustrated in Table 5. These modes are selectable through pin STB. Table 5. OPERATING MODES Pin RXD Low High Mode Pin STB Normal Low Bus Dominant Bus Recessive Standby High Wake−up Request Detected No Wake−up Request Detected Normal Mode Standby Mode In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME. In standby mode both the transmitter and receiver are disabled and a very low−power differential receiver monitors the bus lines for CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 mA. When a wake−up request is http://onsemi.com 4 AMIS−42665 Overtemperature Detection detected by the low−power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of tdbus, the RxD pin is driven low by the transceiver to inform the controller of the wake−up request. A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 160°C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off−state resets when Pin TxD goes high. The thermal protection circuit is particularly needed when a bus line short circuits. Split Circuit The VSPLIT Pin is operational only in normal mode. In standby mode this pin is floating. The VSPLIT is connected as shown in Figure 2 and its purpose is to provide a stabilized DC voltage of 0.5 x VCC to the bus avoiding possible steps in the common−mode signal therefore reducing EME. These unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 x VCC voltage. TxD Dominant Time−out Function A TxD dominant time−out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if Pin TxD is forced permanently low by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TxD. If the duration of the low−level on Pin TxD exceeds the internal timer value tdom(TxD), the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on Pin TxD. See Figure 10. This TxD dominant time−out time (tdom(TxD)) defines the minimum possible bit rate to 40 kbps. Wake−up When a valid wake−up (dominant state longer than tdbus) is received during the standby mode the RxD pin is driven low. Wake−up behavior in case of a permanent dominant – due to, for example, a bus short – represents the only difference between the circuit sub−versions listed in the Ordering Information table. It is depicted in Figures 3 and 4. When the standby mode is entered while a dominant is present on the bus, the “unconditioned bus wake−up” versions will signal a bus−wakeup immediately after the state transition (seen as a High−level glitch on RxD). The other version (differing purely by a metal−level modification in the digital part) will signal bus−wakeup only after the initial dominant is released. In this way it’s ensured, that a CAN bus can be put to a low−power mode even if the nodes have a level sensitivity to RxD pin and a permanent dominant is present on the bus. Fail Safe Features A current−limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 5). Pins TxD and STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse supply should the VCC supply be removed. tdbus tdbus CANH CANL STB RxD unconditioned WU Normal Standby* time *Even if bus dominant signals longer than tdbus are echoed on RxD, the transceiver stays in standby mode until STB is released. Figure 3. AMIS42665TJAA1/3 Wake−up Behavior tdbus CANH CANL STB RxD Normal Standby* time *On this derivative, bus dominant signals longer than tdbus are echoed on RxD after the bus passed through a recessive time following the trigtger of STB. The transceiver stays in standby mode until STB is released. Figure 4. AMIS42665TJAA6 Wake−up Behavior http://onsemi.com 5 AMIS−42665 ELECTRICAL CHARACTERISTICS Definitions is flowing into the pin; sourcing current means the current is flowing out of the pin. All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = −40°C to +150°C; RLT = 60 W unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit SUPPLY (PIN VCC) ICC Supply Current Dominant; VTxD = 0 V Recessive; VTxD = VCC 45 4 65 8 mA ICCS Supply Current in Standby Mode TJ,max = 100°C 10 15 mA TRANSMITTER DATA INPUT (PIN TxD) VIH High−Level Input Voltage Output Recessive 2.0 − VCC + 0.3 V VIL Low−Level Input Voltage Output Dominant −0.3 − +0.8 V IIH High−Level Input Current VTxD = VCC −5 0 +5 mA IIL Low−Level Input Current VTxD = 0 V −75 −200 −350 mA Ci Input Capacitance Not Tested − 5 10 pF TRANSMITTER MODE SELECT (PIN STB) VIH High−Level Input Voltage Standby Mode 2.0 − VCC + 0.3 V VIL Low−Level Input Voltage Normal Mode −0.3 − +0.8 V IIH High−Level Input Current VSTB = VCC −5 0 +5 mA IIL Low−Level Input Current VSTB = 0 V −1 −4 −10 mA Ci Input Capacitance Not Tested − 5 10 pF RECEIVER DATA OUTPUT (PIN RxD) Ioh High−Level Output Current Vo = 0.7 x VCC −5 −10 −15 mA Iol Low−Level Output Current Vo = 0.3 x VCC 5 10 15 mA BUS LINES (PINS CANH AND CANL) Vo(reces) (norm) Recessive Bus Voltage Normal Mode VTxD = VCC; No Load 2.0 2.5 3.0 V Vo(reces) (stby) Recessive Bus Voltage VTxD = VCC; No Load Standby Mode −100 0 100 mV Io(reces) (CANH) Recessive Output Current at Pin CANH −35 V < VCANH < +35 V; 0 V < VCC < 5.25 V −2.5 − +2.5 mA Io(reces) (CANL) Recessive Output Current at Pin CANL −35 V < VCANL < +35 V; 0 V < VCC < 5.25 V −2.5 − +2.5 mA ILI(CANH) Input Leakage Current to Pin CANH VCC = 0 V; VCANL = VCANH = 5 V −10 − +10 mA ILI(CANL) Input Leakage Current to Pin CANL VCC = 0 V; VCANL = VCANH = 5 V −10 − +10 mA Vo(dom) (CANH) Dominant Output Voltage at Pin CANH VTxD = 0 V 3.0 3.6 4.25 V Vo(dom) (CANL) Dominant Output Voltage at Pin CANL VTxD = 0 V 0. 5 1.4 1.75 V Vo(dif) (bus_dom) Differential Bus Output Voltage (VCANH − VCANL) VTxD = 0 V; Dominant; 42.5 W < RLT < 60 W 1.5 2.25 3.0 V Vo(dif) (bus_rec) Differential Bus Output Voltage (VCANH − VCANL) VTxD = VCC; Recessive; No Load −120 0 +50 mV Io(sc) (CANH) Short Circuit Output Current at Pin CANH VCANH = 0 V; VTxD = 0 V −45 −70 −120 mA http://onsemi.com 6 AMIS−42665 CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = −40°C to +150°C; RLT = 60 W unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit VCANL = 36 V; VTxD = 0 V 45 70 120 mA BUS LINES (PINS CANH AND CANL) Io(sc) (CANL) Short Circuit Output Current at Pin CANL Vi(dif) (th) Differential Receiver Threshold Voltage (see Figure 6) −5 V < VCANL < +12 V; −5 V < VCANH < +12 V; 0.5 0.7 0.9 V Vihcm(dif) (th) Differential Receiver Threshold Voltage for High Common−Mode (See Figure 6) −35 V < VCANL < +35 V; −35 V < VCANH < +35 V; 0.40 0.7 1.00 V Vi(dif) (hys) Differential Receiver Input Voltage Hysteresis (see Figure 6) −35 V < VCANL < +35 V; −35 V < VCANH < +35 V; 50 70 100 mV Ri(cm) (CANH) Common−Mode Input Resistance at Pin CANH 15 26 37 kW Ri(cm) (CANL) Common−Mode Input Resistance at Pin CANL 15 26 37 kW Ri(cm) (m) Matching Between Pin CANH and Pin CANL Common Mode Input Resistance −3 0 +3 % Ri(dif) Differential Input Resistance 25 50 75 kW Ci(CANH) Input Capacitance at Pin CANH VTxD = VCC; Not Tested 7.5 20 pF Ci(CANL) Input Capacitance at Pin CANL VTxD = VCC; Not Tested 7.5 20 pF Ci(dif) Differential Input Capacitance VTxD = VCC; Not Tested 3.75 10 pF − 0.7 x VCC VCANH = VCANL COMMON−MODE STABILIZATION (PIN VSPLIT) VSPLIT Reference Output Voltage at Pin VSPLIT Normal Mode; −500 mA < ISPLIT < 500 mA 0.3 x VCC ISPLIT(i) VSPLIT Leakage Current Standby Mode −5 +5 mA ISPLIT(lim) VSPLIT Limitation Current Normal Mode −3 +3 mA CANH, CANL, Vref in Tri−State Below POR Level 2.2 3.5 4.7 V 150 160 180 °C POWER−ON−RESET (POR) PORL POR Level THERMAL SHUTDOWN TJ(sd) Shutdown Junction Temperature TIMING CHARACTERISTICS (see Figures 7 and 8) td(TxD−BUSon) Delay TXD to Bus Active Cl = 100 pF Between CANH to CANL 40 85 105 ns td(TxD−BUSoff) Delay TXD to Bus Inactive Cl = 100 pF Between CANH to CANL 30 60 105 ns td(BUSon−RXD) Delay Bus Active to RXD Crxd = 15 pF 25 55 105 ns td(BUSoff−RXD) Delay Bus Inactive to RXD Crxd = 15 pF 40 100 105 ns tpd(rec−dom) Propagation Delay TXD to RXD from Recessive−to−Dominant Cl = 100 pF Between CANH to CANL 90 230 ns td(dom−rec) Propagation Delay TXD to RXD from Dominant−to−Recessive Cl = 100 pF Between CANH to CANL 90 245 ns td(stb−nm) Delay Standby Mode to Normal Mode 10 ms tdbus Dominant Time for Wake−up via Bus tdom(TxD) TxD Dominant Time for Time Out Baudrate Communication Speed Achievable 5 VTxD = 0 V 0.75 2.5 5 ms 300 650 1000 ms 1M bps 40k http://onsemi.com 7 7.5 AMIS−42665 MEASUREMENT SETUPS AND DEFINITIONS +5 V 100 nF VCC 3 CANH 7 TxD 1 nF 1 VSPLIT AMIS− Transient Generator 5 42665 RxD 1 nF 4 6 PC20040829.5 CANL 2 8 15 pF GND STB Figure 5. Test Circuit for Automotive Transients VRxD High Low Hysteresis PC20040829.7 0.5 Vi(dif)(hys) 0.9 Figure 6. Hysteresis of the Receiver +5 V 100 nF VCC 3 7 TxD CANH 1 VSPLIT AMIS− 42665 RLT 60 W RxD 4 6 CANL 8 15 pF 2 GND STB PC20040829.4 Figure 7. : Test Circuit for Timing Characteristics http://onsemi.com 8 CLT 5 100 pF AMIS−42665 HIGH TxD LOW CANH CANL Dominant 0.9 V Vi(dif) = VCANH − VCANL 0.5 V RxD Recessive 0.7 x VCC 0.3 x VCC Td(TxD−BUSon) Td(TxD−BUSoff) Td(BUSoff−RxD) Tpd(rec−dom) Tpd(dom−rec) PC20040829.6 Figure 8. Timing Diagram for AC Characteristics td(stb−nm) STB Mode Normal Standby Transition delay time Figure 9. Transition from Standby to Normal td(stb−nm) Time−Out(*) TxD CANH CANL *The time−out is reset on TxD rising edge. time Figure 10. AMIS−42665 TxD Time−Out Bus Blockage Prevention in Case of Controller Failure http://onsemi.com 9 AMIS−42665 +5 V 100 nF VCC 3 7 TxD 6.2 kW CANH 10 nF 1 Active Probe AMIS− 42665 Generator RxD 6 6.2 kW CANL Spectrum Anayzer 30 W 4 30 W 5 VSPLIT 2 8 15 pF STB GND 47 nF Figure 11. Basic Test Setup for Electromagnetic Measurement PC20040829.9 Figure 12. EME Measurements DEVICE ORDERING INFORMATION Version Temperature Range Package Type Shipping† Unconditioned Bus Wake−up −40°C − 125°C SOIC−8* (Pb−Free) 96 Tube / Tray AMIS42665TJAA1RG −40°C − 125°C SOIC−8* (Pb−Free) 3000 / Tape & Reel AMIS42665TJAA3L −40°C − 125°C SOIC−8** (Pb−Free) 96 Tube / Tray AMIS42665TJAA3RL −40°C − 125°C SOIC−8** (Pb−Free) 3000 / Tape & Reel −40°C − 125°C SOIC−8* (Pb−Free) 96 Tube / Tray −40°C − 125°C SOIC−8* (Pb−Free) 3000 / Tape & Reel Part Number AMIS42665TJAA1G AMIS42665TJAA6G Bus Wake−up Inactive in Case of Bus Fault AMIS42665TJAA6RG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Matte Sn, JEDEC MS−012 ** NiPdAu, JEDEC MS−012 http://onsemi.com 10 AMIS−42665 PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AMIS−42665/D