SEMICONDUCTOR TECHNICAL DATA The MC10141 is a four–bit universal shift register which performs shift left, or shift right, serial/parallel in, and serial/parallel out operations with no external gating. Inputs S1 and S2 control the four possible operations of the register without external gating of the clock. The flip–flops shift information on the positive edge of the clock. The four operations are stop shift, shift left, shift right, and parallel entry of data. The other six inputs are all data type inputs; four for parallel entry data, and one for shifting in from the left (DL) and one for shifting in from the right (DR). L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 PD = 425 mW typ/pkg (No Load) fShift = 200 MHz typ tr, tf = 2.0 ns typ (20%–80%) FN SUFFIX PLCC CASE 775–02 LOGIC DIAGRAM D3 S1 1 of 4 Decoder S2 DR D2 Parallel Enter D1 D0 DIP PIN ASSIGNMENT Shift Right Shift Left DL Hold VCC1 1 16 VCC2 Q2 2 15 Q1 Q3 3 14 Q0 C 4 13 DL D Q D Q D Q D Q DR 5 12 D0 C C C C D3 6 11 D1 S2 7 10 S1 VEE 8 9 D2 C Q3 Q2 Q1 Q0 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). TRUTH TABLE SELECT OUTPUTS S1 S2 OPERATING MODE L L Parallel Entry Q0n+1 D0 Q1n+1 D1 Q2n+1 D2 L H Shift Right* H L Shift Left* Q1n DL Q2n Q0n Q3n Q1n H H Stop Shift Q0n Q1n Q2n Q3n+1 D3 DR Q2n Q3n *Outputs as exist after pulse appears at “C” input with input conditions as shown. (Pulse = Positive transition of clock input). 3/93 Motorola, Inc. 1996 3–46 REV 5 MC10141 SHIFT FREQUENCY TEST CIRCUIT VCC1 = VCC2 +2.0 VDC VIN COAX INPUT PULSE GENERATOR 0.1 µF 25 uF 1 DL C Q0 TEST PROCEDURES: 1. SET D1, D2, D3 = +0.31 VDC (LOGIC L) D0 = +1.11 VDC (LOGIC H) —V IH TO SET Q0 HIGH. 2. APPY CLOCK PULSE VIL 3. MAINTAIN CLOCK LOW. SET S1 = +0.31 VDC (LOGIC L) S2 = +1.11 VDC (LOGIC H) Q1 D2 D3 Q2 S1 S2 DR Coax All input and output cables to the scope are equal lengths of 50–ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin. 16 D0 D1 50–ohm termination to ground located in each scope channel input. VOUT Q3 4. TEST SHIFT FREQUENCY 8 0.1 µF VEE = –3.2VDC MECL Data DL122 — Rev 6 3–47 MOTOROLA MC10141 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Pi Under Test IE 8 112 IinH 5 6 7 4 350 350 390 425 –30°C Min +25°C Max Min +85°C Max Unit 102 112 mAdc 220 220 245 265 220 220 245 265 µAdc Typ Max 82 Min 12 0.5 Logic 1 VOH 3 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc Output Voltage Logic 0 VOL 3 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc Threshold Voltage Logic 1 VOHA (Note 1.) 3 3 3 3 –1.080 –1.080 –1.080 –1.080 Threshold Voltage Logic 0 VOLA (Note 1.) 3 3 3 3 Switching Times 0.5 µAdc IinL Output Voltage 0.3 –0.980 –0.980 –0.980 –0.980 –0.910 –0.910 –0.910 –0.910 –1.655 –1.655 –1.655 –1.655 –1.630 –1.630 –1.630 –1.630 Vdc –1.595 –1.595 –1.595 –1.595 (50Ω Load) Propagation Delay Setup TIme (tsetup) Hold Time (thold) ns t4+3+ t12+4+ t10+4+ t4+12+ 3 14 14 14 1.7 2.5 5.5 1.5 3.9 1.8 2.5 5.0 1.5 2.9 3.8 2.0 2.5 5.5 1.5 4.2 Rise Time (20 to 80%) t3+ 3 1.0 3.4 1.1 2.0 3.3 1.1 3.6 Fall Time (20 to 80%) t3– 3 1.0 3.4 1.1 2.0 3.3 1.1 3.6 150 200 Shift Frequency Vdc fshift 1. These tests to be performed in sequence as shown. 150 P1 VIH VIL P2 150 VIHA VIL P3 MHz VILA VIL 2. See shift frequency test circuit for test procedures. 3. Reset to zero before performing test. 4. Reset to one before performing test. MOTOROLA 3–48 MECL Data DL122 — Rev 6 MC10141 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Characteristic Symbol Pin Under Test Power Supply Drain Current IE 8 IinH 5 6 7 4 5 6 7 4 IinL 12 4,5,6,7,9, 10,11,13 6 Input Current Output Voltage Logic 1 VOH 3 Output Voltage Logic 0 VOL 3 Threshold Voltage Logic 1 VOHA (Note 1.) 3 3 3 3 Threshold Voltage Logic 0 VOLA (Note 1.) TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax 12 6 6 6 3 3 3 3 Note 3. Note 3. 7 6 7 Note 4. Note 4. 6 Switching Times (50Ω Load) Propagation Delay Setup TIme (tsetup) Hold Time (thold) P1 VEE P2 (VCC) Gnd P3 8 1, 16 8 8 8 8 1, 16 1, 16 1, 16 1, 16 8 1, 16 8 4 1, 16 8 4 1, 16 8 8 8 8 4 4 4 1, 16 1, 16 1, 16 1, 16 8 8 8 8 4 4 4 1, 16 1, 16 1, 16 1, 16 4 4 –3.2 V +2.0 V t4+3+ t12+4+ t10+4+ t4+12+ 3 14 14 14 8 8 8 8 1, 16 1, 16 1, 16 1, 16 Rise Time (20 to 80%) t3+ 3 8 1, 16 Fall Time (20 to 80%) t3– 3 8 1, 16 8 1, 16 Shift Frequency fshift 1. These tests to be performed in sequence as shown. Note 2. P1 VIH VIL P2 VIHA VIL P3 VILA VIL 2. See shift frequency test circuit for test procedures. 3. Reset to zero before performing test. 4. Reset to one before performing test. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MECL Data DL122 — Rev 6 3–49 MOTOROLA MC10141 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 V 0.010 (0.250) G1 X S T L–M N S S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S Z C H –T– SEATING PLANE F VIEW S G1 0.010 (0.250) S T L–M S 0.007 (0.180) M T L–M S N S VIEW S S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA N K 0.004 (0.100) J S K1 E G 0.007 (0.180) M T L–M 3–50 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– MECL Data DL122 — Rev 6 MC10141 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MECL Data DL122 — Rev 6 3–51 *MC10141/D* MC10141/D MOTOROLA