DATASHEET ISL6597 FN9165 Rev 1.00 May 4, 2007 Dual Synchronous Rectified MOSFET Drivers The ISL6597 integrates two ISL6596 drivers and is optimized to drive two independent power channels in a synchronous-rectified buck converter topology. These drivers, combined with an Intersil multiphase PWM controller, form a complete high efficiency voltage regulator solution. Features The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Each driver is capable of driving a 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. • 0.4 On-Resistance and 4A Sink Current Capability The ISL6597 features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6597 also features an input that recognizes a highimpedance state, working together with Intersil multi-phase 3.3V or 5V PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from negative output voltage damage. Ordering Information PART NUMBER (Note) ISL6597CRZ • Adaptive Shoot-Through Protection • Programmable Deadtime for Efficiency Optimization • Supports High Switching Frequency - Fast Output Rise and Fall - Ultra Low Tri-State Hold-Off Time (20ns) • Low VF Internal Bootstrap Diode • Low Bias Supply Current • Support 3.3V and 5V PWM Input • Enable Input and Power-On Reset • QFN Package - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No Leads-Product Outline - Near Chip-Scale Package Footprint; Improves PCB Utilization and Thinner in Profile • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Core Voltage Supplies for Intel® and AMD® Microprocessors • High Frequency Low Profile High Efficiency DC/DC Converters • High Current Low Voltage DC/DC Converters PART MARKING TEMP. RANGE (°C) 65 97CRZ 0 to +70 16 Ld 4x4 QFN L16.4x4 PACKAGE (Pb-Free) PKG. DWG. # Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN9165 Rev 1.00 May 4, 2007 • 5V Quad N-Channel MOSFET Drives for Two Synchronous Rectified Bridges • Synchronous Rectification for Isolated Power Supplies Related Literature • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages” • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Page 1 of 10 ISL6597 Pinout PWM2 PWM1 VCC PHASE1 ISL6597 (16 LD QFN) TOP VIEW 16 15 14 13 GND 1 12 UGATE1 17 LGATE1 2 11 BOOT1 PGND 10 BOOT2 PVCC 3 5 6 7 8 LGATE2 VCTRL PHASE2 9 PGND EN 4 UGATE2 Block Diagram ISL6597 VCC PVCC VCTRL BOOT1 UGATE1 SHOOTTHROUGH PROTECTION 3.5K PHASE1 CHANNEL 1 PVCC1 PWM1 LGATE1 3.5K PGND EN VCTRL CONTROL LOGIC PGND PVCC BOOT2 UGATE2 3.5K PWM2 SHOOTTHROUGH PROTECTION 3.5K GND PHASE2 CHANNEL 2 PVCC LGATE2 PGND PAD FN9165 Rev 1.00 May 4, 2007 Page 2 of 10 ISL6597 Typical Application - Multiphase Converter Using ISL6597 Gate Drivers BOOT1 +3.3V +12V UGATE1 VCTRL PHASE1 +5V LGATE1 +3.3V PVCC VCC DUAL DRIVER ISL6597 BOOT2 COMP FB VCC VSEN +12V EN UGATE2 ISEN1 PGOOD PWM1 EN PWM2 PWM1 PWM2 LGATE2 MAIN ISEN2 CONTROL ISL65xx VID PHASE2 GND PGND +VCORE ISEN3 FS/DIS PWM3 PWM4 GND +3.3V BOOT1 +12V ISEN4 UGATE1 VCTRL PHASE1 +5V LGATE1 PVCC VCC DUAL DRIVER ISL6597 BOOT2 +12V EN UGATE2 PWM1 PHASE2 PWM2 LGATE2 GND FN9165 Rev 1.00 May 4, 2007 PGND Page 3 of 10 ISL6597 Absolute Maximum Ratings Thermal Information Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns) BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC) GND -8V (<20ns Pulse Width, 10J) to 30V (<100ns) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Thermal Resistance (Notes 1 and 2) JA(°C/W) JC(°C/W) QFN Package . . . . . . . . . . . . . . . . . . 46 8.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +70°C Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Constantly operated at +150°C may shorten the life of the part. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 2. JC, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details. Electrical Specifications These specifications apply for TA = 0°C to +70°C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM pin floating, VVCC = VPVCC = 5V - 350 - A FPWM = 300kHz, VVCC = VPVCC = 5V - 1.7 - mA POR Rising - 3.4 4.2 V POR Falling 2.6 3.0 - V - 400 - mV 0.3 0.6 0.7 V 2.5 2.8 - V - 100 - mV EN LOW Threshold 1.00 1.34 - V EN HIGH Threshold 1.40 1.60 - V EN Hysteresis 100 260 - mV VCC SUPPLY CURRENT Bias Supply Current IVCC+PVCC Hysteresis BOOTSTRAP DIODE Forward Voltage VF Forward bias current = 2mA VCTRL INPUT Turn-On Threshold Hysteresis ENABLE INPUT PWM INPUT Sinking Impedance RPWM_SNK - 3.5 - k Source Impedance RPWM_SRC - 3.5 - k - 1.15 1.4 V Tri-State Lower Threshold VVCC = 3.3V (120mV Hysteresis) - 1.55 1.75 V Tri-State Upper Threshold VVCC = 3.3V (110mV Hysteresis) 1.65 1.85 - V VVCC = 5V (300mV Hysteresis) 3.00 3.18 - V - 80 - ns VVCC = 5V (300mV Hysteresis) Tri-State Shutdown Holdoff Time tTSSHD SWITCHING TIME (Note 3, See Figure 1) UGATE Rise Time tRU VVCC = 5V, 3nF Load - 8.0 - ns LGATE Rise Time tRL VVCC = 5V, 3nF Load - 8.0 - ns UGATE Fall Time tFU VVCC = 5V, 3nF Load - 8.0 - ns FN9165 Rev 1.00 May 4, 2007 Page 4 of 10 ISL6597 Electrical Specifications These specifications apply for TA = 0°C to +70°C, unless otherwise noted (Continued) PARAMETER LGATE Fall Time SYMBOL TEST CONDITIONS MIN TYP MAX UNITS tFL VVCC = 5V, 3nF Load - 4.0 - ns tPDLU VVCC = 5V, Unloaded, - 18 - ns LGATE Turn-Off Propagation Delay tPDLL VVCC = 5V, Unloaded, - 25 - ns UGATE Turn-On Propagation Delay tPDHU VVCC = 5V, Unloaded, - 18 - ns LGATE Turn-On Propagation Delay tPDHL VVCC = 5V, Unloaded, - 23 - ns tPTS VVCC = 5V, Unloaded - 30 - ns Upper Drive Source Resistance RUG_SRC 250mA Source Current - 1.0 2.5 Upper Drive Sink Resistance RUG_SNK 250mA Sink Current - 1.0 2.5 Lower Drive Source Resistance RLG_SRC 250mA Source Current - 1.0 2.5 Lower Drive Sink Resistance RLG_SNK 250mA Sink Current - 0.4 1.0 UGATE Turn-Off Propagation Delay Tri-state to UG/LG Rising Propagation Delay OUTPUT (Note 3) NOTE: 3. Guaranteed by Characterization. Not 100% tested in production. Functional Pin Description PACKAGE PIN # PIN SYMBOL 1 GND 2 LGATE1 3 PVCC 4 EN FUNCTION Bias and reference ground. All signals are referenced to this node. Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET. This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from this pin to PGND. Enable input pin. Connect this pin high to enable and low to disable the driver. 5 PGND 6 LGATE2 It is the power ground return of both low gate drivers. Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET. 7 VCTRL This pin sets the PWM logic threshold. Connect this pin to 3.3V source for 3.3V PWM input and pull it to 5V source for 5V PWM input. 8 PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin provides a return path for the upper gate drive. 9 UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET. 10 BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap Considerations” on page 7 for guidance in choosing the capacitor value. 11 BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap Considerations” on page 7 for guidance in choosing the capacitor value. 12 UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET. 13 PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin provides a return path for the upper gate drive. 14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic capacitor from this pin to GND. 15 PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller. 16 PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller. 17 PAD FN9165 Rev 1.00 May 4, 2007 Connect this pad to the power ground plane (PGND) via thermally enhanced connection. Page 5 of 10 ISL6597 Timing Diagram 2.5V PWM tPDHU tPDLU tTSSHD tRU tRU tFU tPTS 1V UGATE LGATE tPTS 1V tRL tTSSHD tPDLL tPDHL tFL FIGURE 1. TIMING DIAGRAM Operation and Adaptive Shoot-Through Protection Designed for high speed switching, the ISL6597 MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising transition on PWM initiates the turn-off of the lower MOSFET (see Figure 1). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the Electrical Specifications. Adaptive shootthrough circuitry monitors the LGATE voltage and turns on the upper gate following a short delay time [tPDHU] after the LGATE voltage drops below ~1V. The upper gate drive then begins to rise [tRU] and the upper MOSFET turns on. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. The adaptive shoot-through circuitry monitors the UGATE-PHASE voltage and turns on the lower MOSFET a short delay time, tPDHL, after the upper MOSFET’s gate voltage drops below 1V. The lower gate then rises [tRL], turning on the lower MOSFET. These methods prevent both the lower and upper MOSFETs from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge characteristics of the MOSFETs being used. This driver is optimized for voltage regulators with large step down ratio. The lower MOSFET is usually sized larger compared to the upper MOSFET because the lower MOSFET conducts for a longer time during a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.4 on-resistance and 4A sink current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate FN9165 Rev 1.00 May 4, 2007 (CGD) capacitor of the lower MOSFET and help prevent shoot through caused by the self turn-on of the lower MOSFET due to high dV/dt of the switching node. Tri-State PWM Input A unique feature of the ISL6597 is the programmable PWM logic threshold set by the control pin (VCTRL) voltage. The VCTRL pin should connect to the controller’s VCC so that the PWM logic thresholds follow with the VCC voltage level. For applications using single rail 5V to power up both controller and driver, this pin can be tied to the driver VCC, simplifying the trace routing. The ISL6597 also features the adaptable tri-state PWM input. Once the PWM signal enters the shutdown window, either MOSFET previously conducting is turned off. If the PWM signal remains within the shutdown window for longer than the gate turn-off propagation delay of the previously conducting MOSFET, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. The PWM rising and falling thresholds outlined in the Electrical Specifications determine when the lower and upper gates are enabled. During normal operation in a typical application, the PWM rise and fall times through the shutdown window should not exceed either output’s turn-off propagation delay plus the MOSFET gate discharge time to ~1V. Abnormally long PWM signal transition times through the shutdown window will simply introduce additional dead time between turn off and turn on of the synchronous bridge’s MOSFETs. For optimal performance, no more than 50pF parasitic capacitive load should be present on the PWM line of ISL6597 (assuming an Intersil PWM controller is used). Page 6 of 10 ISL6597 Bootstrap Considerations This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The following equation helps select a proper bootstrap capacitor size: Q GATE C BOOT_CAP -------------------------------------V BOOT_CAP (EQ. 1) P Qg_TOT = 2 P Qg_Q1 + P Qg_Q2 + I Q VCC Q G1 PVCC Q GATE = ------------------------------------ N Q1 V GS1 where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. As an example, suppose two HAT2168 FETs are chosen as the upper MOSFETs. The gate charge (QG) from the data sheet is 12nC at 5V (VGS) gate-source voltage. Then the QGATE is calculated to be 26.4nC at 5.5V PVCC level. We will assume a 100mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.264F is required. The next larger standard value capacitance is 0.33µF. A good quality ceramic capacitor is recommended. 2.0 1.8 1.6 CBOOT_CAP (µF) 1.2 1.0 0.8 QGATE = 100nC 0.4 0.2 50nC 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VBOOT (V) FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE Power Dissipation Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the external gate resistance, and the selected MOSFET’s internal gate resistance and total gate charge. Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the 16 lead 4x4 FN9165 Rev 1.00 May 4, 2007 (EQ. 2) Q G1 PVCC 2 P Qg_Q1 = --------------------------------------- F SW N Q1 V GS1 Q G2 PVCC 2 P Qg_Q2 = --------------------------------------- F SW N Q2 V GS2 Q G1 N Q1 Q G2 N Q2 I DR = 2 ----------------------------- + ------------------------------ F SW + I Q V GS2 V GS1 (EQ. 3) where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ is the driver’s total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively. The factor 2 is the number of active channels. The IQ VCC product is the quiescent power of the driver without capacitive load and is typically negligible. The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2, should be a short to avoid interfering with the operation shoot-through protection circuitry) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. The power dissipation on the driver can be roughly estimated as: 1.4 0.6 QFN packages, with an exposed heat escape pad, is around 2W. See Layout Considerations paragraph for thermal transfer improvement suggestions. When designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses due to the gate charge of MOSFETs and the driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 2 and 3, respectively, P DR = 2 P DR_UP + P DR_LOW + I Q VCC (EQ. 4) R HI1 R LO1 P Qg_Q1 P DR_UP = -------------------------------------+ --------------------------------------- --------------------2 R + R R + R HI1 EXT1 LO1 EXT1 R HI2 R LO2 P Qg_Q2 P DR_LOW = -------------------------------------+ --------------------------------------- --------------------2 R HI2 + R EXT2 R LO2 + R EXT2 R GI1 R EXT2 = R G1 + ------------N Q1 R GI2 R EXT2 = R G2 + ------------N Q2 Page 7 of 10 ISL6597 PVCC the device rating. Low-profile MOSFETs, such as Direct FETs and multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK), have low parasitic lead inductances and are preferred. BOOT D CGD RHI1 Layout Considerations G RLO1 UGATE RG1 CDS RGI1 CGS Q1 S PHASE FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PVCC D CGD RHI2 LGATE RLO2 G CDS RGI2 RG2 CGS Q2 S GND FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH MOSFET Selection The parasitic inductances of the PCB and of the power devices’ packaging (both upper and lower MOSFETs) can cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the PHASE node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper MOSFET driver. Careful layout, proper selection of MOSFETs and packaging can go a long way toward minimizing such unwanted stress. BOOT D RHI1 RLO1 Q1 UGATE S RPH = 1 to 2 FIGURE 5. PHASE RESISTOR TO MINIMIZE SERIOUS NEGATIVE PHASE SPIKE The D2-PAK, or D-PAK packaged MOSFETs, have large parasitic lead inductances and are not recommended unless a phase resistor (RPH), as shown in Figure 5, is implemented to prevent the bootstrap capacitor from overcharging, exceeding FN9165 Rev 1.00 May 4, 2007 • Minimize trace inductance, especially on low-impedance lines. All power traces (UGATE, PHASE, LGATE, PGND, PVCC, VCC, GND) should be short and wide, at least 25 mils. Try to place power traces on a single layer, otherwise, two vias on interconnection are preferred where possible. For no connection (NC) pins on the QFN part, connect it to the adjacent net (LGATE2/PHASE2) can reduce trace inductance. • Shorten all gate drive loops (UGATE-PHASE and LGATEPGND) and route them closely spaced. • Minimize the current loop of the output and input power trains. Short the source connection of the lower MOSFET to ground as close to the transistor pin as feasible. Input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible. • Avoid routing relatively high impedance nodes (such as PWM and ENABLE lines) close to high dV/dt UGATE and PHASE nodes. In addition, connecting the thermal pad of the QFN package to the power ground through multiple vias is recommended. This is to improve heat dissipation and allow the part to achieve its full thermal potential. Upper MOSFET Self Turn-On Effects At Startup G PHASE • Keep decoupling loops (VCC-GND, PVCC-PGND and BOOT-PHASE) short and wide, at least 25 mils. Avoid using vias on decoupling components other than their ground terminals, which should be on a copper plane with at least two vias. • Minimize the inductance of the PHASE node. Ideally, the source of the upper and the drain of the lower MOSFET should be as close as thermally allowable. Application Information PVCC A good layout helps reduce the ringing on the switching node (PHASE) and significantly lower the stress applied to the output drives. The following advice is meant to lead to an optimized layout and performance: Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, due to the selfcoupling via the internal CGD of the MOSFET, the UGATE could momentarily rise up to a level greater than the threshold voltage of the MOSFET. This could potentially turn on the upper switch and result in damaging inrush energy. Therefore, if such a situation (when input bus powered up before the bias of the controller and driver is ready) could conceivably be encountered, it is a common practice to place a resistor (RUGPH) across the gate and source of the upper MOSFET to suppress the Miller coupling effect. The value of the resistor Page 8 of 10 ISL6597 VCC (EQ. 5) C iss = C GD + C GS C rss = C GD R = R UGPH + R GI VIN BOOT D CBOOT CGD DU UGATE DL G RUGPH The coupling effect can be roughly estimated with the following equations, which assume a fixed linear input ramp and neglect the clamping effect of the body diode of the upper drive and the bootstrap capacitor. Other parasitic components such as lead inductances and PCB capacitances are also not taken into account. These equations are provided for guidance purpose only. Therefore, the actual coupling effect should be examined using a very high impedance (10M or greater) probe to ensure a safe design margin. –V DS ---------------------------------- dV ------- R C dV iss V GS_MILLER = ------- R C rss 1 – e dt dt ISL6597 depends mainly on the input voltage’s rate of rise, the CGD/CGS ratio, as well as the gate-source threshold of the upper MOSFET. A higher dV/dt, a lower CDS/CGS ratio, and a lower gate-source threshold upper FET will require a smaller resistor to diminish the effect of the internal capacitive coupling. For most applications, the integrated 20k typically sufficient, not affecting normal performance and efficiency. CDS RGI CGS QUPPER S PHASE FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE UPPER MOSFET MILLER COUPLING © Copyright Intersil Americas LLC 2006-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9165 Rev 1.00 May 4, 2007 Page 9 of 10 ISL6597 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 A3 b 0.23 D 0.28 9 0.35 5, 8 4.00 BSC D1 D2 9 0.20 REF - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.65 BSC - k 0.25 - - - L 0.50 0.60 0.75 8 L1 - - 0.15 10 N 16 2 Nd 4 3 Ne 4 3 P - - 0.60 9 - - 12 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. FN9165 Rev 1.00 May 4, 2007 Page 10 of 10