NDD03N50Z N-Channel Power MOSFET 500 V, 3.3 W Features • • • • Low ON Resistance Low Gate Charge 100% Avalanche Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com VDSS RDS(on) (MAX) @ 1.15 A 500 V 3.3 W ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit VDSS 500 V Continuous Drain Current RqJC ID 2.6 A Continuous Drain Current RqJC, TA = 100°C ID 1.7 A Pulsed Drain Current, VGS @ 10 V IDM 10 A Power Dissipation RqJC PD 58 W Gate−to−Source Voltage VGS ±30 V Single Pulse Avalanche Energy, ID = 2.6 A EAS 120 mJ ESD (HBM) (JESD22−A114) Vesd 2000 V Peak Diode Recovery dv/dt 4.5 (Note 1) V/ns Continuous Source Current (Body Diode) IS 2.6 A Maximum Temperature for Soldering Leads TL 260 °C Rating Drain−to−Source Voltage Operating Junction and Storage Temperature Range TJ, Tstg −55 to 150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. ID v 2.6 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, TJ ≤ 150°C. © Semiconductor Components Industries, LLC, 2010 July, 2010 − Rev. 0 N−Channel D (2) G (1) S (3) 4 4 1 2 3 IPAK CASE 369D STYLE 2 1 2 3 DPAK CASE 369AA STYLE 2 MARKING AND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. 1 Publication Order Number: NDD03N50Z/D NDD03N50Z THERMAL RESISTANCE Parameter Junction−to−Case (Drain) Junction−to−Ambient Steady State Symbol Value Unit NDD03N50Z RqJC 2.2 °C/W (Note 3) NDD03N50Z (Note 2) NDD03N50Z−1 RqJA 41 80 2. Insertion mounted 3. Surface mounted on FR4 board using 1″ sq. pad size, (Cu area = 1.127 in sq [2 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Conditions Min BVDSS VGS = 0 V, ID = 1 mA 500 DBVDSS/ DTJ Reference to 25°C, ID = 1 mA Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Drain−to−Source Leakage Current Gate−to−Source Forward Leakage IDSS VDS = 500 V, VGS = 0 V IGSS VGS = ±20 V Static Drain−to−Source On−Resistance RDS(on) VGS = 10 V, ID = 1.15 A Gate Threshold Voltage VGS(th) VDS = VGS, ID = 50 mA gFS VDS = 15 V, ID = 1.15 A V 0.6 V/°C 25°C 1 150°C 50 mA ±10 mA 3.3 W 4.5 V ON CHARACTERISTICS (Note 4) Forward Transconductance 2.8 3.0 1.8 S 274 pF DYNAMIC CHARACTERISTICS Input Capacitance Ciss VDS = 25 V, VGS = 0 V, f = 1.0 MHz Output Capacitance Coss Reverse Transfer Capacitance Crss 8 Total Gate Charge Qg 10 Gate−to−Source Charge Qgs Gate−to−Drain (“Miller”) Charge Qgd Plateau Voltage VGP 6.4 V Gate Resistance Rg 4.5 W 9 ns VDD = 250 V, ID = 2.6 A, VGS = 10 V 38 nC 2.3 5.5 RESISTIVE SWITCHING CHARACTERISTICS Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VDD = 250 V, ID = 2.6 A, VGS = 10 V, RG = 5 W tf 7 15 7 SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted) Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr IS = 2.6 A, VGS = 0 V VGS = 0 V, VDD = 30 V IS = 2.6 A, di/dt = 100 A/ms 4. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. http://onsemi.com 2 1.6 V 240 ns 0.7 mC NDD03N50Z 4.0 4.0 VGS = 10 V 3.0 6.5 V 2.5 2.0 6.0 V 1.5 1.0 5.5 V 0.5 0.0 3.0 2.5 2.0 1.5 TJ = 25°C 1.0 TJ = 150°C 0.5 5.0 V 0 VDS = 25 V 3.5 7.0 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 3.5 5 10 15 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.0 25 3 ID = 1.15 A TJ = 25°C 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 2.75 2.50 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 4 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (V) 9.5 10.0 3.5 3.4 3.3 VGS = 10 V TJ = 25°C 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 0.0 0.5 1.0 1.5 2.0 2.5 ID, DRAIN CURRENT (A) Figure 4. On−Resistance versus Drain Current and Gate Voltage BVDSS, NORMALIZED BREAKDOWN VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 3. On−Region versus Gate−to−Source Voltage 2.50 2.25 2.00 ID = 1.15 A VGS = 10 V 1.75 1.50 1.25 1.00 0.75 0.50 0.25 −50 −25 0 25 50 75 100 10 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 5.00 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics TJ = −55°C 125 150 TJ, JUNCTION TEMPERATURE (°C) 1.15 ID = 1 mA 1.10 1.05 1.00 0.95 0.90 −50 Figure 5. On−Resistance Variation with Temperature −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 6. BVDSS Variation with Temperature http://onsemi.com 3 3.0 150 NDD03N50Z 600 550 C, CAPACITANCE (pF) TJ = 150°C 1 TJ = 125°C 0 50 Coss 400 350 Crss 300 250 200 150 100 50 0 0.01 100 150 200 250 300 350 400 450 500 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Drain−to−Source Leakage Current versus Voltage Figure 8. Capacitance Variation VGS, GATE−TO−SOURCE VOLTAGE (V) 0.1 TJ = 25°C VGS = 0 V f = 1 MHz Ciss 500 450 300 12 QT 10 8 VDS 250 VGS QGD 200 QGS 150 6 100 4 VDS = 250 V ID = 2.6 A TJ = 25°C 2 0 0 1 2 3 4 5 6 7 8 9 10 50 0 11 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) IDSS, LEAKAGE (mA) 10 Qg, TOTAL GATE CHARGE (nC) Figure 9. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge 1000 10.0 IS, SOURCE CURRENT (A) VDD = 250 V ID = 2.6 A VGS = 10 V t, TIME (ns) 100 td(off) tr tf td(on) 10 1.0 TJ = 150°C 125°C 25°C −55°C 1 1 10 RG, GATE RESISTANCE (W) 100 0.1 0.3 Figure 10. Resistive Switching Time Variation versus Gate Resistance 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 11. Diode Forward Voltage versus Current http://onsemi.com 4 1.2 NDD03N50Z ID, DRAIN CURRENT (A) 100 VGS v 30 V SINGLE PULSE TC = 25°C 10 100 ms 10 ms 1 ms 10 ms dc 1 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1 10 100 1000 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 12. Maximum Rated Forward Biased Safe Operating Area NDD03N50Z 10 R(t) (C/W) 1 50% (DUTY CYCLE) 20% 10% 0.1 5% 2% 1% RqJC = 2.2°C/W Steady State SINGLE PULSE 0.01 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03 PULSE TIME (s) Figure 13. Thermal Impedance (Junction−to−Case) for NDD03N50Z R(t) (C/W) 100 10 50% (DUTY CYCLE) 20% 10% 5.0% 1 2.0% 1.0% 0.1 0.01 1E−06 RqJA = 41°C/W Steady State SINGLE PULSE 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 PULSE TIME (s) Figure 14. Thermal Impedance (Junction−to−Ambient) for NDD03N50Z http://onsemi.com 5 1E+02 1E+03 NDD03N50Z ORDERING INFORMATION Package Shipping† NDD03N50Z−1G IPAK (Pb−Free) 75 Units / Rail NDD03N50ZT4G DPAK (Pb−Free) 2500 / Tape & Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS 4 Drain YWW 3N 50ZG YWW 3N 50ZG 4 Drain 2 1 Drain 3 Gate Source 1 2 3 Gate Drain Source A Y WW G = Location Code = Year = Work Week = Pb−Free Package http://onsemi.com 6 NDD03N50Z PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NDD03N50Z PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE B C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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