BSI BS62LV2006DCG70 Very low power cmos sram 256k x 8 bit Datasheet

Very Low Power CMOS SRAM
256K X 8 bit
BS62LV2006
Pb-Free and Green package materials are compliant to RoHS
„ FEATURES
„ DESCRIPTION
y Wide VCC operation voltage : 2.4V ~ 5.5V
y Very low power consumption :
VCC = 3.0V Operation current : 23mA (Max.) at 55ns
2mA (Max.) at 1MHz
O
Standby current : 0.7/2uA (Max.) at 70/85 C
VCC = 5.0V Operation current : 55mA (Max.) at 55ns
10mA (Max.) at 1MHz
O
Standby current : 6/20uA (Max.) at 70/85 C
y High speed access time :
-55
55ns (Max.) at VCC : 3.0~5.5V
-70
70ns (Max.) at VCC : 2.7~5.5V
y Automatic power down when chip is deselected
y Easy expansion with CE2, CE1 and OE options
y Three state outputs and TTL compatible
y Fully static operation
y Data retention supply voltage as low as 1.5V
The BS62LV2006 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
O
current of 2/20uA at Vcc=3V/5V at 85 C and maximum access time
of 55/70ns.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV2006 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV2006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP
package.
„ POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
Operating
(ICCSB1, Max)
VCC=5.0V
VCC=3.0V
PKG TYPE
(ICC, Max)
1MHz
VCC=5V
10MHz
fMax.
VCC=3V
10MHz
1MHz
fMax.
BS62LV2006DC
DICE
BS62LV2006SC
Commercial
O
O
+0 C to +70 C
BS62LV2006STC
6.0uA
0.7uA
9mA
29mA
53mA
1.5mA
9mA
22mA
BS62LV2006TC
Industrial
O
O
-40 C to +85 C
BS62LV2006STI
BS62LV2006TI
SOP-32
20uA
2.0uA
10mA
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV2006TC
BS62LV2006TI
BS62LV2006STC
BS62LV2006STI
30mA
55mA
2mA
10mA
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A7
A12
A14
A16
A17
A15
A11
A8
A9
A13
Address
10
Input
1024
Row
Decoder
2048
DQ0
8
Data
Input
Buffer
8
BS62LV2006SC
BS62LV2006SI
DQ4
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
8
DQ5
DQ6
8
256
Column Decoder
DQ7
CE2
CE1
WE
OE
VCC
GND
Data
Output
Buffer
Column I/O
Write Driver
Sense Amp
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Memory Array
1024 x 2048
Buffer
DQ2
•
STSOP-32
„ BLOCK DIAGRAM
DQ1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
23mA
TSOP-32
„ PIN CONFIGURATIONS
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
STSOP-32
TSOP-32
BS62LV2006SI
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
SOP-32
8
Control
Address Input Buffer
A6 A5 A10 A4 A3 A2 A1 A0
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV2006
1
Revision
1.4
Oct.
2008
BS62LV2006
„ PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 8-bit in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
WE Write Enable Input
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
OE Output Enable Input
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
There 8 bi-directional ports are used to read data from or write data into the RAM.
VCC
Power Supply
GND
Ground
„ TRUTH TABLE
MODE
CE1
CE2
WE
OE
Not selected
(Power Down)
H
X
X
X
X
L
X
X
Output Disabled
L
H
H
Read
L
H
Write
L
H
I/O OPERATION
VCC CURRENT
High Z
ICCSB, ICCSB1
H
High Z
ICC
H
L
DOUT
ICC
L
X
DIN
ICC
„ ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
RATING
(2)
-0.5
to 7.0
„ OPERATING RANGE
UNITS
RANG
AMBIENT
TEMPERATURE
V
Commercial
0 C to + 70 C
Industrial
-40 C to + 85 C
-40 to +125
O
C
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
O
O
O
2.4V ~ 5.5V
2.4V ~ 5.5V
„ CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns.
R0201-BS62LV2006
O
VCC
CIN
CIO
Input
Capacitance
Input/Output
Capacitance
VIN = 0V
6
pF
VI/O = 0V
8
pF
1. This parameter is guaranteed and not 100% tested.
2
Revision
1.4
Oct.
2008
BS62LV2006
„ DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
2.4
--
5.5
V
0.8
V
VCC
Power Supply
VIL
Input Low Voltage
-0.5
--
VIH
Input High Voltage
2.2
--
IIL
Input Leakage Current
--
--
1
UA
ILO
Output Leakage Current
--
--
1
UA
VOL
Output Low Voltage
VCC = Max, IOL = 2.0mA
--
--
0.4
V
VOH
Output High Voltage
VCC = Min, IOH = -1.0mA
2.4
--
--
V
ICC(5)
Operating Power Supply
Current
CE1 = VIL, CE2 = VIH,
(4)
IDQ = 0mA, f = FMAX
VCC=3.0V
--
--
23
VCC=5.0V
--
--
55
ICC1
Operating Power Supply
Current
CE1 = VIL, CE2 = VIH,
IDQ = 0mA, f = 1MHz
VCC=3.0V
--
--
2
VCC=5.0V
--
--
10
Standby Current – TTL
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
VCC=3.0V
--
--
0.5
VCC=5.0V
--
--
1.0
Standby Current – CMOS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN ≧VCC-0.2V or V IN ≦0.2V
VCC=3.0V
--
0.1
2.0
VCC=5.0V
--
0.6
20
ICCSB
ICCSB1(6)
(2)
VCC = Max, VIN = 0V to VCC
VCC = Max, CE1= VIH, CE2= VIL, or
OE = VIH, VI/O = 0V to VCC
O
VCC+0.3
(3)
V
mA
mA
mA
uA
4. FMAX=1/tRC.
O
5. ICC (MAX.) is 22mA/53mA at VCC=3.0V/5.0V and TA=70 C.
O
6. ICCSB1(MAX.) is 0.7uA/6.0uA at VCC=3.0V/5.0V and TA=70 C.
1. Typical characteristics are at TA=25 C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
„ DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
VDR
VCC for Data Retention
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
1.5
--
--
V
ICCDR(3)
Data Retention Current
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
--
0.05
1.0
uA
0
--
--
ns
--
--
ns
tCDR
tR
Chip Deselect to Data
Retention Time
See Retention Waveform
Operation Recovery Time
tRC
(2)
O
1. VCC=1.5V, TA=25 C and not 100% tested.
2. tRC = Read Cycle Time.
O
3. ICCRD(Max.) is 0.5uA at TA=70 C.
„ LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VCC
CE1
R0201-BS62LV2006
VCC
VDR≧1.5V
tCDR
VIH
VCC
tR
CE1≧VCC - 0.2V
3
VIH
Revision
1.4
Oct.
2008
BS62LV2006
„ LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.5V
VCC
VCC
VCC
tCDR
CE2
tR
CE2≦0.2V
VIL
VIL
„ AC TEST CONDITIONS
„ KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
Output Load
WAVEFORM
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
Others
CL = 30pF+1TTL
ALL INPUT PULSES
VCC
1 TTL
Output
90%
GND
(1)
CL
90%
10%
10%
→ ←
Rise Time :
1V/ns
→ ←
Fall Time :
1V/ns
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
1. Including jig and scope capacitance.
„ AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
CYCLE TIME : 55ns
(VCC = 3.0~5.5V)
MIN. TYP. MAX.
DESCRIPTION
CYCLE TIME : 70ns
(VCC = 2.7~5.5V)
MIN. TYP. MAX.
UNITS
tAVAX
tRC
Read Cycle Time
55
--
--
70
--
--
ns
tAVQX
tAA
Address Access Time
--
--
55
--
--
70
ns
tE1LQV
tACS1
Chip Select Access Time
(CE1)
--
--
55
--
--
70
ns
tE2HQV
tACS2
Chip Select Access Time
(CE2)
--
--
55
--
--
70
ns
tGLQV
tOE
--
--
30
--
--
35
ns
tE1LQX
tCLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
10
--
--
ns
tE2HQX
tCLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
10
--
--
ns
tGLQX
tOLZ
Output Enable to Output Low Z
5
--
--
5
--
--
ns
tE1HQZ
tCHZ1
Chip Select to Output High Z
(CE1)
--
--
30
--
--
35
ns
tE2LQZ
tCHZ2
Chip Select to Output High Z
(CE2)
--
--
30
--
--
35
ns
tGHQZ
tOHZ
Output Enable to Output High Z
--
--
25
--
--
30
ns
tAVQX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
R0201-BS62LV2006
Output Enable to Output Valid
4
Revision
1.4
Oct.
2008
BS62LV2006
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE1
tACS1
CE2
DOUT
tACS2
tCLZ
tCHZ1, tCHZ2(5)
(5)
READ CYCLE 3 (1, 4)
tRC
ADDRESS
tAA
OE
tOE
tOLZ
CE1
tACS1
tCLZ1(5)
CE2
tOH
tACS2
tCLZ2(5)
tOHZ(5)
tCHZ1(1,5)
tCHZ2(2,5)
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV2006
5
Revision
1.4
Oct.
2008
BS62LV2006
„ AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
DESCRIPTION
CYCLE TIME : 55ns
(VCC = 3.0~5.5V)
CYCLE TIME : 70ns
(VCC = 2.7~5.5V)
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
tAVAX
tWC
Write Cycle Time
55
--
--
70
--
--
ns
tE1LWH
tCW
Chip Select to End of Write
55
--
--
70
--
--
ns
tAVWL
tAS
Address Set up Time
0
--
--
0
--
--
ns
tAVWH
tAW
Address Valid to End of Write
55
--
--
70
--
--
ns
tWLWH
tWP
Write Pulse Width
30
--
--
35
--
--
ns
tWHAX
tWR1
Write Recovery Time
(CE1, WE)
0
--
--
0
--
--
ns
tE2LAX
tWR2
Write Recovery Time
(CE2)
0
--
--
0
--
--
ns
tWLQZ
tWHZ
Write to Output High Z
--
--
25
--
--
30
ns
tDVWH
tDW
Data to Write Time Overlap
25
--
--
30
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
0
--
--
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
tWHQX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
tWR1(3)
OE
tCW(11)
CE1
(5)
CE2
(5)
tAW
WE
tCW(11)
tWR2(3)
tWP(2)
tAS
tOHZ(4,10)
DOUT
tDH
tDW
DIN
R0201-BS62LV2006
6
Revision
1.4
Oct.
2008
BS62LV2006
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
CE1
tCW(11)
(5)
CE2
(5)
tAW
WE
tAS
tCW(11)
tWR2(3)
tWP(2)
tWHZ(4,10)
tOW
(7)
(8)
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62LV2006
7
Revision
1.4
Oct.
2008
BS62LV2006
„ ORDERING INFORMATION
BS62LV2006
X
X
Z
YY
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
D: DICE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
„ PACKAGE DIMENSIONS
WITH PLATING
c
b
c1
b1
BASE METAL
SECTION A-A
SOP -32
R0201-BS62LV2006
8
Revision
1.4
Oct.
2008
BS62LV2006
„ PACKAGE DIMENSIONS (continued)
„
STSOP - 32
TSOP - 32
R0201-BS62LV2006
9
Revision
1.4
Oct.
2008
BS62LV2006
„ Revision History
Revision No.
History
Draft Date
1.2
Add Icc1 characteristic parameter
Improve Iccsb1 spec.
I-grade from 30uA to 20uA at 5.0V
5.0uA to 2.0uA at 3.0V
C-grade from 10uA to 6.0uA at 5.0V
3.0uA to 0.7uA at 3.0V
Jan. 13, 2006
1.3
Change I-grade operation temperature range
- from –25OC to –40OC
May. 25, 2006
1.4
Typical value of standby current is replaced by
maximum value in Featues and Description
section
Oct. 31, 2008
Remark
Remove “-: Normal” (Leaded) PKG Material in
ordering information
Remove BGA Package
R0201-BS62LV2006
10
Revision
1.4
Oct.
2008
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