ON MC100E211FN 5v ecl 1:6 differential clock distribution chip Datasheet

MC10E211, MC100E211
5VECL 1:6 Differential
Clock Distribution Chip
Description
The MC10E/100E211 is a low skew 1:6 fanout device designed
explicitly for low skew clock distribution applications.
The E211 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open in which case it will be
pulled LOW by the input pulldown resistor) the SEL pin will select the
differential clock input.
Both a common enable and individual output enables are provided.
When asserted the positive output will go LOW on the next negative
transition of the CLK (or SCLK) input. The enabling function is
synchronous so that the outputs will only be enabled/disabled when
the outputs are already in the LOW state. In this way the problem of
runt pulse generation during the disable operation is avoided. Note that
the internal flip flop is clocked on the falling edge of the input clock
edge, therefore all associated specifications are referenced to the
negative edge of the CLK input.
The output transitions of the E211 are faster than the standard
ECLinPS edge rates. This feature provides a means of distributing
higher frequency signals than capable with the E111 device. Because
of these edge rates and the tight skew limits guaranteed in the
specification, there are certain termination guidelines which must be
followed. For more details on the recommended termination schemes
please refer to the applications information section of this data sheet.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE211FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Features
•
•
•
•
•
•
•
•
•
• ESD Protection: Human Body Model; > 2 kV,
Guaranteed Low Skew Specification
Synchronous Enabling/Disabling
Multiplexed Clock Inputs
VBB Output for Single−Ended Use
Common and Individual Enable/Disable Control
High Bandwidth Output Transistors
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE =
−4.2 V to −5.7 V
Internal Input 75 kW Pulldown Resistors
Machine Model; > 100 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
•
•
•
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 457 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 12
1
Publication Order Number:
MC10E211/D
MC10E211, MC100E211
EN4 EN5 VCC0
Q5
Q5
Q4
Q4
24
22
21
20
19
25
23
Table 1. PIN DESCRIPTION
18
Q3
27
17
Q3
28
16
VCC
VEE
1
15
Q2
CLK
2
14
Q2
CLK
3
13
Q1
VBB
4
12
Q1
EN3
26
SEL
SCLK
5
6
CEN EN2
7
8
9
10
11
EN1 EN0 VCC0 Q0
Q0
PIN
FUNCTION
EN0−EN5
SEL
SCLK
CLK, CLK
CEN
Q0−Q5, Q0−Q5
VBB
VCC, VCCO
VEE
NC
ECL Enable
ECL Select (Clock)
ECL Single Clock
ECL Differential Clock
ECL Common Enable
ECL Differential Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
*All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28 (Top View)
Q0
Table 2. FUNCTION TABLE
Q0
EN0
DQ
CLK
SCLK
SEL
ENx
Q
H/L
X
Z*
X
H/L
Z*
L
H
X
L
L
H
CLK
SCLK
L
*Z = Negative transition of CLK or SCLK
CLK
CLK
SCLK
SEL
0
BITS 1−4
Q1−4
1
Q1−4
DQ
EN1−4
CEN
Q5
Q5
EN5
DQ
VBB
Figure 2. Logic Diagram
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2
MC10E211, MC100E211
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
VEE
PECL Operating Range
NECL Operating Range
Tsol
Wave Solder
Pb
Pb−Free
VI VCC
VI VEE
22 to 26
°C/W
4.2 to 5.7
−5.7 to −4.2
V
V
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E211, MC100E211
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
119
160
Min
85°C
Typ
Max
119
160
Min
Typ
Max
Unit
119
160
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage (Single−Ended)
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage (Single−Ended)
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.74
3.65
3.75
3.69
3.81
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.4
4.6
2.4
4.6
2.4
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VE E = −5.0 V (Note 4)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
119
160
Min
85°C
Typ
Max
119
160
Min
Typ
Max
Unit
119
160
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 5)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage (Single−Ended)
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage (Single−Ended)
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
VBB
Output Voltage Reference
−1.38
−1.27
−1.35
−1.25
−1.31
−1.19
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
−2.6
−0.4
−2.6
−0.4
−2.6
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E211, MC100E211
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
119
160
Min
85°C
Typ
Max
119
160
Min
Typ
Max
Unit
137
164
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 8)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage (Single−Ended)
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
VBB
Output Voltage Reference
3.62
3.74
3.62
3.74
3.62
3.74
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
2.4
4.6
2.4
4.6
2.4
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 10)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
119
160
Min
85°C
Typ
Max
119
160
Min
Typ
Max
Unit
137
164
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 11)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
−2.6
−0.4
−2.6
−0.4
−2.6
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
10. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E211, MC100E211
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 13)
0°C
Symbol
Characteristic
fMAX
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
SEL to Q
tPHL
Disable Time
CLK or SCLK to Q (Note 15)
tskew
Part−to−Part Skew
Min
Typ
25°C
Max
Min
700
795
745
650
745
CLK (Diff) to Q
CLK (SE), SCLK to Q
Within−Device Skew (Note 14)
Typ
85°C
Max
Min
700
930
930
900
970
1065
1115
1085
1195
600
800
50
270
370
75
805
755
650
755
<1
Typ
Max
700
940
940
910
980
1075
1125
1095
1205
600
800
50
270
370
75
825
775
650
775
MHz
960
960
930
1000
1095
1145
1115
1225
600
800
270
370
75
<1
Unit
tJITTER
Random Clock Jitter (RMS)
<1
ts
Setup Time
ENx to CLK
CEN to CLK (Note 15)
200
200
−100
0
200
200
−100
0
200
200
−100
0
th
Hold Time
CLK to ENx, CEN (Note 15)
900
600
900
160
900
600
VPP
Minimum Input Swing (CLK) (Note 16)
0.25
1.0
0.25
1.0
0.25
1.0
tr
tf
Rise/Fall Times
(20 − 80%)
150
400
150
400
150
400
ps
ps
ps
ps
ps
ps
V
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
13. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
14. Within−Device skew is defined for identical transitions on similar paths through a device.
15. Setup, Hold and Disable times are all relative to a falling edge on CLK or SCLK.
16. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50 mV input swings.
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MC10E211, MC100E211
APPLICATIONS INFORMATION
General Description
situations between cards there will be no AC performance or
noise margin loss for the differential CLK inputs.
For situations where TTL clocks are required the E211 can
be interfaced with the H641 or H643 ECL to TTL Clock
Distribution Chips. The H641 is a single supply 1:9 PECL
to TTL device while the H643 is a 1:8 dual supply standard
ECL to TTL device. By combining the superior skew
performance of the E211, or E111, with the low skew
translating capabilities of the H641 and H643 very low skew
TTL clock distribution networks can be realized.
The MC10E/100E211 is a 1:6 fanout tree designed
explicitly for low skew high speed clock distribution. The
device was targeted to work in conjunction with the E111
device to provide another level of flexibility in the design
and implementation of clock distribution trees. The
individual synchronous enable controls and multiplexed
clock inputs make the device ideal as the first level
distribution unit in a distribution tree. The device provides
the ability to distribute a lower speed scan or test clock along
with the high speed system clock to ease the design of system
diagnostics and self test procedures. The individual enables
could be used to allow for the disabling of individual cards
on a backplane in fault tolerant designs.
Because of lower fanout and larger skews the E211 will
not likely be used as an alternative to the E111 for the bulk
of the clock fanout generation. Figure 3 shows a typical
application combining the two devices to take advantage of
the strengths of each.
E111
Q0
BACKPLANE
E211
Handling Open Inputs and Outputs
All of the input pins of the E211 have a 50 kW to 75 kW
pulldown resistor to pull the input to VEE when left open.
This feature can cause a problem if the differential clock
inputs are left open as the input gate current source transistor
will become saturated. Under these conditions the outputs of
the CLK input buffer will go to an undefined state. It is
recommended, if possible,that the SCLK input should be
selected any time the differential CLK inputs are allowed to
float. The SCLK buffer, under open input conditions, will
maintain a defined output state and thus the Q outputs of the
device will be in a defined state (Q = LOW). Note that if all
of the inputs are left open the differential CLK input will be
selected and the state of the Q outputs will be undefined.
With the simultaneous switching characteristics and the
tight skew specifications of the E211 the handling of the
unused outputs becomes critical. To minimize the noise
generated on the die all outputs should be terminated in
pairs, i.e. both the true and complement outputs should be
terminated even if only one of the outputs will be used in the
system. With both complementary pairs terminated the
current in the VCC pins will remain essentially constant and
thus inductance induced voltage glitches on VCC will not
occur. VCC glitches will result in distorted output
waveforms and degradations in the skew performance of the
device.
The package parasitics of the PLCC−28 cause the signals
on a given pin to be influenced by signals on adjacent pins.
The E211 is characterized and tested with all of the outputs
switching, therefore the numbers in the data book are
guaranteed only for this situation. If all of the outputs of the
E211 are not needed and there is a desire to save power the
unused output pairs can be left unterminated. Unterminated
outputs can influence the propagation delay on adjacent pins
by 15 ps − 20 ps. Therefore under these conditions this 15 ps
− 20 ps needs to be added to the overall skew of the device.
Pins which are separated by a package corner are not
considered adjacent pins in the context of propagation delay
influence. Therefore as long as all of the outputs on a single
side of the package are terminated the specification limits in
the data sheet will apply.
Q0
Q8
E111
Q5
Q0
Q8
Figure 3. Standard E211 Application
Using the E211 in PECL Designs
The E211 device can be utilized very effectively in
designs utilizing only a +5 V power supply. Since the
internal switching reference levels are biased off of the VCC
supply the input thresholds for the single−ended inputs will
vary with VCC. As a result the single−ended inputs should be
driven by a device on the same board as the E211. Driving
these inputs across a backplane where significant
differences between the VCC’s of the transmitter and
receiver can occur can lead to AC performance and/or
significant noise margin degradations. Because the
differential I/O does not use a switching reference, and due
to the CMR range of the E211, even under worst case VCC
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MC10E211, MC100E211
APPLICATIONS INFORMATION
Differential versus Single−Ended Use
IN
As can be seen from the data sheet, to minimize the skew
of the E211 the device must be used in the differential mode.
In the single−ended mode the propagation delays are
dependent on the relative position of the VBB switching
reference. Any VBB offset from the center of the input swing
will add delay to either the TPLH or TPHL and subtract delay
from the other. This increase and decrease in delay will lead
to an increase in the duty cycle skew and thus part−to−part
skew. The within−device skew will be independent of the
VBB and therefore will be the same regardless of whether the
device is driven differentially or single−ended.
For applications where part−to−part skew or duty cycle
skew are not important the advantages of single−ended
clock distribution may lead to its use. Using single−ended
interconnect will reduce the number of signal traces to be
routed, but remember that all of the complementary outputs
still need to be terminated therefore there will be no
reduction in the termination components required. To use
the E211 with a single−ended input the arrangement pictured
in Figure 5 should be used. If the input to the differential
CLK inputs are AC coupled as pictured in Figure 4 the
dependence on a centered VBB reference is removed. The
situation pictured will ensure that the input is centered
around the bias set by the VBB. As a result when AC coupled
the AC specification limits for a differential input can be
used. For more information on AC coupling please refer to
the interfacing section of the design guide in the ECLinPS
data book.
0.001mF
50 W
IN
0.01mF
VBB
Figure 4. AC Coupled Input
IN
IN
0.01 mF
Using the Enable Pins
Both the common enable (CEN) and the individual
enables (ENx) are synchronous to the CLK or SCLK input
depending on which is selected. The active low signals are
clocked into the enable flip flops on the negative edges of the
E211 clock inputs. In this way the devices will only be
disabled when the outputs are already in the LOW state. The
internal propagation delays are such that the delay to the
output through the distribution buffers is less than that
through the enable flip flops. This will ensure that the
disabling of the device will not slice any time off the clock
pulse. On initial power up the enable flip flops will randomly
attain a stable state, therefore precautions should be taken on
initial power up to ensure the E211 is in the desired state.
VBB
Figure 5. Single−Ended Input
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MC10E211, MC100E211
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E211FN
PLCC−28
37 Units / Rail
MC10E211FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E211FNR2
PLCC−28
500 / Tape & Reel
MC10E211FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E211FN
PLCC−28
37 Units / Rail
MC100E211FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E211FNR2
PLCC−28
500 / Tape & Reel
MC100E211FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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9
MC10E211, MC100E211
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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10
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E211, MC100E211
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC10E211/D
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