Maxim MAX9215ETM Programmable dc-balanced 21-bit serializer Datasheet

19-2828; Rev 3; 6/07
Programmable DC-Balanced
21-Bit Serializers
Features
The MAX9209/MAX9211/MAX9213/MAX9215 serialize
21 bits of LVTTL/LVCMOS parallel input data to three
LVDS outputs. A parallel rate clock on a fourth LVDS
output provides timing for deserialization.
The MAX9209/MAX9211/MAX9213/MAX9215 feature
programmable DC balance, which allows isolation
between the serializer and deserializer using AC-coupling. The DC balance circuits on each channel code
the data, limiting the imbalance of transmitted ones and
zeros to a defined range. The companion MAX9210/
MAX9212/MAX9214/MAX9216 deserializers decode the
data. When DC balance is not programmed, the serializers are compatible with non-DC-balanced, 21-bit serializers like the DS90CR215 and DS90CR217.
Two frequency ranges and two DC-balance default
conditions are available for maximum replacement flexibility and compatibility with existing non-DC-balanced
serializers.
♦ Programmable DC-Balanced or Non-DC-Balanced
Operation
♦ DC Balance Allows AC-Coupling for Ground-Shift
Tolerance
♦ As Low as 8MHz Operation
♦ Pin Compatible with DS90CR215 and DS90CR217
in Non-DC-Balanced Mode
♦ Integrated 110Ω (DC-Balanced) and 410Ω (NonDC-Balanced) Output Resistors
♦ 5V Tolerant LVTTL/LVCMOS Data Inputs
♦ PLL Requires No External Components
♦ Up to 1.785Gbps Throughput
Automotive Navigation Systems
♦ LVDS Outputs Meet IEC 61000-4-2 and ISO 10605
Requirements
♦ LVDS Outputs Conform to ANSI TIA/EIA-644
LVDS Standard
♦ Low-Profile 48-Lead TSSOP and Space-Saving
QFN Packages
♦ -40°C to +85°C Operating Temperature Range
Automotive DVD Entertainment Systems
♦ +3.3V Supply
The MAX9209/MAX9211/MAX9213/MAX9215 are available in TSSOP and space-saving thin QFN packages.
Applications
Digital Copiers
Laser Printers
Ordering Information
Functional Diagram
PART
MAX9209
MAX9211
MAX9213
MAX9215
TxIN 0 - 20
LVDS DRIVER 0
TxOUT0+
21
TIMING
CONTROL
DCB/NC
PARALLEL-TOSERIAL
CONVERTER
AND
DC-BALANCE
LOGIC
TxOUT0LVDS DRIVER 1
TxOUT1+
TxOUT1LVDS DRIVER 2
TxOUT2+
PLL
7X OR 9X
PIN-PACKAGE
48 Thin QFN-EP**
MAX9209EUM
-40°C to +85°C
48 TSSOP
MAX9209GUM
-40°C to +105°C
48 TSSOP
MAX9211ETM*
-40°C to +85°C
48 Thin QFN-EP**
MAX9211EUM*
-40°C to +85°C
48 TSSOP
MAX9213ETM*
-40°C to +85°C
48 Thin QFN-EP**
MAX9213EUM
-40°C to +85°C
48 TSSOP
MAX9215ETM*
-40°C to +85°C
48 Thin QFN-EP**
MAX9215EUM*
-40°C to +85°C
48 TSSOP
TxOUT2-
*Future product—contact factory for availability.
TxCLK OUT+
**EP = Exposed pad.
LVDS CLK
TxCLK IN
TEMP RANGE
-40°C to +85°C
MAX9209ETM*
CLOCK
GENERATOR
TxCLK OUT-
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX9209/MAX9211/MAX9213/MAX9215
General Description
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.5V to +4.0V
LVDS Outputs (TxOUT_, TxCLK OUT_) to GND ...-0.5V to +4.0V
5V Tolerant LVTTL/LVCMOS Inputs
(TxIN_, TxCLK IN, PWRDWN) to GND ..............-0.5V to +6.0V
(DCB/NC) to GND ......................................-0.5V to (VCC + 0.5V)
LVDS Outputs (TxOUT_, TxCLK OUT_)
Short to GND and Differential Short .......................Continuous
Continuous Power Dissipation (TA = +70°C)
48-Pin TSSOP (derate 16mW/°C above +70°C) ....... 1282mW
48-Lead QFN (derate 26.3mW/°C above +70°C) ......2105mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
ESD Protection
Human Body Model (RD = 1.5kΩ, CS = 100pF)
All Pins to GND..............................................................±2kV
IEC 61000-4-2 (RD = 330Ω, CS = 150pF)
Contact Discharge (TxOUT_, TxCLK OUT_) to GND ....±8kV
Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND ..±15kV
ISO 10605 (RD = 2kΩ, CS = 330pF)
Contact Discharge (TxOUT_, TxCLK OUT_) to GND ....±8kV
Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND ..±25kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC
= +3.3V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (TxIN_, TxCLK IN, PWRDWN, DCB/NC)
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Input Current
IIN
Input Clamp Voltage
VCL
TxIN_, TxCLK IN, PWRDWN
2.0
5.5
DCB/NC
2.0
VCC +
0.3
-0.3
+0.8
V
-20
+20
µA
-0.9
-1.5
V
350
450
mV
2
25
mV
1.25
1.375
V
10
30
mV
VIN = high or low, PWRDWN = high or low
ICL = -18mA
V
LVDS OUTPUTS (TxOUT_, TxCLK OUT)
Differential Output Voltage
Change in VOD Between
Complementary Output States
Output Offset Voltage
Change in VOS Between
Complementary Output States
Output Short-Circuit Current
Magnitude of Differential Output
Short-Circuit Current
VOD
Figure 1
ΔVOD
Figure 1
VOS
Figure 1
ΔVOS
Figure 1
IOS
IOSD
Output High-Impedance Current
2
RO
IOZ
1.125
VOUT+ or VOUT- = 0V or VCC,
non-DC-balanced mode
-10
±5.7
+10
VOUT+ or VOUT- = 0V or VCC,
DC-balanced mode
-15
±8.2
+15
VOD = 0V, non-DC-balanced mode
(Note 3)
5.7
10
VOD = 0V, DC-balanced mode (Note 3)
8.2
15
DC-balanced mode
Differential Output Resistance
250
Non-DC-balanced
mode
-40°C to +105°C
-40°C to +105°C
PWRDWN = low or VCC = 0V,
VOUT+ = 0V or 3.6V, VOUT- = 0V or 3.6V
mA
78
110
147
78
110
150
292
410
547
292
410
564
-0.5
±0.1
+0.5
_______________________________________________________________________________________
mA
Ω
µA
Programmable DC-Balanced
21-Bit Serializers
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC
= +3.3V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
DC-balanced mode,
worst-case pattern,
CL = 5pF, Figure 2
Worst-Case Supply Current
ICCW
Non-DC-balanced
mode, worst-case
pattern, CL = 5pF,
Figure 2
Power-Down Supply Current
ICCZ
PWRDWN = low
MIN
TYP
MAX
8MHz
MAX9209/MAX9211
40
54
16MHz
MAX9209/MAX9211
48
68
34MHz
MAX9209/MAX9211
71
90
16MHz
MAX9213/MAX9215
46
64
34MHz
MAX9213/MAX9215
59
87
66MHz
MAX9213/MAX9215
94
108
10MHz
MAX9209/MAX9211
30
39
20MHz
MAX9209/MAX9211
37
53
33MHz
MAX9209/MAX9211
49
70
40MHz
MAX9209/MAX9211
56
75
20MHz
MAX9213/MAX9215
36
49
33MHz
MAX9213/MAX9215
45
62
40MHz
MAX9213/MAX9215
49
70
66MHz
MAX9213/MAX9215
68
89
85MHz
MAX9213/MAX9215
83
100
17
50
UNITS
mA
µA
_______________________________________________________________________________________
3
MAX9209/MAX9211/MAX9213/MAX9215
DC ELECTRICAL CHARACTERISTICS (continued)
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values
are at VCC = +3.3V, TA = +25°C.) (Notes 4, 5)
PARAMETER
SYMBOL
LVDS Low-to-High Transition
Time
LLHT
Figure 3
LVDS High-to-Low Transition
Time
LHLT
Figure 3
TxCLK IN Transition Time
TCIT
Figure 4
CONDITIONS
MAX9209/MAX9211
MIN
150
TYP
280
MAX
400
MAX9213/MAX9215
150
260
350
MAX9209/MAX9211
150
280
400
MAX9213/MAX9215
150
260
350
4
UNITS
ps
ps
ns
10MHz
N/7 x TCIP
N/7 x TCIP
N/7 x TCIP
MAX9209/MAX9211
- 0.25
+ 0.25
20MHz
N/7 x TCIP
N/7 x TCIP
N/7 x TCIP
MAX9209/MAX9211
- 0.15
+ 0.15
N = 0, 1, 2, 3,
4, 5, 6
non-DCbalanced mode,
Figure 5 (Note 6)
40MHz
N/7 x TCIP
N/7 x TCIP
N/7 x TCIP
MAX9209/MAX9211
- 0.1
+ 0.1
20MHz
N/7 x TCIP
N/7 x TCIP
N/7 x TCIP
MAX9213/MAX9215
- 0.25
+ 0.25
40MHz
N/7 x TCIP
N/7 x TCIP
N/7 x TCIP
MAX9213/MAX9215
- 0.15
+ 0.15
N/7 x TCIP
85MHz
N/7 x TCIP
N/7 x TCIP
+ 0.1
MAX9213/MAX9215
- 0.1
Output Pulse Position
TPPosN
ns
N/9 x TCIP
8MHz
N/9 x TCIP
N/9 x TCIP
+ 0.25
MAX9209/MAX9211
- 0.25
N/9 x TCIP
16MHz
N/9 x TCIP
N/9 x TCIP
+ 0.15
MAX9209/MAX9211
- 0.15
N = 0, 1, 2, 3,
4, 5, 6, 7, 8
DC-balanced
mode, Figure 6
(Note 6)
N/9 x TCIP
34MHz
N/9 x TCIP
N/9 x TCIP
+ 0.1
MAX9209/MAX9211
- 0.1
N/9 x TCIP
16MHz
N/9 x TCIP
N/9 x TCIP
+ 0.25
MAX9213/MAX9215
- 0.25
N/9 x TCIP
34MHz
N/9 x TCIP
N/9 x TCIP
+ 0.15
MAX9213/MAX9215
- 0.15
66MHz
N/9 x TCIP
N/9 x TCIP
N/9 x TCIP
MAX9213/MAX9215
- 0.1
+ 0.1
4
_______________________________________________________________________________________
Programmable DC-Balanced
21-Bit Serializers
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values
are at VCC = +3.3V, TA = +25°C.) (Notes 4, 5)
PARAMETER
TxCLK IN High Time
SYMBOL
TCIH
Figure 7
CONDITIONS
MIN
0.3 x TCIP
TxCLK IN Low Time
TCIL
Figure 7
0.3 x TCIP
TxIN to TxCLK IN Setup
TSTC
Figure 7
2.2
TxIN to TxCLK IN Hold
THTC
Figure 7
ns
DC-balanced mode, Figure 8
4.7
5.9
7.2
Figure 9
Serializer Power-Down Delay
TPDD
Figure 10
VOD
0
6.0
TPLLS
ns
32800 x
TCIP
ns
50
ns
2
ns
14
595Mbps data rate, worst-case pattern
ns
ns
4.5
Serializer Phase-Locked Loop Set
Magnitude of Differential Output
Voltage
0.7 x TCIP
3.5
TCCD
TJIT
MAX
UNITS
0.7 x TCIP
ns
Non-DC-balanced mode, Figure 8
TxCLK IN to TxCLK OUT Delay
TxCLK IN Cycle-to-Cycle Jitter
(Input Clock Requirement)
TYP
250
mV
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VOD , ΔVOD, and ΔVOS.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Guaranteed by design.
Note 4: TCIP is the period of TxCLK IN.
Note 5: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 6: Pulse position TPPosN is characterized using 27 - 1 PRBS data.
Typical Operating Characteristics
(VCC = +3.3V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, TA = +25°C, unless otherwise noted.)
WORST-CASE
PATTERN
60
27 - 1 PRBS
80
WORST-CASE
PATTERN
60
40
20
10
20
30
FREQUENCY (MHz)
40
50
MAX9213
NON-DC-BALANCED MODE
100
80
WORST-CASE
PATTERN
60
27 - 1 PRBS
40
27 - 1 PRBS
20
20
0
120
MAX9209 toc02
MAX9209
NON-DC-BALANCED MODE
SUPPLY CURRENT (mA)
80
40
100
MAX9209 toc01
MAX9209
DC-BALANCED MODE
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
100
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
MAX9209 toc03
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
0
10
20
30
40
FREQUENCY (MHz)
50
60
15
30
45
60
75
90
FREQUENCY (MHz)
_______________________________________________________________________________________
5
MAX9209/MAX9211/MAX9213/MAX9215
AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, TA = +25°C, unless otherwise noted.)
MAX9213
DC-BALANCED MODE
100
2m OF CAT-5
UTP CABLE
TxCLK IN = 85MHz
DC-COUPLED
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE
MAX9209 TOC05
MAX9209 toc04
120
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE
5m OF CAT-5
UTP CABLE
TxCLK IN = 85MHz
DC-COUPLED
WORST-CASE
PATTERN
80
100mV/div
100mV/div
0V
DIFFERENTIAL
0V
DIFFERENTIAL
60
27 - 1 PRBS
40
ALL-CHANNELS
SWITCHING
20
15
30
45
75
60
27 - 1 PRBS PATTERN
100Ω TERMINATION
27 - 1 PRBS PATTERN
100Ω TERMINATION
ALL-CHANNELS
SWITCHING
300ps/div
300ps/div
FREQUENCY (MHz)
100mV/div
100mV/div
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
2m OF CAT-5
UTP CABLE
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
300ps/div
MAX9213
EYE DIAGRAM—DC-BALANCED MODE
MAX9213
EYE DIAGRAM—DC-BALANCED MODE
5m OF CAT-5
UTP CABLE
100mV/div
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
300ps/div
MAX9209 TOC09
300ps/div
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
6
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
MAX9209 TOC08
10m OF CAT-5
UTP CABLE
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
100mV/div
10m OF CAT-5
UTP CABLE
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
300ps/div
_______________________________________________________________________________________
MAX9209 TOC10
TxCLK IN = 85MHz
DC-COUPLED
MAX9213
EYE DIAGRAM—DC-BALANCED MODE
MAX9209 TOC07
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE
MAX9209 TOC06
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
SUPPLY CURRENT (mA)
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
Programmable DC-Balanced
21-Bit Serializers
PIN
TSSOP
QFN
1, 3, 4, 44, 45, 47, 48,
38, 39, 41, 42, 43, 45, 46
NAME
TxIN0–TxIN6
FUNCTION
5V Tolerant LVTTL/LVCMOS Channel 0 Data Inputs.
Internally pulled down to GND.
2, 8, 14, 21
2, 8, 15, 44
VCC
Digital Supply Voltage
5, 11, 17, 24, 46
5, 11, 18, 40, 47
GND
Ground
6, 7, 9, 10, 12, 13, 15
1, 3, 4, 6, 7, 9, 48
TxIN7–TxIN13
5V Tolerant LVTTL/LVCMOS Channel 1 Data Inputs.
Internally pulled down to GND.
16, 18, 19, 20, 22, 23, 25
10, 12, 13, 14, 16, 17, 19
TxIN14–TxIN20
5V Tolerant LVTTL/LVCMOS Channel 2 Data Inputs.
Internally pulled down to GND.
26
20
TxCLK IN
5V Tolerant LVTTL/LVCMOS Parallel Rate Clock Input.
Internally pulled down to GND.
27
21
PWRDWN
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally
pulled down to GND. Outputs are high impedance when
PWRDWN = low or open.
28, 30
22, 24
PLL GND
PLL Ground
29
23
PLL VCC
PLL Supply Voltage
31, 36, 42
25, 30, 36
LVDS GND
32
26
TxCLK OUT+
33
27
TxCLK OUT-
34
28
TxOUT2+
Noninverting Channel 2 LVDS Serial Data Output
35
29
TxOUT2-
Inverting Channel 2 LVDS Serial Data Output
37
31
LVDS VCC
LVDS Supply Voltage
38
32
TxOUT1+
Noninverting Channel 1 LVDS Serial Data Output
39
33
TxOUT1-
Inverting Channel 1 LVDS Serial Data Output
40
34
TxOUT0+
Noninverting Channel 0 LVDS Serial Data Output
41
35
TxOUT0-
Inverting Channel 0 LVDS Serial Data Output
LVTTL/LVCMOS DC-Balance Programming Input:
MAX9209: pulled up to VCC
MAX9211: pulled down to GND
MAX9213: pulled up to VCC
MAX9215: pulled down to GND
See Table 1.
43
37
DCB/NC
—
EP
EP
LVDS Ground
Noninverting LVDS Parallel Rate Clock Output
Inverting LVDS Parallel Rate Clock Output
Exposed Paddle. Solder to ground.
_______________________________________________________________________________________
7
MAX9209/MAX9211/MAX9213/MAX9215
Pin Description
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
TxOUT_- OR TxCLK OUT-
VOS(-)
VOS(+)
VOS(-)
TxOUT_+ OR TxCLK OUT+
ΔVOS = |VOS(+) - VOS(-)|
VOD(+)
0V
ΔVOD = |VOD(+) - VOD(-)|
VOD(-)
VOD(-)
(TxOUT_+) - (TxOUT_-) OR
(TxCLK OUT+) - (TxCLK OUT-)
Figure 1. LVDS Output DC Parameters
TCIP
TxCLK IN
ODD TxIN
EVEN TxIN
Figure 2. Worst-Case Test Pattern
TxOUT_+ OR
TxCLK OUT+
80%
80%
RL
TxOUT_- OR
TxCLK OUT-
CL
CL
20%
(TxOUT_+) - (TxOUT_-) OR
(TxCLK OUT+) - (TxCLK OUT-)
20%
LLHT
LHLT
Figure 3. LVDS Output Load and Transition Times
VIH
90%
90%
10%
10%
TxCLK IN
TCIT
VIL
TCIT
Figure 4. Clock Transition Time Waveform
8
_______________________________________________________________________________________
Programmable DC-Balanced
21-Bit Serializers
CYCLE N - 1
CYCLE N
TxOUT2
(SINGLE ENDED)
TxIN15
TxIN14
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxOUT1
(SINGLE ENDED)
TxIN8
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxOUT0
(SINGLE ENDED)
TxIN1
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Figure 5. Non-DC-Balanced Mode LVDS Output Pulse Position Measurement
Detailed Description
The MAX9209/MAX9211 operate at a parallel clock frequency of 8MHz to 34MHz in DC-balanced mode and
10MHz to 40MHz in non-DC-balanced mode. The
MAX9213/MAX9215 operate at a parallel clock frequency of 16MHz to 66MHz in DC-balanced mode and
20MHz to 85MHz in non-DC-balanced mode.
DC-balanced or non-DC-balanced operation is controlled by the DCB/NC pin (see Table 1). In non-DCbalanced mode, each channel serializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are serialized every clock cycle (7 data bits + 2 DC-balance bits). The highest data rate in DC-balanced mode
for the MAX9213 or MAX9215 is 66MHz x 9 = 594Mbps.
In non-DC-balanced mode, the maximum data rate is
85MHz x 7 = 595Mbps. A bit time is 1 divided by the
data rate, for example, 1 / 595Mbps = 1.68ns.
DC Balance
Through data coding, the DC-balance circuits limit the
imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary one transmitted
and -1 is assigned to each binary zero transmitted, the
Table 1. DC-Balance Programming
DEVICE
MAX9209
MAX9211
MAX9213
MAX9215
DCB/NC
OPERATING
MODE
OPERATING
FREQUENCY
(MHz)
High or open
DC balanced
8 to 34
Low
Non-DC
balanced
10 to 40
High
DC balanced
8 to 34
Low or open
Non-DC
balanced
10 to 40
High or open
DC balanced
16 to 66
Low
Non-DC
balanced
20 to 85
High
DC balanced
16 to 66
Low or open
Non-DC
balanced
20 to 85
variation in the running sum of assigned values is
called the digital sum variation (DSV). The maximum
DSV for the MAX9209/MAX9211/MAX9213/MAX9215
_______________________________________________________________________________________
9
MAX9209/MAX9211/MAX9213/MAX9215
TxCLK OUT
(DIFFERENTIAL)
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
TxCLK OUT
(DIFFERENTIAL)
CYCLE N - 1
CYCLE N
TxOUT2
(SINGLE ENDED)
DCA2
DCB2
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
DCA2
DCB2
TxOUT1
(SINGLE ENDED)
DCA1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA1
DCB1
TxOUT0
(SINGLE ENDED)
DCA0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
DCA0
DCB0
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos7
TPPos8
Figure 6. DC-Balanced Mode LVDS Output Pulse Position Measurement
TCIP
2.0V
TxCLK IN
TCIH
1.5V
0.8V
TCIL
TSTC
TxIN 0:20
1.5V
SETUP
THTC
HOLD
1.5V
Figure 7. Setup and Hold, High and Low Times
1.5V
TxCLK IN
TxCLK OUT+
TxCLK OUT-
TCCD
DIFFERENTIAL 0
Figure 8. Clock-In to Clock-Out Delay
10
______________________________________________________________________________________
Programmable DC-Balanced
21-Bit Serializers
MAX9209/MAX9211/MAX9213/MAX9215
2.0V
PWRDWN
3.6V
3.0V
VCC
TPPLS
TxCLK IN
TxOUT_, TxCLK OUT
VOD = 0
HIGH-Z
DIFFERENTIAL 0
Figure 9. PLL Set Time
PWRDWN
0.8V
TxCLK IN
TPDD
TxOUT_, TxCLK OUT
HIGH-Z
Figure 10. Power-Down Delay
TxCLK OUT+
TxCLK OUTCYCLE N - 1
DCA2
CYCLE N
CYCLE N + 1
DCB2
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
DCA2
DCB2
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
DCA0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxOUT2
DCA1
TxOUT1
DCA0
TxOUT0
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
data channels is 10. At most, 10 more zeros than ones,
or 10 more ones than zeros, are transmitted. The maximum DSV for the clock channel is 5. Limiting the DSV
and choosing the correct coupling capacitors maintain
differential signal amplitude and reduce jitter due to
droop on AC-coupled links.
To obtain DC balance on the data channels, the parallel
input data is inverted or not inverted, depending on the
sign of the digital sum at the word boundary. Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9210/MAX9212/
MAX9214/MAX9216 deserializers whether the data bits
are inverted (Figure 11). The deserializer restores the
original state of the parallel data. The LVDS clock signal
alternates duty cycles of 4/9 and 5/9, which maintains
DC balance. Figure 12 shows the non-DC-balanced
mode inputs mapped to LVDS outputs.
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be eliminated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the
______________________________________________________________________________________
11
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
TxCLK OUT+
TxCLK OUTCYCLE N - 1
TxIN15
CYCLE N
CYCLE N + 1
TxIN14
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxOUT2
TxIN8
TxOUT1
TxIN1
TxOUT0
Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
MAX9209
MAX9211
MAX9213
MAX9215
MAX9210
MAX9212
MAX9214
MAX9216
TRANSMISSION LINE
TxOUT
7
RxIN
7
7:1
RO
RT =
100Ω
1:7
7:1
RO
RT =
100Ω
1:7
7:1
RO
RT =
100Ω
1:7
PLL
RO
RT =
100Ω
PLL
7
7
TxIN
7
PWRDWN
TxCLK IN
TxCLK OUT
21:3 SERIALIZER
RxOUT
7
PWRDWN
RxCLK OUT
RxCLK IN
3:21 DESERIALIZER
Figure 13. DC-Coupled Link, Non-DC-Balanced Mode
common-mode voltage range of an LVDS receiver to
nearly the voltage rating of the capacitor. The typical
LVDS driver output is 350mV centered on an offset voltage of 1.25V, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
12
from 0V to 2.4V, allowing approximately ±1V commonmode difference between the driver and receiver on a
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V 0V = 1.075V). Figure 13 shows the DC-coupled link,
non-DC-balanced mode.
______________________________________________________________________________________
Programmable DC-Balanced
21-Bit Serializers
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT
SERIALIZER INSTEAD OF DESERIALIZER.
TxOUT
RxIN
7
7
(7 + 2):1
RO
RT =
100Ω
1:(9 - 2)
(7 + 2):1
RO
RT =
100Ω
1:(9 - 2)
(7 + 2):1
RO
RT =
100Ω
1:(9 - 2)
PLL
RO
RT =
100Ω
PLL
7
TxIN
MAX9210
MAX9212
MAX9214
MAX9216
7
PWRDWN
TxCLK IN
TxCLK OUT
7
RxOUT
7
PWRDWN
RxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 14. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than ±1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the differential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
5V Tolerant Inputs
All signal and control inputs except DCB/NC are 5V tolerant and are internally pulled down to GND. The
DCB/NC pin has a pulldown on MAX9211/MAX9215
and a pullup on the MAX9209/MAX9213.
DCB/NC Pin Default Conditions
The MAX9209/MAX9211/MAX9213/MAX9215 have programmable DC balance/non-DC balance. See Table 1
for DCB/NC default settings and operating modes.
______________________________________________________________________________________
13
MAX9209/MAX9211/MAX9213/MAX9215
MAX9209
MAX9211
MAX9213
MAX9215
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
MAX9209
MAX9211
MAX9213
MAX9215
MAX9210
MAX9212
MAX9214
MAX9216
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
TxOUT
RxIN
7
RO
RT =
100Ω
1:(9 - 2)
(7 + 2):1
RO
RT =
100Ω
1:(9 - 2)
(7 + 2):1
RO
RT =
100Ω
1:(9 - 2)
PLL
RO
RT =
100Ω
PLL
7
TxIN
7
(7 + 2):1
7
PWRDWN
TxCLK IN
TxCLK OUT
7
RxOUT
7
PWRDWN
RxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 15. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (RT), the LVDS driver
output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value
series capacitors is (C x (RT + RO)) / 2 (Figure 14). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO)) / 4 (Figure 15).
14
RT is required to match the transmission line impedance (usually 100Ω) and RO is determined by the LVDS
driver design, with a minimum value of 78Ω (see the DC
Electrical Characteristics table). This leaves the capacitor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1)
where:
C = AC-coupling capacitor (F)
tB = bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
RT = termination resistor (Ω)
______________________________________________________________________________________
Programmable DC-Balanced
21-Bit Serializers
lock to the input clock and switches in the output termination resistors. The LVDS outputs are not driven until
the PLL locks. The differential output resistance pulls
the outputs together and the LVDS outputs are high
impedance to ground. If the power supply is turned off,
the output resistors are switched out and the LVDS outputs are high impedance.
C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO))
C = -(2 x 13.9ns x 10) / (ln (1 - .02) x (100Ω + 78Ω))
C = 0.0773µF
Jitter due to droop is proportional to the droop and
transition time:
The PLL lock time is set by an internal counter. The maximum time to lock is 32,800 clock periods. Power and
clock should be stable to meet the lock-time specification. When the PLL is locking, the LVDS outputs are not
active and have a differential output resistance of RO.
tJ = tT x D (Eq 2)
where:
tJ = jitter (s)
tT = transition time (s) (0% to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tJ = 1ns x 0.02
tJ = 20ps
There are separate power domains for LVDS, PLL, and
digital circuits. Bypass each LVDS VCC, PLL VCC, and
VCC pin with high-frequency surface-mount ceramic
0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smallest value capacitor
closest to the supply pin.
The transition time in a real system depends on the frequency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 15) is:
C = -(4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3)
Integrated Termination
The MAX9209/MAX9211/MAX9213/MAX9215 have an
integrated output termination resistor across each of
the four LVDS outputs. These resistors damp reflections
from induced noise and mismatches between the transmission line impedance and termination resistor at the
deserializer input. In DC-balanced mode, the differential output resistance is part of the RC time constant. In
non-DC-balanced mode, the output termination is
increased to 410Ω (typ) to reduce power. In powerdown mode (PWRDWN = low) or when the power supply is off, the output resistor is switched out and the
LVDS outputs are high impedance.
PLL Lock Time
Power-Supply Bypassing
LVDS Outputs
The LVDS outputs are current sources. The voltage
swing is proportional to the load impedance. The outputs are rated for a differential load of 100Ω ±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS input and LVDS output signals separated to prevent crosstalk. A four-layer PCB
with separate layers for power, ground, LVDS outputs,
and digital signals is recommended.
PWRDWN and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated output termination resistors, puts the LVDS
outputs in high impedance, and reduces supply current
to 50µA or less. Driving PWRDWN high starts the PLL
______________________________________________________________________________________
15
MAX9209/MAX9211/MAX9213/MAX9215
RO = output resistance (Ω)
Equation 1 is for two series capacitors (Figure 14). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capacitors (Figure 15).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
ESD Protection
The MAX9209/MAX9211/MAX9213/MAX9215 ESD tolerance is rated for IEC 61000-4-2, Human Body Model
and ISO 10605 standards. IEC 61000-4-2 and ISO
10605 specify ESD tolerance for electronic systems.
The IEC 61000-4-2 discharge components are CS =
150pF and RD = 330Ω (Figure 16). For IEC 61000-4-2,
the LVDS outputs are rated for ±8kV contact and ±15kV
50Ω TO 100Ω
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
CS
150pF
RD
330Ω
1MΩ
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
CHARGE-CURRENTLIMIT RESISTOR
DEVICE
UNDER
TEST
Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit
50Ω TO 100Ω
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
CS
330pF
air discharge. The Human Body Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 17).
For the Human Body Model, all pins are rated for ±2kV
contact discharge. The ISO 10605 discharge components are CS = 330pF and RD = 2kΩ (Figure 18). For
ISO 10605, the LVDS outputs are rated for ±8kV contact and ±25kV air discharge.
HIGHVOLTAGE
DC
SOURCE
CS
100pF
RD
1.5kΩ
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Figure 17. Human Body ESD Test Circuit
RD
2kΩ
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 18. ISO 10605 Contact Discharge ESD Test Circuit
16
______________________________________________________________________________________
DEVICE
UNDER
TEST
Programmable DC-Balanced
21-Bit Serializers
LVDS VCC
TxIN12 13
36
LVDS GND
VCC 14
35
TxOUT2-
TxIN13
15
34
TxOUT2+
TxIN14
16
33
TxCLK OUT-
GND 17
32
TxCLK OUT+
TxIN15 18
31
LVDS GND
TxIN16 19
30
PLL GND
TxIN17 20
29
PLL VCC
21
28
PLL GND
TxIN18 22
27
PWRDWN
TxIN19
23
26
TxCLK IN
GND 24
25
TxIN20
VCC
TxIN1
TxIN0
DCB/NC
37
38
39
36
2
35
3
34
4
33
5
32
TxIN12
VCC
7
TxIN13
TxIN14
GND
9
10
TxIN15
12
6
31
MAX9209
MAX9211
MAX9213
MAX9215
8
30
29
28
27
11
26
EXPOSED PAD
25
LVDS GND
TxOUT0TxOUT0+
TxOUT1TxOUT1+
LVDS VCC
LVDS GND
TxOUT2TxOUT2+
TxCLK OUTTxCLK OUT+
LVDS GND
24
37
1
23
TxIN11 12
40
TxOUT1+
TxIN8
VCC
TxIN9
TxIN10
GND
TxIN11
22
38
GND 11
41
TxOUT1-
21
TxOUT0+
39
MAX9209
MAX9211
MAX9213
MAX9215
20
40
TxIN9 9
TxIN10 10
TxCLK IN
PWRDN
PLL GND
PLL VCC
PLL GND
TxOUT0-
TxIN4
TxIN3
TxIN2
GND
41
42
VCC 8
43
LVDS GND
19
DCB/NC
42
18
43
TxIN8 7
TxIN5
VCC
TxIN7 6
44
TxIN0
45
44
17
GND 5
46
TxIN1
16
GND
45
15
46
TxIN6 4
TxIN7
TxIN5 3
GND
TxIN6
TxIN2
47
47
14
VCC 2
13
TxIN3
TxIN17
VCC
TxIN18
TxIN19
GND
TxIN20
48
TxIN16
TxIN4 1
48
TOP VIEW
Thin QFN
TSSOP
Chip Information
MAX9209 TRANSISTOR COUNT: 9458
MAX9211 TRANSISTOR COUNT: 9458
MAX9213 TRANSISTOR COUNT: 9458
MAX9215 TRANSISTOR COUNT: 9458
PROCESS: CMOS
______________________________________________________________________________________
17
MAX9209/MAX9211/MAX9213/MAX9215
Pin Configurations
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
48L TSSOP.EPS
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
N
MARKING
AAA A
E
H
1 2 3
TOP VIEW
BOTTOM VIEW
SEE DETAIL A
b
A1
A2
A
CL
e
D
c
END VIEW
SEATING
PLANE
SIDE VIEW
(
b
)
PARTING
LINE
0.25
L
b1
WITH PLATING
DETAIL A
NOTES:
1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE.
3. CONTROLLING DIMENSION: MILLIMETERS.
4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED (48L), EE (56L).
5. "N" REFERS TO NUMBER OF LEADS.
6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL
PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE
FROM (-C-) IN THE DIRECTION INDICATED.
7. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
8. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
c1
BASE METAL
SECTION C-C
PACKAGE OUTLINE,
48 & 56L TSSOP, 6.1mm BODY
21-0155
18
c
______________________________________________________________________________________
C
1
1
Programmable DC-Balanced
21-Bit Serializers
DETAIL A
32, 44, 48L QFN.EPS
E
(NE-1) X e
E/2
k
e
D/2
C
L
(ND-1) X e
D
D2
D2/2
b
L
E2/2
C
L
k
E2
C
L
C
L
L
L
e
A1
A2
e
A
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
1
2
______________________________________________________________________________________
19
MAX9209/MAX9211/MAX9213/MAX9215
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX9209/MAX9211/MAX9213/MAX9215
Programmable DC-Balanced
21-Bit Serializers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
2
2
___________________Revision History
Pages changed at Rev 3: 1–5, 9, 14, 15, 18, 19, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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