Catalyst CAT522JI-TE10 Configured digitally programmable potentiometer Datasheet

H
CAT522
EE
GEN FR
ALO
Configured Digitally Programmable Potentiometer (DPP™):
Programmable Voltage Applications
LE
FEATURES
APPLICATIONS
■ Two 8-bit DPPs configured as programmable
■ Automated product calibration.
voltage sources in DAC-like applications
A D F R E ETM
■ Remote control adjustment of equipment
■ Independent reference inputs
■ Offset, gain and zero adjustments in self-
■ Non-volatile NVRAM memory wiper storage
calibrating and adaptive control systems.
■ Output voltage range includes both supply rails
■ Tamper-proof calibrations.
■ 2 independently addressable buffered
■ DAC (with memory) substitute.
output wipers
■ 1 LSB accuracy, high resolution
■ Serial Microwire-like interface
■ Single supply operation: 2.7V - 5.5V
■ Setting read-back without effecting outputs
DESCRIPTION
dithered to test new output values without effecting the
stored settings and stored settings can be read back
without disturbing the DPP's output.
The CAT522 is a dual, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The CAT522 is controlled with a simple 3-wire, microwirelike serial interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the CAT522 Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of the non-volatile NVRAM memory Erase/Write cycle.
The CAT522 offers two independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail opamps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically
reinstated when power is returned. Each wiper can be
The CAT522 is available in the 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges. Both 14-pin plastic DIP and surface mount
packages are available.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
RDY/BSY
3
PROG
DI
CLK
CS
7
VREFH1 VREFH2
V
DD
14
1
DIP Package (P, L)
PROGRAM
CONTROL
VDD
1
14
VREFH1
VDD
1
14
VREFH1
CLK
2
13
VREFH2
CLK
2
13
VREFH2
RDY/BSY
3
12
VOUT1 RDY/BSY
3
12
VOUT1
CS
4
11
VOUT2
CS
4
11
VOUT2
DI
5
10
VREFL2
DI
5
10
VREFL2
DO
6
9
VREFL1
DO
6
9
VREFL1
PROG
7
8
GND
PROG
7
8
GND
5
2
SERIAL
CONTROL
+
WIPER
CONTROL
REGISTERS
AND
NVRAM
SOIC Package (J, W)
13
11
24KΩ
4
+
24kΩ
SERIAL
DATA
OUTPUT
REGISTER
12
V
OUT2
V
OUT1
6
DO
CAT522
CAT522
CAT522
8
GND
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
10
VREFL1 VREFL2
1
Doc. No. 2004, Rev. E
CAT522
ABSOLUTE MAXIMUM RATINGS
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix) ........................ -40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
Supply Voltage*
VDD to GND ...................................... -0.5V to +7V
Inputs
CLK to GND ............................ -0.5V to VDD +0.5V
CS to GND .............................. -0.5V to VDD +0.5V
DI to GND ............................... -0.5V to VDD +0.5V
RDY/BSY to GND ................... -0.5V to VDD +0.5V
PROG to GND ........................ -0.5V to VDD +0.5V
VREFH to GND ........................ -0.5V to VDD +0.5V
VREFL to GND ......................... -0.5V to VDD +0.5V
Outputs
D0 to GND ............................... -0.5V to VDD +0.5V
VOUT 1– 4 to GND ................... -0.5V to VDD +0.5V
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
VZAP(1)
ILTH(1)(2)
ESD Susceptibility
Latch-Up
2000
100
Max
Units
Test Method
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
POWER SUPPLY
Symbol Parameter
Conditions
IDD1
Supply Current (Read)
IDD2
Supply Current (Write)
VDD
Min
Typ
Max
Units
Normal Operating
—
400
600
µA
Programming, VDD = 5V
—
1600
2500
µA
VDD = 3V
—
1000
1600
µA
2.7
—
5.5
V
Min
Typ
Max
Units
Operating Voltage Range
LOGIC INPUTS
Symbol
Parameter
Conditions
IIH
Input Leakage Current
VIN = VDD
—
—
10
µA
IIL
Input Leakage Current
VIN = 0V
—
—
-10
µA
VIH
High Level Input Voltage
2
—
VDD
V
VIL
Low Level Input Voltage
0
—
0.8
V
Min
Typ
Max
Units
VDD -0.3
—
—
V
LOGIC OUTPUTS
Symbol Parameter
Conditions
VOH
High Level Output Voltage
IOH = -40µA
VIL
Low Level Output Voltage
IOL = 1 mA, VDD = +5V
—
—
0.4
V
IOL = 0.4 mA, VDD = +3V
—
—
0.4
V
Doc. No. 2004, Rev. E
2
CAT522
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
RPOT
Potentiometer Resistance
Conditions
Min
Typ
Max
Units
24
RPOT to RPOT Match
—
+0.5
Pot Resistance Tolerance
kΩ
+1
%
+20
%
Voltage on VREFH pin
2.7
VDD
V
Voltage on VREFL pin
0V
VDD - 2.7
V
Resolution
0.4
%
INL
Integral Linearity Error
0.5
1
LSB
DNL
Differential Linearity Error
0.25
0.5
LSB
ROUT
Buffer Output Resistance
10
Ω
IOUT
Buffer Output Current
3
mA
TCRPOT
TC of Pot Resistance
300
ppm/˚C
CH/CL
Potentiometer Capacitances
8/8
pF
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
150
100
0
50
50
—
—
—
—
—
150
700
500
300
DC
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
—
—
—
—
—
150
150
—
—
5
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
MHz
—
—
3
6
10
10
µs
µs
Digital
tCSMIN
tCSS
tCSH
tDIS
tDIH
tDO1
tDO0
tHZ
tLZ
tBUSY
tPS
tPROG
tCLKH
tCLKL
fC
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
CL=100pF,
see note 1
Analog
tDS
DPP Settling Time to 1 LSB
CLOAD = 10 pF, VDD = +5V
CLOAD = 10 pF, VDD = +3V
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
3
Doc. No. 2004, Rev. E
CAT522
A. C. TIMING DIAGRAM
to
1
2
3
4
5
t CLK H
CLK
t CSS
t CLK L
t CSH
CS
t CSMIN
t DIS
DI
t DIH
t DO0
t LZ
DO
t HZ
t DO1
PROG
t PS
t PROG
RDY/BSY
t BUSY
to
Doc. No. 2004, Rev. E
1
2
3
4
4
5
CAT522
PIN DESCRIPTION
Pin
DPP addressing is as follows:
Name
Function
1
2
3
4
5
6
7
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
8
9
10
11
12
13
14
GND
VREFL1
VREFL2
VOUT2
VOUT1
VREFH2
VREFH1
Power supply positive
Clock input pin
Ready/Busy output
Chip select
Serial data input pin
Serial data output pin
EEPROM Programming Enable
Input
Power supply ground
Minimum DPP 1 output voltage
Minimum DPP 2 output voltage
DPP 2 output
DPP 1 output
Maximum DPP 2 output voltage
Maximum DPP 1 output voltage
DPP OUTPUT
A0
A1
VOUT1
0
1
VOUT2
1
1
DEVICE OPERATION
CHIP SELECT
The CAT522 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost when
power is removed from the chip. Upon power up the
DPPs return to the settings stored in non-volatile memory.
Each DPP can be written to and read from independently
without effecting the output voltage during the read or
write cycle. Each output can also be adjusted without
altering the stored output setting, which is useful for
testing new output settings before storing them in
memory.
Chip Select (CS) enables and disables the CAT522’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance
Tri-State mode.
DIGITAL INTERFACE
CLOCK
The CAT522 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
The CAT522’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
No clock is necessary upon system power-up. The
CAT522’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
5
Doc. No. 2004, Rev. E
CAT522
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
single serial data line and simplifies interfacing multiple
522s to a microprocessor.
WRITING TO MEMORY
Programming the CAT522’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP wiper control register via the DI pin.
Data enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
VREF
VREF, the voltage applied between pins VREFH &VREFL,
sets the configured DPP’s Zero to Full Scale output
range where VREFL = Zero and VREFH = Full Scale. VREF
can span the full power supply range or just a fraction of
it. In typical applications VREFH &VREFL are connected
across the power supply rails. When using less than the
full supply voltage be mindful of the limits placed on
VREFL and VREFL as specified in the References section
of DC Electrical Characteristics.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP wiper
control register will be ready to receive the next set of
address and data bits. The clock must be kept running
throughout the programming cycle. Internal control
circuitry takes care of generating and ramping up the
programming voltage for data transfer to the non-volatile
cells. The CAT522’s non-volatile memory cells will
endure over 1,000,000 write cycles and will retain data
for a minimum of 100 years without being refreshed.
BUSY
READY/BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT522 will ignore any
data appearing at DI and no data will be output on DO.
READING DATA
Data is output serially by the CAT522, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 522s to share a
Each time data is transferred into a DPP control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register. Since this value is the
Figure 1. Writing to Memory
Figure 2. Reading from Memory
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
to
1
2
3
4
5
6
7
8
9
10
11
12
N
N+1 N+2
to
1
2
3
4
5
6
7
8
9
10
11
12
CS
CS
NEW DPP DATA
DI
1
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
DI
D6
D7
DO
1
A0
A1
CURRENT DPP DATA
DO
D0
D1
D2
D3
D4
D5
CURRENT DPP DATA
PROG
PROG
RDY/BSY
RDY/BSY
DPP
OUTPUT
Doc. No. 2004, Rev. E
CURRENT
DPP VALUE
NEW
DPP VALUE
NEW
DPP VALUE
NON-VOLATILE
VOLATILE
NON-VOLATILE
DPP
OUTPUT
D0
D1
D2
D3
D4
D5
CURRENT
DPP VALUE
NON-VOLATILE
6
D6
D7
CAT522
Figure 3. Temporary Change in Output
same as that which had been there previously no change
in the DPP’s output is noticed. Had the value held in the
control register been different from that stored in nonvolatile memory then a change would occur at the read
cycle’s conclusion.
to
1
2
3
4
5
6
7
8
9
10
11
12
N
N+1 N+2
CS
NEW DPP DATA
TEMPORARILY CHANGE OUTPUT
1
DI
The CAT522 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D6
D7
CURRENT DPP DATA
D0
DO
D1
D2
D3
D4
D5
PROG
RDY/BSY
DPP
OUTPUT
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP wiper settings
may be changed as many times as required and can be
made to any of the two DPPs in any order or sequence.
The temporary setting(s) remain in effect long as CS
remains high. When CS returns low all two DPPs will
return to the output values stored in non-volatile memory.
CURRENT
DPP VALUE
NEW
DPP VALUE
CURRENT
DPP VALUE
NON-VOLATILE
VOLATILE
NON-VOLATILE
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
because the CAT522’s internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
APPLICATION CIRCUITS
DPP INPUT
DPP OUTPUT
ANALOG
OUTPUT
+5V
Vi
Ri
CODE (V - V
VDPP = ———
FS ZERO ) + V ZERO
255
RF
+15V
VDD
CONTROL
& DATA
VREFH
+
CAT522
GND
VREFL
VOUT
–
VFS = 0.99 VREF
VZERO = 0.01 V REF
LSB
1111
1111
255 (.98 V
——
REF) + .01 VREF = .990 V REF
255
V OUT= +4.90V
1000
0000
128 (.98 V
——
) + .01 V
= .502 V
REF
REF
REF
255
127
—— (.98 V
) + .01 V
= .498 V
255
REF
REF
REF
1 (.98 V
——
) + .01 V
= .014 V
255
REF
REF
REF
V
0 (.98 V
——
) + .01 V
= .010 V
REF
REF
REF
255
V
OP 07
-15V
VREF = 5V
R I = RF
MSB
0111
1111
VOUT = V DPP ( R i+ RF) -Vi R F
Ri
0000
0001
For R i = RF
VOUT = 2VDPP -Vi
0000
0000
V
V
OUT
OUT
OUT
OUT
= +0.02V
= -0.02V
= -4.86V
= -4.90V
Bipolar DPP Output
+5V
RI
RF
+15V
VDD
CONTROL
& DATA
VREFH
–
+
CAT522
GND
VOUT
OP 07
-15V
VREFL
RF
VOUT = (1 + –––)
V DPP
RI
Amplified DPP Output
7
Doc. No. 2004, Rev. E
CAT522
APPLICATION CIRCUITS (Cont.)
VREF
RC = —————
256 * 1 µA
+5V
VDD
VREF
+5V
VDD
Fine adjust gives ± 1 LSB change in V OFFSET
VREF
when V OFFSET = ———
2
VREFH
+VREF
VREFH
+
(+VREF ) - (VOFFSET )
RC = ———————————
1 µA
127RC
FINE ADJUST
DPP
CAT522
CAT522
RC
COARSE ADJUST
DPP
V OFFSET
(-VREF ) + (VOFFSET+ )
Ro = ———————————
1 µA
RC
COARSE ADJUST
DPP
+V
+
GND
VREFL
+V
Ro
–
GND
127RC
FINE ADJUST
DPP
VOFFSET
-VREF
VREFL
+
–
-V
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
28 - 32V
V+
15K
10 µF
I > 2 mA
1N5231B
VDD
CONTROL
& DATA
VREF = 5.000V
VREFH
CAT522
VDD
5.1V
10K
LT 1029
CONTROL
& DATA
+
CAT522
GND
GND
VREFH
VREFL
–
MPT3055EL
LM 324
VREFL
OUTPUT
4.02 K
1.00K
Digitally Trimmed Voltage Reference
Doc. No. 2004, Rev. E
10 µF
35V
Digitally Controlled Voltage Reference
8
0 - 25V
@ 1A
CAT522
APPLICATION CIRCUITS (Cont.)
+5V
2.2K
VDD
VREFH
4.7 µA
LM385-2.5
ISINK = 2 - 255 mA
+15V
+
DPP
+5V
CONTROL
& DATA
10K
CAT522
1 mA steps
2N7000
–
39 Ω 1W
10K
39 Ω 1W
+
DPP
5 µA steps
2N7000
–
VREFL
GND
5M
5M
3.9K
10K
10K
–
TIP 30
+
-15V
Current Sink with 4 Decades of Resolution
+15V
51K
+
TIP 29
–
10K
10K
+5V
VDD
VREFH
5M
5M
39 Ω 1W
DPP
39 Ω 1W
CONTROL
& DATA
–
CAT522
BS170P
+
5M
5M
1 mA steps
3.9K
DPP
GND
–
VREFL
BS170P
5 µA steps
+
LM385-2.5
-15V
ISOURCE = 2 - 255 mA
Current Source with 4 Decades of Resolution
9
Doc. No. 2004, Rev. E
CAT522
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
522
J
Optional
Company ID
Product
Number
I
Package
P: PDIP
J: SOIC
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
-TE13
Tape & Reel
TE13: 2000/Reel
Temperature Range
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
Notes:
(1) The device used in the above example is a CAT522JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 2004, Rev. E
10
CAT522
REVISION HISTORY
Date
Rev.
Reason
3/16/2004
D
Updated Potentiometer Characteristics
7/12/2004
E
Updated Functional Diagram
Updated Potentiometer Characteristics
Copyrights, Trademarks and Patents
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DPP ™
AE2 ™
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labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
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11
2004
E
7/12/04
Final
Doc. No. 2004, Rev. E
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