Intersil CD22M3493 12 x 8 x 1 bimos-e crosspoint switch Datasheet

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CD22M3493
Data Sheet
January 1997
12 x 8 x 1 BiMOS-E Crosspoint Switch
Features
The Intersil CD22M3493 is an array of 96 analog switches
capable of handling signals from DC to video. Because of
the switch structure, input signals may swing through the
total supply voltage range, VDD to VSS. Each of the 96
switches may be addressed via the ADDRESS input to the
7 to 96 line decoder. The state of the addressed switch is
established by the signal to the DATA input. A low or logic
zero input will open the switch, while a high logic level or a
one will result in closure of the addressed switch when the
STROBE input goes high from its normally low state. Any
number or combination of connections may be active at
one time. Each connection, however, must be made or
broken individually in the manner previously described. All
switches may be reset by taking the RESET input from a
zero state to a one state and then returning it to its normal
low state.
• 96 Analog Switches
TEMP.
RANGE (oC)
2491.4
• Low RON
• Guaranteed RON Matching
• Analog Signal Input Voltage Equal to the Supply Voltage
• Wide Operating Voltage . . . . . . . . . . . . . . . . . . . 4V to 16V
• Parallel Input Addressing
• High Latch Up Current . . . . . . . . . . . . . . . . . . 50mA (Min)
• Very Low Crosstalk
• Pin and Functionally Compatible with the Following Types:
SGS M3493, SGS M093, SSI 78A093A, and Mitel
MT8812
Applications
Ordering Information
PART NUMBER
File Number
• PBX Systems
• Instrumentation
PACKAGE
PKG. NO.
• Analog and Digital Multiplexers
CD22M3493E
-40 to 85
40 Ld PDIP
E40.6
CD22M3493Q
-40 to 85
44 Ld PLCC
N44.65
• Video Switching Networks
Block Diagram
STROBE
DATA
RESET
V DD
1
AX0
AX1
AX2
AX3
AY0
AY1
AY2
1
7 TO 96
DECODER
LATCHES
96
96
V SS
64
12 X 8
SWITCH
ARRAY
X0 - X11
Y0 - Y7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
CD22M3493
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (VDD) (Referenced to VSS . . . . . . . -0.5V to 17V
Supply Voltage Range
For TA = Full Package Temperature Range
VSS = 0V, VDD 4V to 16V
DC Input Diode Current, IIN
For VI < VSS -0.5V or VI > VDD +0.5V . . . . . . . . . . . . . . . . ±20mA
DC Output Diode Current, IOK
For VO < VSS -0.5V or VO > VDD +0.5V . . . . . . . . . . . . . . ±20mA
DC Transmission Gate Current . . . . . . . . . . . . . . . . . . . . . . . ±25mA
Power Dissipation Per Package (Po)
For TA = -40oC to 85oC (PDIP) . . . . . . . . . . . . . . . . . . . . .500mW
For TA = -40oC to 85oC (PLCC) . . . . . . . . . . . . . . . . . . . . .600mW
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
Plastic DIP Package. . . . . . . . . . . . . . . . . . . . . . . . .
55
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range (TSTG). . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC - Lead Tips Only)
Operating Conditions
Temperature Range (TA)
Package Type E and Q. . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
DC Input or Output Voltage . . . . . . . . . . . . . Min = VSS , Max = VDD
Digital Input Voltage . . . . . . . . . . . . . . . . . . . Min = VSS , Max = VDD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = -40oC to 85oC, VSS = 0V, VDD = 14V, Unless Otherwise Specified
PARAMETER
SYMBOL
Supply Current
IDD
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 5V, Logic Inputs = VDD
-
-
2
mA
VDD = 16V, Logic Inputs = VDD
-
-
5
mA
High-Level Input Voltage
VIH
2.4
-
-
V
Low-Level Input Voltage
VIL
-
-
0.8
V
Input Leakage Current, Digital
IIN
-
-
±10
(Note 3)
µA
MIN
TYP
MAX
UNITS
VDD = 5V
-
40
70
Ω
VDD = 14V
-
22
45
Ω
VDD = 5V
-
-
80
Ω
VDD = 14V
-
-
55
Ω
Electrical Specifications
Reset = Low (Note 2)
TA = -40oC to 85oC, VSS = 0V, VDD = 14V, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC CROSSPOINTS
ON Resistance
RON
ON Resistance
RON
TA = 25oC,
VIN = VDD/2
VX - VY = 0.25V
TA = -40oC to 85oC
VIN = VDD/2
VX - VY = 0.25V
Difference in ON Resistance Between Any Two Switches
∆RON
TA = 25oC, VIN = VDD/2
VX - VY = 0.25V, VDD = 14V
-
4
10
Ω
Difference in ON Resistance Between Any Two Switches
∆RON
TA = -40oC to 85oC, VIN = VDD/2
VX - VY = 0.25V, VDD = 14V
-
-
10
Ω
|VX - VY| = 14V
-
-
±10
(Note 3)
µA
MIN
TYP
MAX
UNITS
OFF-State Leakage Current
IL
Electrical Specifications
TA = 25oC, VSS = 0V, VDD = 14V, CL = 50pF, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
DYNAMIC CROSSPOINTS
Switch I/O Capacitance
VIN = 7V, f = 1MHz
-
20
-
pF
Switch Feedthrough Capacitance
VIN = 7V, f = 1MHz
-
0.2
-
pF
-
30
100
ns
Propagation Delay Time (Switch ON)
Signal Input to Output, tPHL or tPLH
65
CD22M3493
Electrical Specifications
TA = 25oC, VSS = 0V, VDD = 14V, CL = 50pF, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Frequency Response Channel ON
f = 20log (VX/VY) = -3dB
CL = 3pF, RL = 75Ω, VIN = 2VP-P
-
50
-
MHz
Total Harmonic, THD
VIN = 2VP-P, f = 1kHz
-
0.01
-
%
Feedthrough Channel OFF
Feedthrough = 20log (VX/VY) = FDT
VIN = 2VP-P, f = 1kHz
-
-95
-
dB
40dB
VIN = 2VP-P, RL = 75Ω
-
10
-
MHz
110dB
VIN = 2VP-P, RL = 1kΩ || 10pF
-
5
-
kHz
Control Input = 3VP-P
Square Wave, tR = tF = 10ns
RIN = 1K, ROUT = 10kΩ || 10pF
-
75
-
mVPEAK
Frequency for Signal Crosstalk, fCT
Attenuation of:
Control Crosstalk DATA-Input, ADDRESS,
or STROBE to Output
Electrical Specifications
TA = 25oC, VSS = 0V, VDD = 14V, RL = 1kΩ || 50pF, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
5
-
pF
DYNAMIC CONTROLS
Digital Input Capacitance
CIN
VIN = 5V, f = 1MHz
Propagation Delay Time
STROBE to Output
Switch Turn-ON
tPSN
-
30
100
ns
Switch Turn-OFF
tPSF
-
40
100
ns
Turn-ON to High Level
tPZH
-
30
100
ns
Turn-ON to Low Level
tPZL
-
30
100
ns
Turn-ON to High Level
tPAN
-
30
100
ns
Turn-OFF to Low Level
tPAF
-
25
100
ns
DATA-IN to STROBE
tDS
20
-
-
ns
ADDRESS to STROBE
tAS
20
-
-
ns
STROBE to DATA-IN
tDH
20
-
-
ns
STROBE to ADDRESS
tAH
10
-
-
ns
STROBE
tSPW
30
-
-
ns
RESET
tRPW
50
-
-
ns
tPHZ
-
100
200
ns
DATA-IN to Output
ADDRESS to Output
Setup Time
Hold Time
Pulse Width
RESET Turn-OFF to Output Delay
NOTES:
2. Reset IIH < 2mA, Reset = VDD = 16V.
3. At 25oC Limit is ±100nA.
66
CD22M3493
Timing Diagram
ADDRESS
50%
50%
tSPW
tAS
STROBE
tAH
50%
tPSN
tPSF
tDH
tDS
DATA
50%
50%
tRPW
50%
RESET
tPAF
tPZL
50%
tPHZ
90%
90%
SWITCH
OUTPUT
10%
tPZH
tPAN
TRUTH TABLE X AXIS
TRUTH TABLE Y AXIS
X ADDRESS
Y ADDRESS
AX3
AX2
AX1
AX0
NOTE
X SWITCH
AY2
AY1
AY0
Y SWITCH
0
0
0
0
X0
0
0
0
Y0
0
0
0
1
X1
0
0
1
Y1
0
0
1
0
X2
0
1
0
Y2
0
0
1
1
X3
0
1
1
Y3
0
1
0
0
X4
1
0
0
Y4
0
1
0
1
X5
1
0
1
Y5
0
1
1
0
4
No Connect
1
1
0
Y6
0
1
1
1
4
No Connect
1
1
1
Y7
1
0
0
0
X6
1
0
0
1
X7
1
0
1
0
X8
1
0
1
1
X9
1
1
0
0
X10
1
1
0
1
X11
1
1
1
0
4
No Connect
1
1
1
1
4
No Connect
NOTE: 4. When X switch addresses are in these states, no change in
status will occur in switches between any X and Y points.
To make a connection (close switch) between any two points, specify an ‘‘X’’ address, a ‘‘Y’’ address, set ‘‘DATA’’ high, and switch
‘‘Strobe’’ from low to high. To break a connection, follow this same procedure with ‘‘DATA’’ low.:
X ADDRESS
Example:
Y ADDRESS
DATA
AX3
AX2
AX1
AX0
AY2
AY1
AY0
To connect switch X3 to switch Y4:
1
0
0
1
1
1
0
0
To connect switch X6 to switch Y7:
1
1
0
0
0
1
1
1
To break connection from X3 to Y4:
0
0
0
1
1
1
0
0
67
CD22M3493
Pin Descriptions
SYMBOL
40 LEAD PDIP
PIN NO.
44 LEAD PLCC
PIN NO.
DESCRIPTION
POWER SUPPLIES
VDD
40
44
Positive Supply
VSS
20
22
Negative Supply
AX0 - AX3
5, 22, 23 and 4
5, 24, 25 and 4
X Address Lines. These pins select one of the 12 rows of switches. See the Truth Table for
the valid addresses.
AY0 - AY2
24, 25 and 2
26, 27 and 2
Y Address Lines. These pins select one of the 8 columns of switches. See the Truth Table
for the valid addresses.
DATA
38
42
DATA Input determines the state of the addressed switch. A high or one will close the
switch. A low or zero will open the switch.
STROBE
18
20
STROBE Input enables the action defined by the DATA and ADDRESS Inputs. A low or
zero results in no action. The ADDRESS Input must be stable before the STROBE Input
goes to the active high level. The DATA Input must be stable on the failing edge of the
STROBE.
RESET
3
3
MASTER RESET. A high or one on this line opens all switches.
X0 - X5
I/O
X6 - X11
33 - 28 8 - 13
37 - 32 9 - 14
Y0 - Y7
I/O
35, 37, 39, 1, 21,
19, 17 and 15
40, 41, 43, 1, 23,
21, 19 and 18
ADDRESS
CONTROL
INPUTS/OUTPUTS
Analog or Digital Inputs/Outputs. These pins are the rows X0 - X11.
Analog or Digital Inputs/Outputs. These pins are the columns Y0 - Y7.
Pinouts
CD22M3493 (PDIP)
TOP VIEW
CD22M3493 (PLCC)
TOP VIEW
3
2
1
44 43 42 41 40
Y0
4
Y1
VDD
5
DATA
Y3
6
Y2
AY2
38 DATA
RESET
3
AX3
39 Y2
RESET
AX0
AY2
2
NC
40 VDD
Y3 1
AX3 4
37 Y1
AX0 5
36 NC
NC
7
39 NC
NC
6
35 Y0
NC
8
38 NC
NC
7
34 NC
X6
9
37 X0
X6 8
33 X0
X7 10
36 X1
X7 9
32 X1
X8 11
35 X2
X8 10
31 X2
X9 12
34 X3
X9 11
30 X3
X10 13
33 X4
X10 12
29 X4
X11 14
32 X5
NC 15
31 NC
NC 16
30 NC
NC 17
29 NC
23 AX2
Y5 19
22 AX1
VSS 20
21 Y4
68
NC
STROBE 18
18 19 20 21 22 23 24 25 26 27 28
AY1
24 AY0
AY0
Y6 17
AX2
25 AY1
AX1
NC 16
Y4
26 NC
VSS
Y7 15
Y5
27 NC
STROBE
NC 14
Y6
28 X5
Y7
X11 13
CD22M3493
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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69
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