ATMEL AT27LV1026-45 1-megabit 2 x 32k x 16 16-bit interleaved low-voltage otp eprom Datasheet

Features
• Fast Interleave Cycle Time - 35 ns
• Continuous Memory Interleaving
– Unlimited Linear Access Data Output
• Dual Voltage Range Operation
•
•
•
•
•
•
•
– Low Voltage Power Supply Range, 3.0V to 3.6V
or Standard 5V ± 10% Supply Range
Low Power CMOS Operation
– 108 mW max. Active at 25 MHz for VCC = 3.6V
– 14.4 mW max. Standby for VCC = 3.6V
JEDEC Standard Surface Mount Packages
– 44-Lead PLCC
– 40-Lead VSOP (10 x 14mm)
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid™ Programming Algorithm - 50 µs/word (typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
1-Megabit
(2 x 32K x 16)
16-Bit Interleaved
Low-Voltage OTP
EPROM
Description
The AT27LV1026 is a high performance 16-bit interleaved low-voltage 1,048,576-bit
one-time programmable read only memory (OTP EPROM) organized as 2 x 32K x 16
bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode
operation.
AT27LV1026
Preliminary
Pin Configurations
Pin Name
Function
A0 - A15
Addresses
O0 - O15
Outputs
CS
Chip Select
RD
Read Strobe
ALE
Address Latch Enable
PGM
Program Strobe
NC
No Connect
Note:
Both GND pins must be
connected.
PLCC Top View
VSOP Top View
Type 1
O13 O15 VPP VCC ALE A14
O14 CS GND PGM A15
6
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
7
8
9
10
11
12
13
14
15
16
17
4
42 40
41 39
38
37
36
35
34
33
32
31
30
19 21 23 25 27 29
18 20 22 24 26 28
5
A9
44
2
3
1
43
O2 O0 GND A1 A3
O3 O1 RD A0 A2 A4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
A11
A13
A15
PGM
1
A10
A12
4
A14
6
ALE
8
10
3
38
36
7
34
9
32
11
30
13
28
15
26
16
O11 O10
O9 O8
18 17
20 19
14
40
5
VCC
VPP
CS
O15
O14
O13 O12
12
2
39
A8
37
A6
35
A4
33
A2
31
A0
29
O0
27
O2
25
O4
24 23
22 21
O6
GND
A7
A5
A3
A1
RD
O1
O3
O5
GND O7
Rev. 0956D–02/98
1
This device is internally architected as two 32K x 16 memory banks, odd and even. To begin a non-linear access
NLA cycle, (which typically equals a minimum of two linear
access LA cycles), ALE is asserted high and CS is
asserted low. The two internal 15-bit counters store the
address for the odd and even banks and increment alternately during each subsequent linear access LA cycle. The
LA cycle will be terminated when CS is asserted high putting the device in standby mode, or another NLA cycle
starts. The LA cycle can be resumed when CS is asserted
low and ALE stays low. The AT27LV1026 will continuously
output data within each LA cycle which is determined by
the read RD signal. Continuous interleave read operation is
possible as there is no physical limit to the linear access LA
output. When the last address in the array is reached the
counters will wrap around to the first address location and
continue.
For a NLA cycle where A0 = 0 (ALE asserted high, CS
asserted low), both even and odd counters will be loaded
with new address (A1 - A15). Outputs (O0 - O15) from the
even bank will be valid in tACCNLA within the NLA cycle, the
outputs from the odd bank will become valid in tACCLA within
the following LA cycle while the even counter increments
by one to ready the data out for the next LA cycle. The outputs will have even or odd data alternating and the
counters increment for the consecutive LA cycles until CS
is asserted high putting the device in standby mode, or a
new NLA cycle begins.
For a NLA cycle where A0 = 1 (ALE asserted high, CS
asserted low), the odd counter will be loaded with the new
address (A1 - A15) while the even counter gets loaded with
the new address+1. Outputs (O0 - O15) from odd bank of
memory will be valid in tACCNLA within the NLA cycle, the
data output from the even bank of memory will become
valid in tACCLA within the following LA cycle while the odd
counter increments by one to ready the data out for the
next LA cycle. The outputs will have data from the odd or
even memory bank alternately and the counters increment
for the following consecutive LA cycles until CS is asserted
high putting the device in standby mode, or a new NLA
cycle begins. When coming out of standby mode, the
device can either enter into a new NLA cycle or resume
where the previous LA operation left off and was terminated by standby mode.
System Considerations
Switching under active conditions may produce transient
voltage excursions. Unless accommodated by the system
design, these transients may exceed data sheet limits,
resulting in device non-conformance. At a minimum, a 0.1
µF high frequency, low inherent inductance, ceramic
capacitor should be utilized for each device. This capacitor
should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected
between the V CC and Ground terminals. This capacitor
should be positioned as close as possible to the point
where the power supply is connected to the array.
Operating Table
If A0 = 0 at beginning of NLA cycle:
Consecutive
Cycle
If A0 = 1 at beginning of NLA cycle:
Counter
Outputs
Consecutive
Cycle
Address
from Even Bank
NLA
+1
-
from Odd Bank
LA
-
+1
LA
+1
LA
-
Even
Odd
Address
LA
NLA
Counter
Even
Odd
Address+1
Address
from Odd Bank
LA
-
+1
from Even Bank
from Even Bank
LA
+1
-
from Odd Bank
-
from Odd Bank
LA
-
+1
from Even Bank
+1
from Even Bank
LA
+1
-
from Odd Bank
HiZ
Standby
Standby
Outputs
HiZ
LA
+1
-
from Odd Band
LA
-
+1
from Even Bank
LA
-
+1
from Even Bank
LA
+1
-
from Odd Band
and so on.
2
and so on.
AT27LV1026
AT27LV1026
Block Diagram
ALE
RD
A0
CS
PGM
Logic
CLK_ODD
Address
Input
A1-A1 5
CLK_EVEN
Even Counter
Odd Counter
15
15
32K x 16
32K x 16
Memory
Array
Memory
Array
16
VCC
GND
VPP
16
A0
MUX
16
CS
Data Outputs
O0-O1 5
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which
may overshoot to +7.0V for pulses of less than 20
ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground .......................................-2.0V to +14.0V(1)
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
1.
3
Operating Modes
Mode/Pin
ALE
Non-Linear Access Cycle
(2)
CS
VIL
Linear Access Cycle(2)
VIL
VIL
Standby(2)
X
VIH
Rapid Program
(3)
VIH
(3)
VIH
RD
VIL
X
VIL
PGM
A0
A1 - A15
VPP
VCC
Outputs
DOUT
VIH
VIL/VIH
Ai
X
VCC(2)
VIH
X(1)
X
X
VCC(2)
DOUT
VIH
X
X
X
VCC(2)
High Z
VPP
VCC(3)
DIN
DOUT
VIL
VIL/VIH
Ai
VIH
VIL
VIL
VIH
VIL/VIH
Ai
VPP
VCC(3)
PGM Inhibit(3)
X
VIH
X
VIH
X
X
VPP
VCC(3)
High Z
Product Identification(3)(5)
X
VIL
X
VIH
VIL/VIH
A9 = VH (4)
A1 - A15 = VIL
VCC
VCC(3)
Identification Code
PGM Verify
Notes:
1. X can be VIL or VIH.
2. Non-Linear and Linear Access Cycles, and standby modes require, 3.0V ≤ VCC ≤ 3.6V, or 4.5V ≤ VCC ≤ 5.5V.
3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V.
4. VH = 12.0 ± 0.5V.
5. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
DC and AC Operating Conditions for Read Operation
AT27LV1026
Operating
Temperature (Case)
Com.
Ind.
VCC Power Supply
4
AT27LV1026
-35
-45
-55
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
3.0V - 3.6V
3.0V - 3.6V
3.0V - 3.6V
5V ± 10%
5V ± 10%
5V ± 10%
AT27LV1026
DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
VCC = 3.0V to 3.6V
ILI
ILO
IPP1
(2)
Input Load Current
VIN = 0V to VCC
±1
µA
Output Leakage Current
VOUT = 0V to VCC
±5
µA
VPP
(1)
Read/Standby Current
VPP = VCC
10
µA
(1)
Standby Current
CS = VIH
4
mA
f = 25 MHz, IOUT = 0 mA, CS = VIL
30
mA
ISB
VCC
ICC
VCC Active Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.0 mA
0.4
V
VOH
Output High Voltage
IOH = -2.0 mA
2.4
V
VCC = 4.5V to 5.5V
ILI
Input Load Current
VIN = 0V to VCC
±1
µA
ILO
Output Leakage Current
VOUT = 0V to VCC
±5
µA
IPP1(2)
VPP(1) Read/Standby Current
VPP = VCC
10
µA
ISB
VCC(1) Standby Current
CS = VIH
6
mA
ICC
VCC Active Current
f = 25 MHz, IOUT = 0 mA, CS = VIL
50
mA
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = -400 µA
Notes:
2.4
V
1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
5
AC Characteristics for Read Operation (VCC = 3.0V to 3.6V and 4.5V to 5.5V)
AT27LV1026
Symbol
Parameter
tNLACYC
Non-Linear Access Cycle
tLACYC
Linear Access Cycle
tALE
ALE High Width
7.5
ns
tAS
Address/CS Setup Time
2.5
ns
tAH
Address Hold Time
20
ns
tARD
ALE Low to RD Low
5
ns
tRDL
RD Low Width
ALE = CS = VIL
13
ns
tRDH
RD High Width
ALE = CS = VIL
12
ns
tACCNLA
Address to Output Delay in Non-Linear Address Cycle from ALE Low
tACCLA
Output Valid Delay in Linear Address Cycle from RD High
tDF
(2)(3)
Condition
ALE = CS = VIL
Min
Typ
70
80
ns
35
40
ns
ALE = CS = VIL
CS High to Output Float
Max
Units
52
ns
17
ns
14
ns
tOH
Output Hold from CS High
tCS
Output Valid Delay from CS Low in Linear Address Cycle
tRC
RD High to CS Falling Edge Delay
10
ns
tCR
CS Falling Edge to RD Low Delay
12
ns
tCA
CS Rising Edge to ALE Low Delay
2.5
ns
Notes:
0
ns
17
ns
2, 3. - See AC Waveforms for Read Operation.
AC Waveforms for Read Operation(1)
t ALE
t
tCA
NLACYC
ALE
t AS
CS
t RC
t AH
A 0-15
VALID
t ARD
RD
t ACCNLA
t LACYC
t RDL
t DF
t RDH
tACCLA
t CR
t OH
t CS
O
0 -15
NLA
Notes:
6
LA
LA
LA
LA
1.
Refer to Test Waveforms and Measurement Levels diagram on next page.
2.
This parameter is only sampled and is not 100% tested.
3.
Output float is defined as the point when data is no longer driven.
4.
When reading a 27LV1026, a 0.1 µF capacitor is required across VCC and ground to suppress spurious voltage transients.
AT27LV1026
AT27LV1026
Input Test Waveforms and
Measurement Levels
Output Test Load
3.0V
1.5V
0.0V
tR, tF < 2.5 ns (10% to 90%)
Note:
CL = 100 pF including jig capacitance.
Pin Capacitance (f = 1 MHz T = 25°C) (1)
Typ
Max
Units
CIN
4
10
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
Conditions
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Programming Waveforms (1)
READ
(VERIFY)
PROGRAM
VIH
ADDRESS
ADDRESS STABLE
VIL
tAS
DATA
DATA
VIL
V
PP
DATA OUT
VALID
IN
tDS
V
CC
tAH
tCS
VIH
tDH
6.5V
5.0V
tDFP
tVCS
13.0V
5.0V
tVPS
tPRT
VIH
RD
VIL
VIH
ALE
PGM
VIL
VIH
VIL
tPW
CS
Notes:
tCSS
VIH
VIL
1.
The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2.
tCS and tDFP are characteristics of the device but must accompanied by the programmer.
3.
When programming the AT27LV1026 a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
7
DC Programming Characteristics
TA = 25 ± 5°°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
8
Symbol
Parameter
Test Conditions
ILI
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
VIH
Input High Level
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
ICC2
VCC Supply Current (Program and Verify)
IPP2
VPP Supply Current
VID
A9 Product Identification Voltage
AT27LV1026
Min
Max
Units
±10
µA
-0.6
0.8
V
2.0
VCC + 0.1
V
0.4
V
2.4
PGM = VIL
11.5
V
50
mA
30
mA
12.5
V
AT27LV1026
AC Programming Characteristics
TA = 25 ± 5°°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Test Conditions (1)
Min
Max
Units
Symbol
Parameter
tAS
Address Setup Time
2
µs
tCSS
CS Setup Time
2
µs
tDS
Data Setup Time
2
µs
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
2
µs
tDFP
CS High to Output
Float Delay (2)
tVPS
VPP Setup Time
tVCS
VCC Setup Time
tPW
PGM Program
Pulse Width (3)
tCS
Data Valid from CS
tPRT
Notes:
Input Rise and Fall Times
(10% to 90%) 20 ns
Input Pulse Levels
0.45V to 2.4V
0
130
ns
Input Timing Reference Level
0.8V to 2.0V
2
µs
2
µs
Output Timing Reference Level
0.8V to 2.0V
45
55
µs
150
ns
VPP Pulse Rise Time
50
During Programming
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
ns
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven
— see timing diagram.
3. Program Pulse width tolerance is 50 µsec ± 5%.
Atmel's 27LV1026 Integrated Product Identification Code
Pins
A0
015-08
O7
O6
O5
O4
O3
O2
O1
O0
Hex
Data
Manufacturer
0
0
0
0
0
1
1
1
1
0
001E
Device Type
1
0
0
1
1
0
0
0
0
1
0061
Codes
9
Rapid Programming Algorithm
A 50 µs PGM pulse width is used to program. The address
is set to the first location. VCC is raised to 6.5V and VPP is
raised to 13.0V. Each address is first programmed with one
50 µs PGM pulse without verification. Then a verification /
reprogramming loop is executed for each address. In the
event a word fails to pass verification, up to 10 successive
50 µs pulses are applied with a verification after each
10
AT27LV1026
pulse. If the word fails to verify after 10 pulses have been
applied, the part is considered failed. After the word verifies
properly, the next address is selected until all have been
checked. VPP is then lowered to 5.0V and VCC to 5.0V. All
words are read again and compared with the original data
to determine if the device passes or fails.
AT27LV1026
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
35
30
0.1
30
45
30
30
55
30
30
0.1
0.1
0.1
0.1
0.1
Ordering Code
Package
Operation Range
AT27LV1026-35JC
44J
Commercial
AT27LV1026-35VC
40V
(0°C to 70°C)
AT27LV1026-35JI
44J
Industrial
AT27LV1026-35VI
40V
(-40°C to 85°C)
AT27LV1026-45JC
44J
Commercial
AT27LV1026-45VC
40V
(0°C to 70°C)
AT27LV1026-45JI
44J
Industrial
AT27LV1026-45VI
40V
(-40°C to 85°C)
AT27LV1026-55JC
44J
Commercial
AT27LV1026-55VC
40V
(0°C to 70°C)
AT27LV1026-55JI
44J
Industrial
AT27LV1026-55VI
40V
(-40°C to 85°C)
Package Type
44J
44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
40V
40-Lead, Plastic Thin Small Outline Package (VSOP) 10 x 14 mm
11
Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
40V, 40-Lead, Plastic Thin Small Outline Package
(VSOP) Dimension in Millimeters and (Inches)
JEDEC STANDARD MS-018 AC
JEDEC OUTLINE MO-142 CA
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
*Controlling dimension: millimeters
12
AT27LV1026
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