CS5156 CPU 5−Bit Nonsynchronous Buck Controller The CS5156 is a 5−bit nonsynchronous N−Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high−density, high−speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5156 is designed to operate over a 4.25−16 V range (VCC) using 12 V to power the IC and 5.0 V as the main supply for conversion. The CS5156 is specifically designed to power Pentium® II processors and other high performance core logic. It includes the following features: on board, 5−bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5156 is backwards compatible with the 4−bit CS5151, allowing the mother board designer the capability of using either the CS5151 or the CS5156 with no change in layout. The CS5156 is available in 16 pin surface mount and DIP packages. Features N−Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 5−Bit DAC Backward Compatible with 4−Bit CS5150/CS5151 30 ns Gate Rise/Fall Times 1.0% DAC Accuracy 5.0 V & 12 V Operation Remote Sense Programmable Soft Start Lossless Short Circuit Protection VCC Monitor Adaptive Voltage Positioning V2™ Control Topology Current Sharing Overvoltage Protection http://onsemi.com MARKING DIAGRAMS 16 16 1 CS5156 AWLYWW SOIC−16 D SUFFIX CASE 751B 1 16 • • • • • • • • • • • • • • • • 16 CS5156 AWLYYWW 1 DIP−16 N SUFFIX CASE 648 A WL, L YY, Y WW, W 1 = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS VID0 1 VFB VID1 COMP VID2 VID3 SS LGND VCC1 NC VID4 PGND COFF VFFB VGATE VCC2 ORDERING INFORMATION Device © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 11 1 Package Shipping CS5156GD16 SO−16 48 Units/Rail CS5156GDR16 SO−16 2500 Tape & Reel CS5156GN16 DIP−16 25 Units/Rail Publication Order Number: CS5156/D CS5156 5.0 V 12 V 0.1 μF VCC1 VID0 VID0 VID1 VID1 VID2 VID2 VID3 VID3 VID4 VID4 COFF 330 pF VCC2 VGATE 2.0 μH 1.3 V to 3.5 V @ 13 A 2 MBR1535CT 1,3 CS5156 PGND SS 0.1 μF 1200 μF/16 V × 3 AIEI IRL3103 COMP VFB 3.3 k 0.33 μF LGND VFFB 1200 μF/16 V × 5 AIEI 100 pF Figure 1. Application Diagram, Switching Power Supply for Core Logic − Pentium) II Processor ABSOLUTE MAXIMUM RATINGS* Rating Value Unit 0 to 150 °C 260 peak 230 peak °C −65 to +150 °C 2.0 kV Operating Junction Temperature, TJ Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow: (SMD styles only) (Note 2) Storage Temperature Range, TS ESD Susceptibility (Human Body Model) 1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. ABSOLUTE MAXIMUM RATINGS Pin Name Max Operating Voltage Max Current VCC1 16 V/−0.3 V 25 mA DC/1.5 A peak VCC2 16 V/−0.3 V 20 mA DC/1.5 A peak SS 6.0 V/−0.3 V −100 μA COMP 6.0 V/−0.3 V 200 μA VFB 6.0 V/−0.3 V −0.2 μA COFF 6.0 V/−0.3 V −0.2 μA VFFB 6.0 V/−0.3 V −0.2 μA VID0 − VID4 6.0 V/−0.3 V −50 μA VGATE 16 V/−0.3 V 100 mA DC/1.5 A peak LGND 0V 25 mA PGND 0V 100 mA DC/1.5 A peak http://onsemi.com 2 CS5156 ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +85°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 14 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 μF, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Error Amplifier VFB Bias Current VFB = 0 V − 0.3 1.0 μA Open Loop Gain 1.25 V < VCOMP < 4.0 V; Note 3 50 60 − dB Unity Gain Bandwidth Note 3 500 3000 − kHz COMP SINK Current VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V 0.4 2.5 8.0 mA COMP SOURCE Current VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V 30 50 70 μA COMP CLAMP Current VCOMP = 0 V; VFB = 2.7 V 0.4 1.0 1.6 mA COMP High Voltage VFB = 2.7 V; VSS = 5.0 V 4.0 4.3 5.0 V COMP Low Voltage VFB = 3.0 V − 160 600 mV PSRR 8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 3 60 85 − dB VCC1 Monitor Start Threshold Output switching 3.75 3.90 4.05 V Stop Threshold Output not switching 3.70 3.85 4.00 V Hysteresis Start−Stop − 50 − mV Out SOURCE Sat at 100 mA Measure VCC2 − VGATE − 1.2 2.0 V Out SINK Sat at 100 mA Measure VGATE − VPGND − 1.0 1.5 V Out Rise Time 1.0 V < VGATE < 9.0 V; VCC1 = VCC2 = 12 V − 30 50 ns Out Fall Time 9.0 V > VGATE > 1.0 V; VCC1 = VCC2 = 12 V − 30 50 ns Shoot−Through Current Note 3 − − 50 mA VGATE Resistance Resistor to LGND. 20 50 100 kΩ VGATE Schottky LGND to VGATE @ 10 mA − 600 800 mV VGATE Soft Start (SS) Charge Time − 1.6 3.3 5.0 ms Pulse Period − 25 100 200 ms Duty Cycle (Charge Time /Pulse Period) × 100 1.0 3.3 6.0 % COMP Clamp Voltage VFB = 0 V; VSS = 0 0.50 0.95 1.10 V VFFB SS Fault Disable VGATE = Low 0.9 1.0 1.1 V − 2.5 3.0 V High Threshold − PWM Comparator Transient Response VFFB = 0 to 5.0 V to VGATE = 9.0 V to 1.0 V; VCC1 = VCC2 = 12 V − 100 125 ns VFFB Bias Current VFFB = 0 V − 0.3 − μA 3. Guaranteed by design, not 100% tested in production. http://onsemi.com 3 CS5156 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +85°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 14 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 μF, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit DAC Input Threshold VID0, VID1, VID2, VID3, VID4 1.00 1.25 2.40 V Input Pull Up Resistance VID0, VID1, VID2, VID3, VID4 25 50 100 kΩ 4.85 5.00 5.15 V − − 1.0 % Pull Up Voltage − Accuracy Measure VFB = COMP, 25°C ≤ TJ ≤ 85°C VID4 VID3 VID2 VID1 VID0 0 1 1 1 1 − 1.3266 1.3400 1.3534 V 0 1 1 1 0 − 1.3761 1.3900 1.4039 V 0 1 1 0 1 − 1.4256 1.4400 1.4544 V 0 1 1 0 0 − 1.4751 1.4900 1.5049 V 0 1 0 1 1 − 1.5246 1.5400 1.5554 V 0 1 0 1 0 − 1.5741 1.5900 1.6059 V 0 1 0 0 1 − 1.6236 1.6400 1.6564 V 0 1 0 0 0 − 1.6731 1.6900 1.7069 V 0 0 1 1 1 − 1.7226 1.7400 1.7574 V 0 0 1 1 0 − 1.7721 1.7900 1.8079 V 0 0 1 0 1 − 1.8216 1.8400 1.8584 V 0 0 1 0 0 − 1.8711 1.8900 1.9089 V 0 0 0 1 1 − 1.9206 1.9400 1.9594 V 0 0 0 1 0 − 1.9701 1.9900 2.0099 V 0 0 0 0 1 − 2.0196 2.0400 2.0604 V 0 0 0 0 0 − 2.0691 2.0900 2.1109 V 1 1 1 1 1 − 1.2315 1.2440 1.2564 V 1 1 1 1 0 − 2.1186 2.1400 2.1614 V 1 1 1 0 1 − 2.2176 2.2400 2.2624 V 1 1 1 0 0 − 2.3166 2.3400 2.3634 V 1 1 0 1 1 − 2.4156 2.4400 2.4644 V 1 1 0 1 0 − 2.5146 2.5400 2.5654 V 1 1 0 0 1 − 2.6136 2.6400 2.6664 V 1 1 0 0 0 − 2.7126 2.7400 2.7674 V 1 0 1 1 1 − 2.8116 2.8400 2.8684 V 1 0 1 1 0 − 2.9106 2.9400 2.9694 V 1 0 1 0 1 − 3.0096 3.0400 3.0704 V 1 0 1 0 0 − 3.1086 3.1400 3.1714 V 1 0 0 1 1 − 3.2076 3.2400 3.2724 V 1 0 0 1 0 − 3.3066 3.3400 3.3734 V 1 0 0 0 1 − 3.4056 3.4400 3.4744 V 1 0 0 0 0 − 3.5046 3.5400 3.5754 V http://onsemi.com 4 CS5156 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +85°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 14 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 μF, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Supply Current ICC1 No Switching − 8.5 13.5 mA ICC2 No Switching − 1.6 3.0 mA Operating ICC1 VFB = COMP = VFFB − 8.0 13 mA Operating ICC2 VFB = COMP = VFFB − 2.0 5.0 mA COFF Normal Charge Time VFFB = 1.5 V; VSS = 5.0 V 1.0 1.6 2.2 μs Extension Charge Time VSS = VFFB = 0 5.0 8.0 11.0 μs Discharge Current COFF to 5.0 V; VFB > 1.0 V 5.0 − − mA Time Out Time VFB = VCOMP; VFFB = 2.0 V; Record VGATE Pulse High Duration 10 30 50 μs Fault Mode Duty Cycle VFFB = 0V 35 50 65 % Time Out Timer PACKAGE PIN DESCRIPTION PACKAGE PIN # SO−16, DIP−16 PIN SYMBOL FUNCTION 1, 2, 3, 4, 6 VID0−VID4 Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic ones if left open. VID4 selects the DAC range. When VID4 is High (logic one), the DAC range is 2.14 V to 3.54 V with 100 mV increments. When VID4 is Low (logic zero), the DAC range is 1.34 V to 2.09 V with 50 mV increments. VID0 − VID4 select the desired DAC output voltage. Leaving all 5 DAC input pins open results in a DAC output voltage of 1.244 V, allowing for adjustable output voltage, using a traditional resistor divider. 5 SS Soft Start Pin. A capacitor from this pin to LGND in conjunction with internal 60 μA current source provides Soft Start function for the controller. This pin disables fault detect function during Soft Start. When a fault is detected, the Soft Start capacitor is slowly discharged by internal 2.0 μA current source setting the time out before trying to restart the IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is shorted. 7 COFF A capacitor from this pin to ground sets the time duration for the on board one shot, which is used for the constant off time architecture. 8 VFFB Fast feedback connection to the PWM comparator. This pin is connected to the regulator output. The inner feedback loop terminates on time. 9 VCC2 Boosted power for the gate driver. 10 VGATE MOSFET driver pin capable of 1.5 A peak switching current. 11 PGND High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor ground and the anode of the Schottky diode should be tied to this pin. 12 NC 13 VCC1 Input power for the IC. 14 LGND Signal ground for the IC. All control circuits are referenced to this pin. 15 COMP Error amplifier compensation pin. A capacitor to ground should be provided externally to compensate the amplifier. 16 VFB Error amplifier DC feedback input. This is the master voltage feedback which sets the output voltage. This pin can be connected directly to the output or a remote sense trace. No connection. http://onsemi.com 5 CS5156 VCC1 VCC2 VCC1 Monitor − Comparator 5.0 V + − 3.90 V 3.85V + 60 μA 0.7 V SS + 2.0 μA VID0 VID1 VID2 5 BIT DAC Error Amplifier Q S Q FAULT PGND FAULT Latch SS High Comparator 2.5 V + − PWM Comparator VID4 − Maximum On−Time Timeout + Slow Feedback Normal Off−Time Timeout Extended Off−Time Timeout COMP VFFB R FAULT − VID3 VFB VGATE SS Low Comparator Fast Feedback − + LGND 1.0 V R Q S Q PMW Latch GATE = ON GATE = OFF COFF One Shot R Off−Time Timeout COFF Q S VFFB Low Comparator Time−Out Timer (30 μs) PWM COMP Edge Triggered Figure 2. Block Diagram APPLICATIONS INFORMATION THEORY OF OPERATION + V2 Control Method PWM Comparator C The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. − Ramp Signal VGATE VFFB Error Amplifier COMP Error Signal Output Voltage Feedback VFB − E + Figure 3. V2 Control Diagram http://onsemi.com 6 Reference Voltage CS5156 The V2 control method is illustrated in Figure 3. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub−harmonic oscillations at high duty cycles is avoided. Switch on time is limited by an internal 30 μs timer, minimizing stress to the power components. Programmable Output The CS5156 is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.14 V to 3.54 V in 100 mV steps, the second is 1.34 V to 2.09 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5156 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. The CS5156 is specifically designed to be backwards compatible with the CS5151, which uses a four bit DAC code. Start Up Until the voltage on the VCC1 supply pin exceeds the 3.9 V monitor threshold, the Soft Start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GATE output is activated, and the Soft Start capacitor begins charging. The GATE output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE pin drives low for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. Then, the GATE pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by Constant Off Time To maximize transient response, the CS5156 uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2 control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time. http://onsemi.com 7 CS5156 the Soft Start COMP clamp and the voltage on the Soft Start pin (see Figures 4 and 5). M 10.0 μs Trace 1− Regulator Output Voltage (5.0 V/div.) M 250 μs Trace 2− Inductor Switching Node (5.0 V/div.) Trace 1− Regulator Output Voltage (1.0 V/div.) Trace 2− Inductor Switching Node (2.0 V/div.) Trace 3− 12 V Input (VCC1 and VCC2) (5.0 V/div.) Trace 4− 5.0 V Input (1.0 V/div.) Figure 6. CS5156 Demonstration Board Enable Startup Waveforms Figure 4. CS5156 Demonstration Board Startup in Response to Increasing 12 V and 5.0 V Input Voltages. Extended Off Time is Followed by Normal Off Time Operation when Output Voltage Achieves Regulation to the Error Amplifier Output. Normal Operation During normal operation, switch off time is constant and set by the COFF capacitor. Switch on time is adjusted by the V2 control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working into the ESR of the output capacitors (see Figures 7 and 8). M 2.50 ms Trace 1− Regulator Output Voltage (1.0 V/div.) Trace 3− COMP PIn (error amplifier output) (1.0 V/div.) Trace 4− Soft Start Pin (2.0 V/div.) Figure 5. CS5156 Demonstration Board Startup Waveforms M 1.00 μs If the input voltage rises quickly, or the regulator output is enabled externally, output voltage will increase to the level set by the error amplifier output more rapidly, usually within a couple of cycles (see Figure 6). Trace 1− Regulator Output Voltage (10 mV/div.) Trace 2− Inductor Switching Node (5.0 V/div.) Figure 7. Peak−to−Peak Ripple on VOUT = 2.8 V, IOUT = 0.5 A (Light Load) http://onsemi.com 8 CS5156 level, the output capacitor is pre−positioned −40 mV (see Figures 9, 10, and 11). For best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. If the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor. M 1.00 μs Trace 1− Regulator Output Voltage (10 mV/div.) Trace 2− Inductor Switching Node (5.0 V/div.) Figure 8. Peak−to−Peak Ripple on VOUT = 2.8 V, IOUT = 13 A (Heavy Load) Transient Response The CS5156 V2 control loop’s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called “adaptive voltage positioning”. This technique pre−positions the output capacitor’s voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1.0% allows the error amplifier’s reference voltage to be targeted +40 mV high without compromising DC accuracy. A “droop resistor”, implemented through a PC board trace, connects the error amplifier’s feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the error amplifier’s, including the +40 mV offset. When the full load current is delivered, an 80 mV drop is developed across this resistor. This results in output voltage being offset −40 mV low. The result of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre−positioned +40 mV. Conversely, when load current suddenly decreases from its maximum Trace 1− Regulator Output Voltage (1.0 V/div.) Trace 2− Regulator Output Voltage (20 V/div.) Figure 9. CS5156 Demonstration Board Response to a 0.5 to 13 A Load Pulse (Output Set for 2.8 V) Trace 1− Regulator Output Voltage (1.0 V/div.) Trace 2− Inductor Switching Node (5.0 V/div.) Trace 3− Output Current (0.5 to 13 Amps) (20 V/div.) Figure 10. CS5156 Demonstration Board Response to 13 A Load Turn On (Output Set for 2.8 V). Upon Completing a Normal Off Time, The V2 Control Loop Immediately Connects the Inductor to the Input Voltage, Providing 100% Duty Cycle. Regulation is Achieved in Less Than 20 ms http://onsemi.com 9 CS5156 traces than occurs with constant current limit protection (see Figures 12 and 13). If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume. Trace 1− Regulator Output Voltage (1.0 V/div.) Trace 2− Inductor Switching Node (5.0 V/div.) Trace 3− Output Current (13 to 0,5 Amps) (20 mV/div.) Figure 11. CS5156 Demonstration Board Response to 13 A Load Turn Off (Output Set for 2.8 V). V2 Control Topology Immediately Connects Inductor to Ground, Providing 0% Duty Cycle. Regulation is Achieved in Less Than 10 ms M 25.0 ms Trace 4− 5.0 V Supply Voltage (2.0 V/div.) Trace 3− Soft Start Timing Capacitor (1.0 V/div.) Trace 2− Inductor Switching Node (2.0 V/div.) Figure 12. CS5156 Demonstration Board Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While the Soft Start Capacitor Charges, and Cease During Discharge PROTECTION AND MONITORING FEATURES VCC1 Monitor To maintain predictable startup and shutdown characteristics an internal VCC1 monitor circuit is used to prevent the part from operating below 3.75 V minimum startup. The VCC1 monitor comparator provides hysteresis and guarantees a 3.70 V minimum shutdown threshold. Short Circuit Protection A lossless hiccup mode short circuit protection feature is provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs (VFFB < 1.0 V), the VFFB low comparator sets the FAULT latch. This causes the MOSFET to shut off, disconnecting the regulator from it’s input voltage. The Soft Start capacitor is then slowly discharged by a 2.0 μA current source until it reaches it’s lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 μA charge current. If the short circuit condition persists, the regulator output will not achieve the 1.0 V low VFFB comparator threshold before the Soft Start capacitor is charged to it’s upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 μA/60 μA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board M 50.0 μs Trace 4− 5.0 V from PC Power Supply (2.0 V/div.) Trace 2− Inductor Switching Node (2.0 V/div.) Figure 13. Startup with Regulator Output Shorted Overvoltage Protection Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. External Output Enable Circuit On/off control of the regulator can be implemented through the addition of two additional discrete components http://onsemi.com 10 CS5156 (see Figure 14). This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition. 5.0 V MMUN2111T1 (SOT−23) 5 SS M 2.50 ms CS5156 8 V FFB Trace 3 − 12 V Input (VCC1) and (VCC2) (10 V/div.) Trace 4− 5.0 V Input (2.0 V/div.) IN4148 Trace 1− Regulator Output Voltage (1.0 V/div.) Shutdown Input Trace 2− Power Good Signal (2.0 V/div.) Figure 16. CS5156 Demonstration Board During Power Up. Power Good Signal is Activated when Output Voltage Reaches 1.70 V. Figure 14. Implementing Shutdown with the CS5156 Selecting External Components External Power Good Circuit The CS5156 can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection. An optional Power Good signal can be generated through the use of four additional external components (see Figure 15). The threshold voltage of the Power Good signal can be adjusted per the following equation: VPower Good + (R1 ) R2) 0.65 V R2 NFET Power Transistors Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and use logic level MOSFETs. A charge pump may be easily implemented to support 5.0 V only systems. Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. The gate driver output is specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of its bias supply when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided; This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good. 5.0 V R3 10 k VOUT CS5156 R1 10 k PN3904 Power Good PN3904 R2 6.2 k Figure 15. Implementing Power Good with the CS5156 VGATE(H) + 12 V * 5.0 V + 7.0 V (see Figure 17.) http://onsemi.com 11 CS5156 regulator is unloaded, and −40 mV at full load. This results in increased margin before encountering minimum and maximum transient voltage limits, allowing use of less capacitance on the regulator output (see Figure 9). To implement adaptive voltage positioning, a “droop” resistor must be connected between the output inductor and output capacitors and load. This is normally implemented by a PC board trace of the following value: RDROOP + 80 mV IMAX Adaptive voltage positioning can be disabled for improved DC regulation by connecting the VFB pin directly to the load using a separate, non−load current carrying circuit trace. M 1.00 μs Channel 3 = VGATE M1 = VGATE − 5.0 VIN Channel 2− Inductor Switching Node Input and Output Capacitors These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. Figure 17. CS5156 Gate Drive Waveforms Depicting Rail to Rail Swing The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFETs and the Schottky diode may be estimated as follows; Switching MOSFET: Power + ILOAD2 RDSON Output Inductor The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. duty cycle Schottky diode: Power + VFORWARD ILOAD (1 * duty cycle) Duty Cycle = THERMAL MANAGEMENT VOUT ) VFORWARD VIN ) VFORWARD * (ILOAD RDSON OF SYNCH FET) Thermal Considerations for Power MOSFETs and Diodes Off Time Capacitor (COFF) In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150°C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: The COFF timing capacitor sets the regulator off time: TOFF + COFF 4848.5 When the VFFB pin is less than 1.0 V, the current charging the COFF capacitor is reduced. The extended off time can be calculated as follows: TOFF + COFF Thermal Impedance + 24, 242.5 Off time will be determined by either the TOFF time, or the time out timer, whichever is longer. The preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the COFF timing capacitor: COFF + Perioid A heatsink may be added to TO−220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. (1 * duty cycle) 4848.5 EMI Management As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter where: Period + TJUNCTION(MAX) * TAMBIENT Power 1 switching frequency “Droop” Resistor for Adaptive Voltage Positioning Adaptive voltage positioning is used to reduce output voltage excursions during abrupt changes in load current. Regulator output voltage is offset +40 mV when the http://onsemi.com 12 CS5156 and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions. RTRACE + 80 mV IMAX This causes the output voltage to be +40 mV with no load, and −40 mV with a full load, improving regulator transient response. This trace must be wide enough to carry the full output current. (Typical trace is 1.0 inch long, 0.17 inch wide). Care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. If DC regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to VFB pin directly to the load with a separate trace (remote sense). 8. Place 5.0 V input capacitors close to the switching MOSFET. Route gate drive signals VGATE (pin 10) with a trace that is a minimum of 0.025 inches wide. 2.0 μH 33 Ω 1000 pF Figure 18. Filter Components 2.0 μH To the negative terminal of the input capacitors VCC 0.1 μF + 1200 pF × 3.0/16 V 15 11 1.0 μF VCOMP Figure 19. Input Filter Layout Guidelines 1. Place 12 V filter capacitor next to the IC and connect capacitor ground to pin 11 (PGND). 2. Connect pin 11 (PGND) with a separate trace to the ground terminals of the 5.0 V input capacitors. 3. Place fast feedback filter capacitor next to pin 8 (VFFB) and connect it’s ground terminal with a separate, wide trace directly to pin 14 (LGND). 4. Connect the ground terminals of the Compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the PWM comparator. 5. Place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (LGND). 6. To implement adaptive voltage positioning, connect both slow and fast feedback pins 16 (VFB) and 8 (VFFB) to the regulator output right at the inductor terminal. Connect inductor to the output capacitors via a trace with the following resistance: 8 5 100 pF VFFB SOFT START OFF TIME To the negative terminal of the output capacitors Figure 20. Layout Guidelines http://onsemi.com 13 CS5156 5.0V 0.1 μF MBRS120 MBRS 120 1.0 μF VCC1 + 1.0 μF MBRS120 VCC2 100 μF/10 V × 3 Tantalum Si4410DY VGATE 3.0 μH 3.3 V/10 A VID0 VID1 VID2 VID3 VID4 CS5156 COFF 1,3 PGND 330 pF SS VFB COMP 0.1 μF 2 MBR1535CT LGND 3.3 k VFFB + 100 μF/10 V × 3 Tantalum 100 pF 0.33 μF Figure 21. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter 12 V 3.3 V 1.0 μF + VCC1 VCC2 Si9410 VGATE 33 μF/25 V × 3 Tantalum 5.0 μH VID0 2.5 V/7.0 A VID1 VID2 VID3 VID4 VFB CS5156 MBR1535CT COFF 2 1,3 + 100 μF/10 V × 2 Tantalum 330 pF SS 0.1 μF PGND COMP LGND 0.33 μF 3.3 k VFFB 100 pF Figure 22. Additional Application Diagram, 3.3 V to 2.5 V/7.0 A Converter with 12 V Bias http://onsemi.com 14 CS5156 5.0V MBRS 120 0.1 μF MBRS120 1.0 μF VCC1 + 1.0 μF MBRS120 VCC2 100 μF/10 V × 3 Tantalum Remote Sense Si4410 VGATE 3.0 μH 3.3 V/10 A VID0 VID1 VFB VID2 VID3 VID4 MBR1535CT CS5156 2 1,3 10 Ω + 100 μF/10 V × 3 Tantalum COFF 330 pF PGND SS 0.1 μF 3.3 k VFFB COMP LGND 100 pF 0.33 μF Connect to other circuits for current sharing Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing http://onsemi.com 15 CS5156 PACKAGE DIMENSIONS SO−16 D SUFFIX CASE 751B−05 ISSUE J −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B A S S DIP−16 N SUFFIX CASE 648−08 ISSUE R 9 1 8 B F C DIM A B C D F G H J K L M S L S −T− H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 PACKAGE THERMAL DATA Parameter 16−SO DIP−16 Unit RΘJC Typical 28 42 °C/W RΘJA Typical 115 80 °C/W http://onsemi.com 16 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 CS5156 V2 is a trademark of Switch Power, Inc. Pentium is a registered trademark of Intel Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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