TI1 CY74FCT16373ATPVC 16-bit latch Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16373T
CY74FCT162373T
16-Bit Latches
SCCS054C - August 1994 - Revised October 2003
Features
Functional Description
• Ioff supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
• VCC = 5V ± 10%
CY74FCT16373T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
The CY74FCT162373T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162373T is ideal for driving transmission lines.
Pin Configuration
Logic Block Diagrams
SSOP/TSSOP/TVSOP
Top View
1OE
1LE
D
1O1
C
TO 7 OTHER CHANNELS
FCT162373-1
2OE
2LE
2D1
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16373T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
CY74FCT162373T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
1D1
CY74FCT16373T and CY74FCT162373T are 16-bit D-type
latches designed for use in bus applications requiring high
speed and low power. These devices can be used as two
independent 8-bit latches or as a single 16-bit latch by
connecting the Output Enable (OE) and Latch (LE) inputs.
Flow-through pinout and small shrink packaging aid in
simplifying board layout.
D
2O1
C
TO 7 OTHER CHANNELS
1OE
1
48
1O1
2
47
1D1
1O2
3
46
1D2
GND
4
45
GND
1O3
5
44
1D3
1O4
6
43
1D4
VCC
1O5
7
42
8
41
VCC
1D5
1O6
1LE
9
40
1D6
GND
10
39
GND
1O7
11
38
1D7
1O8
37
36
1D8
2O1
12
13
2O2
14
35
2D2
GND
15
34
GND
2O3
16
33
2D3
2O4
17
32
2D4
VCC
2O5
18
31
19
30
VCC
2D5
2D1
2O6
20
29
2D6
GND
21
28
GND
2O7
22
27
2D7
2O8
23
26
2D8
2OE
24
25
2LE
FCT162373-2
FCT162373-3
Copyright
© 2003, Texas Instruments Incorporated
CY74FCT16373T
CY74FCT162373T
Maximum Ratings[2, 3]
Pin Description
Name
Description
D
Data Inputs
LE
Latch Enable Inputs (Active HIGH)
OE
Output Enable Inputs (Active LOW)
O
Three-State Outputs
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ...................... Com’l −55°C to +125°C
Ambient Temperature with
Power Applied................................. Com’l −55°C to +125°C
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
Function Table[1]
Inputs
Outputs
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
D
LE
OE
O
Power Dissipation .......................................................... 1.0W
H
H
L
H
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
L
H
L
L
X
L
L
Q0
X
X
H
Z
Operating Range
Range
Industrial
Ambient
Temperature
VCC
−40°C to +85°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[5]
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=−18 mA
IIH
Input HIGH Current
IIL
IOZH
Min.
Typ.[4]
Max.
2.0
Unit
V
0.8
100
−1.2
V
VCC=Max., VI=VCC
±1
µA
Input LOW Current
VCC=Max., VI=GND
±1
µA
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=2.7V
±1
µA
IOZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=0.5V
±1
µA
IOS
Short Circuit Current[6]
VCC=Max., VOUT=GND
−80
−200
mA
Current[6]
VCC=Max., VOUT=2.5V
−50
−180
mA
±1
µA
Max.
Unit
IO
Output Drive
IOFF
Power-Off Disable
−0.7
V
mV
−140
VCC=0V, VOUT≤4.5V[7]
Output Drive Characteristics for CY74FCT16373T
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Min.
Typ.[4]
VCC=Min., IOH=−3 mA
2.5
3.5
V
VCC=Min., IOH=−15 mA
2.4
3.5
V
VCC=Min., IOH=−32 mA
2.0
3.0
Test Conditions
VCC=Min., IOL=64 mA
0.2
V
0.55
V
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q0=Previous state of flip-flop.
2. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. Typical values are at VCC=5.0V, TA= +25˚C ambient.
5. This parameter is specified but not tested.
6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
7. Tested at +25˚C.
2
CY74FCT16373T
CY74FCT162373T
Output Drive Characteristics for CY74FCT162373T
Parameter
Description
[6]
Test Conditions
Min.
Typ.[4]
Max.
Unit
IODL
Output LOW Current
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
60
115
150
mA
IODH
Output HIGH Current[6]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
−60
−115
−150
mA
VOH
Output HIGH Voltage
VCC=Min., IOH=−24 mA
2.4
3.3
VOL
Output LOW Voltage
VCC=Min., IOL=24 mA
V
0.3
0.55
V
Typ.[4]
Max.
Unit
Capacitance[5] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Test Conditions
CIN
Input Capacitance
VIN = 0V
4.5
6.0
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[4]
Max.
Unit
5
500
µA
ICC
Quiescent Power Supply Current VCC=Max.
VIN≤0.2V,
VIN≥VCC−0.2V
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
VCC=Max.
VIN=3.4V[8]
0.5
1.5
mA
ICCD
Dynamic Power Supply
Current[9]
VCC=Max., One Input
Toggling, 50% Duty Cycle,
Outputs Open, OE=GND
VIN=VCC or
VIN=GND
60
100
µA/MHz
IC
Total Power Supply Current[10]
VCC=Max., f1=10 MHz,
50% Duty Cycle, Outputs
Open, One Bit Toggling,
OE=GND, LE=VCC
VIN=VCC or
VIN=GND
0.6
1.5
mA
VIN=3.4V or
VIN=GND
0.9
2.3
mA
VCC=Max., f1=2.5 MHz,
VIN=VCC or
50% Duty Cycle, Outputs
VIN=GND
Open, Sixteen Bits Toggling,
VIN=3.4V or
OE=GND, LE=VCC
VIN=GND
2.4
4.5[11]
mA
6.4
16.5[11]
mA
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC= IQUIESCENT + IINPUTS + IDYNAMIC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input(VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
DH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
3
CY74FCT16373T
CY74FCT162373T
Switching Characteristics Over the Operating Range[12]
CY74FCT16373AT
CY74FCT162373AT
Parameter
Description
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay D to O
1.5
5.2
ns
1, 3
tPLH
tPHL
Propagation Delay
LE to O
2.0
6.7
ns
1, 5
tPZH
tPZL
Output Enable Time
1.5
6.1
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
1.5
5.5
ns
1, 7, 8
tSU
Set-Up Time HIGH or LOW, D to LE
2.0
ns
9
tH
Hold Time HIGH or LOW, D to LE
1.5
ns
9
tW
LE Pulse Width HIGH
3.3
tSK(O)
Output Skew[14]
0.5
ns
5
ns
—
CY74FCT16373CT
CY74FCT162373CT
Parameter
Description
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay
D to O
1.5
4.2
ns
1, 3
tPLH
tPHL
Propagation Delay
LE to O
2.0
5.5
ns
1, 5
tPZH
tPZL
Output Enable Time
1.5
5.5
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
1.5
5.0
ns
1, 7, 8
tSU
Set-Up Time HIGH or LOW, D to LE
2.0
ns
9
tH
Hold Time HIGH or LOW,
D to LE
1.5
ns
9
tW
LE Pulse Width HIGH
3.3
ns
5
ns
—
tSK(O)
Output
Skew[14]
0.5
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
14. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
4
CY74FCT16373T
CY74FCT162373T
Ordering Information CY74FCT16373
Speed
(ns)
4.2
Ordering Code
Package Type
CY74FCT16373CTPACT
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16373CTPVC/PVCT
O48
48-Lead (300-Mil) SSOP
CY74FCT16373CTVR
5.2
Package
Name
-
48-Lead (173-Mil) TVSOP
CY74FCT16373ATPACT
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16373ATPVC/PVCT
O48
48-Lead (300-Mil) SSOP
CY74FCT16373ATVR
-
Operating
Range
Industrial
Industrial
48-Lead (173-Mil) TVSOP
Ordering Information CY74FCT162373
Speed
(ns)
4.2
5.2
Ordering Code
Package
Name
Package Type
74FCT162373CTPACT
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162373CTPVC
O48
48-Lead (300-Mil) SSOP
74FCT162373CTPVCT
O48
48-Lead (300-Mil) SSOP
74FCT162373ATPACT
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162373ATPVC
O48
48-Lead (300-Mil) SSOP
74FCT162373ATPVCT
O48
48-Lead (300-Mil) SSOP
5
Operating
Range
Industrial
Industrial
CY74FCT16373T
CY74FCT162373T
Package Diagrams
48-Lead Shrunk Small Outline Package O48
48-Lead Thin Shrunk Small Outline Package Z48
6
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74FCT162373ATPACT
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162373A
74FCT162373ATPVCG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162373A
74FCT162373ATPVCT
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162373A
74FCT162373CTPVCG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162373C
74FCT162373ETPACT
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
-40 to 85
74FCT162373ETPVCT
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
-40 to 85
74FCT16373ATPACTG4
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16373A
74FCT16373ATPVCG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16373A
CY74FCT162373ATPVC
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162373A
CY74FCT162373CTPVC
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162373C
CY74FCT162373ETPAC
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
-40 to 85
CY74FCT162373ETPVC
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
-40 to 85
CY74FCT16373ATPACT
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16373A
CY74FCT16373ATPVC
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16373A
CY74FCT16373ATPVCT
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16373A
CY74FCT16373CTPACT
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16373C
CY74FCT16373CTPVC
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16373C
CY74FCT16373ETPAC
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
-40 to 85
CY74FCT16373ETPACT
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
-40 to 85
CY74FCT16373ETPVC
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
-40 to 85
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Apr-2015
Status
(1)
CY74FCT16373ETPVCT
OBSOLETE
Package Type Package Pins Package
Drawing
Qty
SSOP
DL
48
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74FCT162373ATPACT
Package Package Pins
Type Drawing
TSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
74FCT162373ATPVCT
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
CY74FCT16373ATPACT
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
CY74FCT16373ATPVCT
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
CY74FCT16373CTPACT
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74FCT162373ATPACT
TSSOP
DGG
48
2000
367.0
367.0
45.0
74FCT162373ATPVCT
SSOP
DL
48
1000
367.0
367.0
55.0
CY74FCT16373ATPACT
TSSOP
DGG
48
2000
367.0
367.0
45.0
CY74FCT16373ATPVCT
SSOP
DL
48
1000
367.0
367.0
55.0
CY74FCT16373CTPACT
TSSOP
DGG
48
2000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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