VGA Port Companion Circuit PACVGA105 Features Product Description • The PACVGA105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC1000-4-2 Level-4 ESD Protection Standard (±8kV contact discharge). When the channels are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. • • • • • • • Seven channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (±8kV contact discharge) Very low loading capacitance from ESD protection diodes at less than 5pF typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent supply pins (VCC, VRGB and VAUX) to facilitate operation with sub-micron Graphics Controller ICs High impedance pull-ups (50kΩ nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8kΩ nominal to VCC) for DDC_CLK and DDC_DATA lines Compact 16-pin QSOP package Lead-free version available Applications • • • • ESD protection and termination resistors for VGA (video) port interfaces Desktop PCs Notebook computers LCD monitors ©2010 SCILLC. All rights reserved. May 2010 Rev. 2 The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance. Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC. These drivers have a nominal 60Ω output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also have high impedance pull-ups (50kW nom.) pulling up to the VAUX rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8kΩ resistors pulling these inputs up to the main 5V (VCC) rail. Publication Order Number: PACVGA105/D PACVGA105 Simplified Electrical Schematic VCC VAU X VRGB 1.8k R 1.8k 50k 50k VSYNC_OUT DDC_CLK G B GNDA DDC_DATA HSYNC VSYNC GNDD Rev. 2 | Page 2 of 9 | www.onsemi.com HSYNC_OUT PACVGA105 PIN DESCRIPTIONS LEAD(s) NAME DESCRIPTION 1 HSYNC_OUT 2 HSYNC Horizontal sync signal buffer input. Connects to the VGA Controller side of the horizontal sync line. 3, 11 GNDD Digital ground reference supply pin. 4 VRGB 5 B Blue signal video protection channel. This pin is typically tied to the B video line between the VGA controller device and the video connector. 6 G Green signal video protection channel. This pin is typically tied to the G video line between the VGA controller device and the video connector. 7 R Red signal video protection channel. This pin is typically tied to the R video line between the VGA controller device and the video connector. 8 GNDA 9, 16 VCC 10 DDC_DATA DDC data pin. 12 DDC_CLK DDC clock pin. 13 VAUX 14 VSYNC 15 VSYNC_OUT Horizontal sync signal buffer output. Connects to the video connector side of the horizontal sync line. VRGB supply pin. This is an isolated supply pin for the R, G and B ESD protection circuits. Analog ground reference supply pin. VCC supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup resistors and ESD protection circuits. It is also connected to the sync buffers and to the ESD protection diodes present on the HSYNC_OUT and VSYNC_OUT lines. VAUX supply pin. This is the supply input for the 50kΩ pullups connected to the HSYNC and VSYNC buffer inputs. Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical sync line. Vertical sync signal buffer output. Connects to the video connector side of the vertical sync line. Rev. 2 | Page 3 of 9 | www.onsemi.com PACVGA105 Ordering Information PART NUMBERING INFORMATION Standard Finish Pins Package 16 QSOP Lead-free Finish Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking PACVGA105Q PACVGA105Q PACVGA105QR PACVGA105QR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER VCC,VRGB,VAUX Supply Voltage Inputs Diode Forward Current (one diode conducting at a time) DC Voltage at Inputs R, G, B HSYNC, VSYNC DDC_CLK, DDC_DATA Operating Temperature Range Storage Temperature Range Package Power Rating Rev. 2 | Page 4 of 9 | www.onsemi.com RATING UNITS [GND - 0.5] to +6.0 V 20 mA [GND - 0.5] to [VRGB + 0.5] [GND - 0.5] to [VAUX + 0.5] [GND - 0.5] to [VCC + 0.5] V V V 0 to +70 °C -40 to +150 °C 750 mW PACVGA105 STANDARD OPERATING CONDITIONS SYMBOL PARAMETER MIN MAX UNITS VCC Main Supply Voltage 4.5 5.5 V VRGB RGB Supply Voltage 1.7 3.7 V VAUX Auxiliary Supply Voltage 2.9 3.7 V VIH Logic High Input Voltage (Note 1) 2.0 VIL Logic Low Input Voltage (Note 1) VI Input Voltage RGB HSYNC, VSYNC DDC_CLK, DDC_DATA 0 0 0 V 0.8 V VRGB VAUX VCC V V V IOH High Level Output Current (Note 1) -8 mA IOL Low Level Output Current (Note 1) 8 mA TA Free-air Operating Temperature +70 °C Note 1: These parameters apply only to the HSYNC and VSYNC signals. Rev. 2 | Page 5 of 9 | www.onsemi.com 0 PACVGA105 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS VF Diode Forward Voltage IF = 10mA VOH Logic High Output Voltage IOH = -4mA, VCC = 4.5V VOL Logic Low Output Voltage IOL = 4mA, VCC = 4.5V 0.4 V IIN Input Current R, G and B pins HSYNC, VSYNC pins HSYNC, VSYNC pins VRGB = 3.63V, VIN = VRGB or GND VAUX = 3.63V, VIN = VAUX VAUX = 3.63V, VIN = GND -72.5 +1 +1 -95 μA μA μA 35 100 μA 10 μA ICC VCC Supply Current VCC = 5.5V; VAUX = VRGB = 2.97V; All inputs and outputs floating IRGB VRGB Supply Current R, G and B pins at VCC or GND; All inputs and outputs floating CIN Input Capacitance R, G and B pins HSYNC, VSYNC pins DDC_DATA, DDC_CLK pins Note 2 applies for all cases RPU MIN TYP MAX UNITS 1.0 V 4.0 -30 V 5 10 5 Pull-up Resistance DDC_DATA, DDC_CLK pins 1.62 1.8 pF pF pF 1.98 ±8 kΩ kV VESD ESD Withstand Voltage VCC = 5V; VRGB = 3.3V; VAUX = 3.3V; Note 3 tPLH SYNC Buffer L => H Propagation Delay CL = 50pF; VCC = 5.0V; RL = 500Ω; Note 4 7.0 15.0 ns tPHL SYNC Buffer H => L Propagation Delay CL = 50pF; VCC = 5.0V; RL = 500Ω; Note 4 7.0 15.0 ns tR, tF SYNC Buffer Output Rise & Fall Times CL = 50pF; VCC = 5.0V; RL = 500Ω; Note 4 7.0 ns Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: Measured at 1MHz. R/G/B inputs biased at 1.65V with VRGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V with VCC=5V. HSYNC and VSYNC inputs biased at VAUX or GND with VAUX = 3.3V and VCC = 5V. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VRGB and VCC must be bypassed to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2kV per the Human Body Model (MIL-STD-883, Method 3015). Note 4: Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times ≤ 5ns. Guaranteed by correlation to buffer output drive currents. Rev. 2 | Page 6 of 9 | www.onsemi.com PACVGA105 Application Information Figure 1. Typical Connection Diagram GNDA, the negative voltage rail for the R, G and B diodes is not connected internally to GNDD. GNDA should ideally be connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital signals from injecting noise onto the R, G and B signals. Analog GND and digital GND are typically connected on the printed circuit board. Rev. 2 | Page 7 of 9 | www.onsemi.com PACVGA105 Mechanical Details QSOP Mechanical Specifications PACVGA105 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins 16 Millimeters Inches Dimensions Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e 0.64 BSC 0.025 BSC H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs Controlling dimension: inches Package Dimensions for QSOP-16 * This is an approximate number which may vary. Rev. 2 | Page 8 of 9 | www.onsemi.com PACVGA105 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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