Samsung K6X1008C2D-PB55 128kx8 bit low power cmos static ram Datasheet

K6X1008C2D Family
CMOS SRAM
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No.
History
Draft Data
Remark
0.0
Initial draft
July 15, 2002
Preliminary
0.1
Revised
- Deleted 32-TSOP1-0820R Package Type.
- Added Commercial product.
December 4, 2002
Preliminary
0.2
Revised
- Added Lead Free 32-SOP-525 Product
May 13, 2003
Preliminary
0.3
Revised
- Added Lead Free 32-TSOP1-0820F Product
June 21, 2003
Preliminary
1.0
Finalized
- Changed ICC from 10mA to 5mA
- Changed ICC2 from 35mA to 25mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR(industrial) from 15µA to 10µA
- Changed IDR(Automotive) from 25µA to 20µA
September 16, 2003
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
128Kx8 bit Low Power full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 128K x 8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-DIP-600, 32-SOP-525,
32-SOP-525, 32-TSOP1-0820F
The K6X1008C2D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
verious operating temperature ranges and have various package types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
PRODUCT FAMILY
Product Family
Operating
Temperature
K6X1008C2D-B
Commercial(0~70°C)
K6X1008C2D-F
Industrial(-40~85°C)
K6X1008C2D-Q
Automotive(-40~125°C)
Power Dissipation
Vcc Range
Speed
Standby
(ISB1, Max)
Operating
(ICC2, Max)
10µA
551)/70ns
4.5~5.5V
15µA
25mA
25µA
PKG Type
32-DIP-600, 32-SOP-525,
32-SOP-525
32-TSOP1-0820F
32-SOP-525, 32-TSOP1-0820F
1. The parameters are tested with 50pF test load
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CS2
A12
4
29
WE
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CS1
A0
12
21
I/O8
I/O1
13
20
I/O7
I/O2
14
19
I/O6
I/O3
15
18
I/O5
VSS
16
17
I/O4
32-SOP
32-DIP
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP
Type1-Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
Row
addresses
I/O1
I/O8
Row
select
Data
cont
Precharge circuit.
Memory array
I/O Circuit
Column select
Data
cont
Column Addresses
Name
CS1, CS2
Function
Chip Select Input
CS1
OE
Output Enable Input
WE
Write Enable Input
WE
Data Inputs/Outputs
OE
CS2
I/O1~I/O8
A0~A16
Control
logic
Address Inputs
Vcc
Power
Vss
Ground
NC
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°C)
Part Name
Industrial Products(-40~85°C)
Function
K6X1008C2D-DB55
K6X1008C2D-DB70
K6X1008C2D-GB55
K6X1008C2D-GB70
K6X1008C2D-BB551)
K6X1008C2D-BB701)
K6X1008C2D-TB55
K6X1008C2D-TB70
K6X1008C2D-PB551)
K6X1008C2D-PB701)
32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
Part Name
Automotive Products(-40~125°C)
Function
K6X1008C2D-DF55
K6X1008C2D-DF70
K6X1008C2D-GF55
K6X1008C2D-GF70
K6X1008C2D-BF551)
K6X1008C2D-BF701)
K6X1008C2D-TF55
K6X1008C2D-TF70
K6X1008C2D-PF551)
K6X1008C2D-PF701)
Part Name
32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
Function
K6X1008C2D-GQ55
K6X1008C2D-GQ70
K6X1008C2D-TQ55
K6X1008C2D-TQ70
32-SOP, 55ns, L
32-SOP, 70ns, L
32-TSOP-F, 55ns, L
32-TSOP-F, 70ns, L
1. Lead Free Product
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
H
X1)
X1)
X1)
High-Z
Deselected
Standby
X1)
L
X1)
X1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X1)
L
Din
Write
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
Remark
VIN,VOUT
-0.5 to VCC+0.5V(Max. 7.0V)
V
-
Voltage on Vcc supply relative to Vss
VCC
-0.3 to 7.0
V
-
Power Dissipation
PD
1.0
W
-
TSTG
-65 to 150
°C
-
0 to 70
°C
K6X1008C2D-B
TA
-40 to 85
°C
K6X1008C2D-F
-40 to 125
°C
K6X1008C2D-Q
Voltage on any pin relative to Vss
Storage temperature
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
Input high voltage
VIH
2.2
-
Input low voltage
VIL
-0.5
3)
V
Vcc+0.5
-
V
2)
0.8
V
Note:
1. Commercial Product: TA=0 to 70°C, Otherwise specified
Industrial Product: TA=-40 to 85°C, Otherwise specified
Automotive Product: TA=-40 to 125°C, Otherwise specified
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Symbol
Test Conditions
Min Typ Max Unit
µA
ILI
VIN=Vss to Vcc
-1
-
1
Output leakage current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
Operating power supply current
ICC
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read
-
-
5
mA
ICC1
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2≥Vcc-0.2V,
VIN≤0.2V or VIN≥VCC-0.2V
-
-
7
mA
ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,
VIN=VIH or VIL
-
-
25
mA
Output low voltage
VOL
IOL=2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH=-1.0mA
2.4
-
-
V
Standby Current(TTL)
ISB
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
0.4
mA
-
10
µA
ISB1
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or
CS2≤0.2V, Other inputs=0~Vcc
-
Standby Current(CMOS)
Average operating current
4
K6X1008C2D-B
K6X1008C2D-F
-
-
15
µA
K6X1008C2D-Q
-
-
25
µA
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40~125°C)
Speed Bins
Parameter List
Symbol
55ns
Min
Read
Max
Min
Max
Read Cycle Time
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
tLZ
10
-
10
-
ns
tOLZ
5
-
5
-
ns
tHZ
0
20
0
25
ns
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
25
ns
Data to Write Time Overlap
tDW
20
-
25
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
Output Disable to High-Z Output
Write
Units
70ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR
CS1≥Vcc-0.2V1)
Data retention current
IDR
Vcc=3.0V, CS1≥Vcc-0.2V1)
Data retention set-up time
tSDR
Recovery time
tRDR
Typ
Max
Unit
2.0
-
5.5
V
K6X1008C2D-B
-
-
10
µA
K6X1008C2D-F
-
-
10
µA
µA
K6X1008C2D-Q
See data retention waveform
Min
-
-
20
0
-
-
5
-
-
ms
1. CS1≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V
5
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS1
tAW
CS2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
7
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
4.5V
2.2V
VDR
CS≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
4.5V
CS2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
8
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 DUAL INLINE PACKAGE (600mil)
0.25
+0.10
-0.05
0.010+0.004
-0.002
#17
15.24
0.600
#32
13.60±0.20
0.535±0.008
#1
#16
41.91±0.20
1.650±0.008
3.30±0.30
0.130±0.012
0.46±0.10
0.018±0.004
1.52±0.10
0.060±0.004
( 1.91 )
0.075
0~15°
3.81±0.20
0.150±0.008
5.08
0.200 MAX
42.31 MAX
1.666
2.54
0.100
0.38
0.015 MIN
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#17
14.12±0.30
0.556±0.012
#1
#16
2.74±0.20
0.108±0.008
3.00
0.118 MAX
20.87 MAX
0.822
20.47±0.20
0.806±0.008
11.43±0.20
0.450±0.008
0.20 +0.10
-0.05
0.008+0.004
-0.002
13.34
0.525
#32
0.80±0.20
0.031±0.008
0.10 MAX
0.004 MAX
( 0.71 )
0.028
+0.100
-0.050
+0.004
0.016 -0.002
0.41
1.27
0.050
0.05
0.002 MIN
9
Revision 1.0
September 2003
K6X1008C2D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
0.008+0.004
-0.002
0.20
20.00±0.20
0.787±0.008
#1
#32
8.40
0.331 MAX
0.50
0.0197
#16
0.25
0.010 TYP
0.25
)
0.010
8.00
0.315
(
#17
1.00±0.10
0.039±0.004
1.20
0.047 MAX
18.40±0.10
0.724±0.004
+0.10
-0.05
0.006+0.004
-0.002
0.05
0.002 MIN
0~8°
0.45 ~0.75
0.018 ~0.030
(
10
0.10 MAX
0.004 MAX
0.15
0.50
)
0.020
Revision 1.0
September 2003
Similar pages