Revised August 1999 74F620 • 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs General Description Features These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA and have 3STATE outputs. Dual enable pins (GAB, GBA) allow data transmission from the A bus to the B bus or from the B bus to the A bus. The 74F620 is an inverting option of the 74F623. ■ Designed for asynchronous two-way data flow between busses ■ Outputs sink 64 mA ■ Dual enable inputs control direction of data flow ■ Guaranteed 4000V minimum ESD protection ■ 74F620 is an inverting option of the 74F623 Ordering Code: Order Number Package Number Package Description 74F620PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74F623SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F623PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram FAST is a registered trademark of Fairchild Semiconductor Corporation © 1999 Fairchild Semiconductor Corporation DS009577 www.fairchildsemi.com 74F620 • 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs April 1988 74F620 • 74F623 Unit Loading/Fan Out Pin Names Description GBA, GAB Enable Inputs A0–A7 A Inputs or 3-STATE Outputs B0–B7 B Inputs or 3-STATE Outputs U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 1.0/1.0 20 µA/−0.6 mA 3.5/1.083 70 µA/−0.4 mA 150/40 −3 mA/64 mA 3.5/1.083 70 µA/−0.4 mA 150/40 −3 mA/64 mA Function Table Functional Description The enable inputs GAB and GBA control whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. If both GBA and GAB are disabled (GBA HIGH and GAB LOW), the outputs are in the high impedance state and data is stored at the A and B busses. When GBA is active LOW, B data is sent to the A bus. When GAB is active HIGH, data from the A bus is sent to the B bus. If both enable inputs are active (GBA LOW and GAB HIGH) B data is sent to the A bus while A data is sent to the B bus. Enable Inputs GBA GAB Operation 74F620 74F623 L L B Data to A Bus B Data to A Bus H H A Data to B Bus A Data to B Bus H L L H Z Z B Data to A Bus, B Data to A Bus, A Data to B Bus A Data to B Bus H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance Logic Diagrams 74F620 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F623 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) in LOW State (Max) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins) VOH Output HIGH V Min IOH = −15 mA (An, Bn) 0.55 V Min IOL = 64 mA (A n, Bn) 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V (GBA, GAB) 0.5 mA Max VIN = 5.5V (An, Bn) 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V (Non I/O Pins) 70 µA Max VOUT = 2.7V (An, Bn) −650 µA Max VOUT = 0.5V (An, Bn) −225 mA Max VOUT = 0V VOL Output LOW Voltage IIH 10% VCC V Conditions Input HIGH Voltage Voltage 2.0 Units VIH 2.0 10% VCC Input HIGH Current IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown (I/O) ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current Recognized as a HIGH Signal Recognized as a LOW Signal IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IIL Input LOW Current IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test 500 µA 0.0V VOUT = 5.25V ICCH Power Supply Current (74F620) 82 mA Max VO = HIGH, VIN = 0.2V ICCL Power Supply Current (74F620) 82 mA Max VO = LOW ICCZ Power Supply Current (74F620) 95 mA Max VO = HIGH Z ICCH Power Supply Current (74F623) 65 mA Max VO = HIGH ICCL Power Supply Current (74F623) 82 mA Max VO = LOW, VIN = 0.2V ICCZ Power Supply Current (74F623) 85 mA Max VO = HIGH Z −100 3 www.fairchildsemi.com 74F620 • 74F623 Absolute Maximum Ratings(Note 1) 74F620 • 74F623 AC Electrical Characteristics Symbol Parameter Min TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Max Min tPLH Propagation Delay 2.5 Typ 7.5 2.0 8.0 tPHL A Input to B Output (74F620) 2.0 7.0 2.0 7.0 Max tPLH Propagation Delay 2.5 7.5 2.0 8.0 tPHL B Input to A Output (74F620) 2.0 7.0 2.0 7.0 tPLH Propagation Delay 1.5 6.5 1.5 7.5 tPHL A Input to B Output (74F623) 2.0 7.0 2.0 7.5 tPLH Propagation Delay 1.5 6.5 1.5 7.5 tPHL B Input to A Output (74F623) 2.0 7.0 2.0 7.5 8.0 tPZH Enable Time 2.0 7.0 2.0 tPZL GBA Input to A Output 2.5 8.0 2.0 8.5 tPHZ Disable Time 1.5 6.5 1.5 7.5 tPLZ GBA Input to A Output 1.0 5.5 1.0 5.5 tPZH Enable Time 2.0 7.5 2.0 8.5 tPZL GAB Input to B Output (74F620) 3.0 8.0 2.0 8.5 tPHZ Disable Time 2.5 8.0 2.0 9.0 tPLZ GAB Input to B Output (74F620) 2.0 7.5 2.0 8.0 tPZH Enable Time 2.0 7.5 2.0 8.5 tPZL GAB Input to B Output (74F623) 2.5 8.0 2.0 8.5 tPHZ Disable Time 2.0 8.0 2.0 9.0 tPLZ GAB Input to B Output (74F623) 2.0 8.0 2.0 8.0 www.fairchildsemi.com 4 Units ns ns ns ns ns ns ns 74F620 • 74F623 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74F620 • 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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