MMDF2P02E Power MOSFET 2 Amps, 25 Volts P−Channel SO−8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain−to−source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc−dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. http://onsemi.com 2 AMPERES, 25 VOLTS RDS(on) = 250 mW P−Channel D G Features • • • • • • • • • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs Miniature SO−8 Surface Mount Package − Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, with Soft Recovery IDSS Specified at Elevated Temperatures Avalanche Energy Specified Mounting Information for SO−8 Package Provided Pb−Free Package is Available MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 25 Vdc Gate−to−Source Voltage − Continuous VGS ± 20 Vdc ID ID 2.5 1.7 13 Adc 2.0 16 W mW/°C Drain Current − Continuous @ TA = 25°C Drain Current − Continuous @ TA = 100°C Drain Current − Single Pulse (tp ≤ 10 ms) Total Power Dissipation @ TA = 25°C (Note 2) Derate above 25°C Operating and Storage Temperature Range IDM PD TJ, Tstg 8 −55 to 150 F2PO2 AYWW G G SO−8, Dual CASE 751 STYLE 11 8 1 1 F2P02 = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT Source−1 1 8 Drain−1 Gate−1 2 7 Drain−1 °C Source−2 3 6 Drain−2 mJ Gate−2 4 5 Drain−2 EAS Thermal Resistance, Junction−to−Ambient (Note 2) RqJA 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 sec. TL 260 °C 245 Top View ORDERING INFORMATION Device MMDF2P02ER2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Negative sign for P−Channel device omitted for clarity. 2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10 sec. max. April, 2006 − Rev. 8 MARKING DIAGRAM Apk Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 W) © Semiconductor Components Industries, LLC, 2006 S 1 MMDF2P02ER2G Package Shipping† SO−8 2500 Tape & Reel SO−8 (Pb−Free) 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MMDF2P02E/D MMDF2P02E ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 3) Characteristic Symbol Min Typ Max Unit 25 − − 2.2 − − − − − − 1.0 10 − − 100 1.0 − 2.0 3.8 3.0 − − − 0.19 0.3 0.25 0.4 gFS 1.0 2.8 − Mhos Ciss − 340 475 pF Coss − 220 300 Crss − 75 150 td(on) − 20 40 tr − 40 80 td(off) − 53 106 tf − 41 82 td(on) − 13 26 tr − 29 58 td(off) − 30 60 tf − 28 56 QT − 10 15 Q1 − 1.0 − Q2 − 3.5 − Q3 − 3.0 − VSD − 1.5 2.0 Vdc trr − 32 64 ns ta − 19 − tb − 12 − QRR − 0.035 − OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc W DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 5.0 Vdc, RG = 6.0 W) Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 W) Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 4) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time See Figure 11 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Storage Charge 3. Negative sign for P−Channel device omitted for clarity. 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 mC MMDF2P02E TYPICAL ELECTRICAL CHARACTERISTICS 4 4.5 V 3 4.3 V 2 4.1 V 3.9 V 1 0 3.7 V 3.5 V 3.3 V 0 VDS ≥ 10 V TJ = 25°C 4.7 V I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 4 5V VGS = 10 7 V 0.4 0.8 1.2 1.6 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 3 100°C 2 25°C TJ = −55°C 1 0 2.5 2 RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 0.6 ID = 1 A TJ = 25°C 0.5 0.4 0.3 0.2 0.1 0 3 4 5 7 6 8 9 4.5 Figure 2. Transfer Characteristics 10 0.6 TJ = 25°C 0.5 0.4 VGS = 4.5 0.3 0.2 10 V 0.1 0 0.5 1 1.5 2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.0 100 VGS = 10 V ID = 2 A VGS = 0 V 1.5 I DSS , LEAKAGE (nA) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 1. On−Region Characteristics 3 3.5 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1.0 0.5 0 −50 −25 0 25 50 75 100 125 TJ = 125°C 10 100°C 1 150 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 20 MMDF2P02E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP 1000 VDS = 0 V TJ = 25°C Ciss 800 C, CAPACITANCE (pF) VGS = 0 V VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. 600 Crss 400 Ciss Coss 200 Crss 0 10 5 0 VGS 5 10 15 20 25 12 QT 9 6 3 4 Q3 0 8 Q2 Q1 ID = 2 A TJ = 25°C 2 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 12 VGS VDS 0 30 16 4 6 8 Qg, TOTAL GATE CHARGE (nC) 10 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation http://onsemi.com 4 0 12 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. MMDF2P02E 2 100 TJ = 25°C VGS = 0 V IS, SOURCE CURRENT (AMPS) t, TIME (ns) VDD = 10 V ID = 2 A VGS = 10 V TJ = 25°C td(off) tr tf td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 1.6 1.2 0.8 0.4 0 0.6 100 0.8 1 1.2 1.4 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.6 Figure 10. Diode Forward Voltage versus Current Figure 9. Resistive Switching Time Variation versus Gate Resistance di/dt = 300 A/ms Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MMDF2P02E 10 280 Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max. VGS = 20 V SINGLE PULSE TC = 25°C 100 ms EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 10 ms 10 ms 1 dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1 I pk = 7 A 240 200 160 120 80 40 0 10 100 25 50 75 100 150 125 TJ, STARTING JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 Normalized to qja at 10s. Chip 0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W 0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F 0.01 0.01 SINGLE PULSE 0.001 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) 1.0E+00 1.0E+01 Figure 14. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 6 1.0E+02 Ambient 1.0E+03 MMDF2P02E PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. E−FET and MiniMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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