IRF CHL8225G-00CRTY Digital multi-phase buck controller Datasheet

CHL8225G/8G
Digital Multi-Phase Buck Controller
DESCRIPTION
 Pb-Free, RoHS, 6x6 40-pin & 8x8 56-pin QFN, MSL2
package
APPLICATIONS
 Multiphase GPU systems
The CHL8225G/8G provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal. The CHL8225G/8G
includes numerous features like register diagnostics for
fast design cycles and platform differentiation, simplifying
VRD design and enabling fastest time-to-market with its
“set-and-forget” methodology.
RCSP
RCSM
IRTN1
ISEN1
IRTN2
ISEN2
IRTN3
ISEN3
IRTN4
ISEN4
IRTN5
ISEN5
PIN DIAGRAM
40
39
38
37
36
35
34
33
32
31
1
30
2
29
ISEN6
 +3.3V supply voltage; 0ºC to 85ºC ambient
operation
IRTN7
 Compatible with IR ATL and 3.3V tri-state Drivers
The I2C/PMBus interface can communicate with up to 16
CHL8225G/8G-based VR loops. Device configuration and
fault parameters are defined using the IR Digital Power
Design Center (DPDC) GUI and stored in on-chip NVM.
IRTN6
 Non-Volatile Memory (NVM) for custom
configuration
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
ISEN5
 I2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both
loops
IRTN5
 Per-Loop Fault Protection: OVP, UVP, OCP, OTP
ISEN4
 IR Adaptive Transient Algorithm (ATA) minimizes
output bulk capacitors and system cost
IRTN4
 Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
The CHL8225G/8G includes the IR Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. IR Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. IR Dynamic Phase Control adds and
drops phases based upon load current. The CHL8225G/8G
can be configured to enter 1-phase operation and active
diode emulation based upon load current or by command.
ISEN3
 IR Efficiency Shaping Features including Variable
Gate Drive, Dynamic Phase Control
IRTN3
 Phase Switching frequency from 200kHz to 1.2MHz
ISEN2
 ICRITICAL Monitor and Phase Current Capture Mode
IRTN2
 Input Voltage Management for up to 3 Input
Voltages
ISEN1
 Dynamic voltage control by 2-bit parallel interface
with Gamer Mode override and Vmax setting
The CHL8225G/8G are dual-loop, digital multi-phase buck
controllers. The CHL8225G drives up to 5 phases and the
CHL8228G drives up to 8 phases. They feature Input
Voltage Management allowing up to 3 input voltages to be
monitored to ensure adequate power is delivered to the
load. Dynamic voltage control is provided by 4 registers
which are programmed through I2C/SMBus/PMBus and
then selected using a 2-bit parallel bus for fast access.
IRTN1
 5-phase & 8-phase dual output PWM Controller
with phases flexibly assigned between Loops 1 & 2
IRTN8
FEATURES
56
55
54
53
52
51
50
49
48
47
46
45
44
43
ISEN8
1
42
ISEN7
RCSP
2
41
RCSP_L2
RCSM
3
40
RCSM_L2
VCC
4
39
VCC
VRHOT2
5
38
VSEN_L2
37
VRTN_L2
36
PWM8
35
PWM7
RCSP_L2
RCSM_L2
VCC
3
28
VCC
VSEN
6
VSEN
4
27
VSEN_L2
VRTN
7
VRTN
5
26
VRTN_L2
RRES
8
RRES
6
25
PWM5
TSEN
9
34
PWM6
TSEN
7
24
PWM4
V18A
10
33
PWM5
8
23
PWM3
VR_READY_L1
11
32
V18A
PWM4
VR_READY_L2
12
31
9
22
PWM2
PWM3
VR_READY_L1
EN_L2
13
30
PWM2
21
PWM1
29
PWM1
CHL8225G
40 Pin 6x6 QFN
Top View
41 GND
10
57 GND
VINSEN
Figure 1: CHL8225G Package Top View
1
14
June 21, 2013 | FINAL | V1.12
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VINSEN_AUX2
VIDSEL0_L2
VIDSEL1
VIDSEL0
VRHOT_ICRIT#
ENABLE
VIDSEL1_L2
SMB_DIO
SMB_CLK
VBOOT
VMAX
TSEN2
VAR_GATE
20
VAR_GATE
19
SMB_CLK
18
SMB_DIO
17
ENABLE
16
VRHOT_ICRIT#
15
VIDSEL0
14
VIDSEL1
13
VIDSEL_L2
VINSEN
12
VINSEN_AUX1
11
VINSEN_AUX1
VR_READY_L2
CHL8228G
56 Pin 8x8 QFN
Top View
Figure 2: CHL8228G Package Top View
CHL8225G/8G
Digital Multi-Phase Buck Controller
ORDERING INFORMATION
CHL822  G ―     
Package
Packing Qty
T – Tape & Reel / TY - Tray
QFN
T=3000
TY=4900
Part Number
CHL8225G-00CRT
CHL8225G-00CRTY
R – Package Type (QFN)
QFN
T=3000
CHL8225G-xxCRT
QFN
T=3000
TY=2600
CHL8228G-00CRT
CHL8228G-00CRTY
QFN
T=3000
CHL8228G-xxCRT1
C – Operating Temperature
(Commercial Standard)
xx – Configuration File
38
37
36
35
34
33
32
IRTN1
ISEN1
IRTN2
ISEN2
IRTN3
ISEN3
IRTN4
ISEN4
IRTN5
ISEN5
IRTN6
ISEN6
IRTN7
ISEN5
IRTN5
ISEN4
IRTN4
ISEN3
IRTN3
ISEN2
IRTN2
IRTN1
ISEN1
39
IRTN8
Notes:
1. “xx” indicates customer specific configuration file.
Part Number
5: CHL8225G
8: CHL8228G
40
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
ISEN8
1
42
ISEN7
RCSP
2
41
RCSP_L2
31
RCSP
1
30
RCSP_L2
RCSM
3
40
RCSM_L2
RCSM
2
29
RCSM_L2
VCC
4
39
VCC
VCC
3
28
VCC
VRHOT2
5
38
VSEN_L2
VSEN
6
37
VRTN_L2
VRTN
7
36
PWM8
RRES
8
35
PWM7
TSEN
9
34
PWM6
24
PWM4
V18A
10
33
PWM5
VR_READY_L1
11
32
PWM4
VR_READY_L2
12
31
PWM3
EN_L2
13
30
PWM2
VINSEN
14
29
PWM1
PWM2
14
15
16
17
18
19
VIDSEL1
VIDSEL0
VRHOT_ICRIT#
ENABLE
SMB_DIO
SMB_CLK
20
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VAR_GATE
13
57 GND
PWM1
TSEN2
12
VAR_GATE
11
VIDSEL_L2
21
VINSEN
10
VINSEN_AUX1
VR_READY_L2
VMAX
22
41 GND
VBOOT
9
PWM3
SMB_CLK
23
SMB_DIO
VR_READY_L1
8
PWM5
VIDSEL1_L2
V18A
25
ENABLE
TSEN
7
VRTN_L2
VRHOT_ICRIT#
6
26
VIDSEL0
RRES
CHL8225G
40 Pin 6x6 QFN
Top View
CHL8228G
56 Pin 8x8 QFN
Top View
VIDSEL1
5
VSEN_L2
VIDSEL0_L2
VRTN
27
VINSEN_AUX2
4
VINSEN_AUX1
VSEN
Figure 4: CHL8228G Top View Enlarged
Figure 3: CHL8225G Top View Enlarged
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June 21, 2013 | FINAL | V1.12
Digital Multi-Phase Buck Controller
CHL8225G/8G
FUNCTIONAL BLOCK DIAGRAM
V18A
RCSP_L2
VCC
VID_2
RSCM_L2
1.8V
AFE_2
LDO
VSEN_L2
VRTN_L2
ITOT_2
RCSP
Vout1_Error
Voltage
ADC
PWM1
RSCM
Vout2_Error
AFE_1
PWM2
VSEN
VID_1
VRTN
PWM3
PWM4
ISEN1
Mode Control
IRTN1
.
.
.
ISENx
.
.
.
IP1
.
.
.
PWM Generator
PWM5
Control
and
Monitoring
IPx
IRTNx
Σ
Phase_
Period_1
Phase_
Period_2
ITOT_1
PWM7
CHL8225G CHL8228G
x
3
4
y
4
5
z
5
8
Iout
.
.
.
IRTNz
Vin
IPy
.
.
.
IPz
ITOT_2
Σ
VAR_GATE
Vout
Temp
Current ADC
Fault Bus
System Clock
IP1
.
.
.
IP5
Only for
CHL8228G
Only for
CHL8228G
PWM8
ISENy
IRTNy
.
.
.
ISENz
PWM6
System Clock
IP6
.
.
.
IP8
ADC Clocks
MUX Clocks
Phase_Period_1
TSEN2
(CHL8228G only)
Phase_Period_2
VID_1
TSEN
VID_2
VINSEN
Monitor ADC
VINSEN_AUX1
VINSEN_AUX2
(CHL8228G only)
V3_3
EN
VIDSEL1
VIDSEL0
SMB_DIO
SMB_CLK
Reference,
Oscillator,
State Control,
Interfaces,
Registers and
NVM
Iout
Vin
Temp
Fault Bus
VRHOT_ICRIT#
VR_READY_L1
VR_READY_L2
VIDSEL0_L2
VIDSEL1_L2
Only for
CHL8228G
VRHOT2
EN_L2
VBOOT VMAX RRES
Only for CHL8228G
Figure 5: CHL8225G & CHL8228G Functional Block Diagram
3
June 21, 2013 | FINAL | V1.12
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