Revised March 2005 74LVT240 • 74LVTH240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The LVT240 and LVTH240 are inverting octal buffers and line drivers designed to be employed as memory address drivers, clock drivers and bus oriented transmitters or receivers which provides improved PC board density. ■ Input and output interface capability to systems at 5V VCC The LVTH240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal buffers and line drivers are designed for lowvoltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT240 and LVTH240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH240), also available without bushold feature (74LVT240) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink 32 mA/64 mA ■ Functionally compatible with the 74 series 240 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Package Description Number 74LVT240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVT240SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT240MSA MSA20 74LVT240MTC MTC20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVT240MTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH240SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH240MSA MSA20 74LVTH240MTC MTC20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH240MTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JECED J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS500153 www.fairchildsemi.com 74LVT240 • 74LVTH240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs July 1999 74LVT240 • 74LVTH240 Pin Descriptions Logic Symbol IEEE/IEC Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 3-STATE Outputs Truth Tables Inputs In OE1 Connection Diagram Outputs (Pins 12, 14, 16, 18) L L L H L H X Z Inputs OE2 2 Outputs (Pins 3, 5, 7, 9) In L L L H L H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance www.fairchildsemi.com H H Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 3) V VI GND mA VO GND mA 64 VO ! VCC 128 VO ! VCC Output at LOW State Output at HIGH State mA mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Min Max VCC Symbol Supply Voltage Parameter 2.7 3.6 V VI Input Voltage 0 5.5 V IOH HIGH-Level Output Current 32 IOL LOW-Level Output Current 64 TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Units mA 40 85 qC 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC (V) Parameter T A 40qC to 85qC Min Typ Max Units 1.2 V Conditions (Note 4) Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC0.2 V IOH 100 PA 2.7 2.4 V IOH 8 mA 3.0 2.0 V IOH 32 mA VOL II(HOLD) 2.7 Output LOW Voltage (Note 5) II VO t VCC 0.1V 0.2 V IOL 100 PA 2.7 0.5 V IOL 24 mA 3.0 0.4 V IOL 16 mA 3.0 0.5 V IOL 32 mA 3.0 0.55 V IOL 64 mA 3.0 75 PA VI 0.8V 75 PA VI 2.0V Bushold Input Over-Drive Current to Change State 3.0 500 PA (Note 6) PA (Note 7) Input Current 3.6 10 PA VI 5.5V 3.6 r1 PA VI 0V or VCC 5 PA VI 0V 1 PA VI VCC 0 r100 PA 0V d VI or VO d 5.5V 0–1.5V r100 PA 500 Data Pins IPU/PD V Bushold Input Minimum Drive Control Pins IOFF 0.8 VO d 0.1V or 2.7 (Note 5) II(OD) 2.0 II 18 mA VIK Power Off Leakage Current Power up/down 3-STATE Output Current 3.6 VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V 3 www.fairchildsemi.com 74LVT240 • 74LVTH240 Absolute Maximum Ratings(Note 2) 74LVT240 • 74LVTH240 DC Electrical Characteristics Symbol (Continued) T A 40qC to 85qC VCC (V) Parameter Min Typ Units Max Conditions (Note 4) IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d VO d 5.5V, Outputs Disabled 'ICC Increase in Power Supply Current 3.6 0.2 One Input at VCC 0.6V mA (Note 8) Other Inputs at VCC or GND Note 4: All typical values are at VCC 3.3V, TA 25qC. Note 5: Applies to bushold versions only (74LVTH240). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics (Note 9) Symbol 25qC TA VCC Parameter (V) Min Typ Max Units Conditions CL 500: 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Note 9: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA 40qC to 85qC CL 50 pF, RL 500: Symbol VCC Parameter Min 3.3V r0.3V Typ VCC 2.7V Max Min Max 1.1 3.8 1.1 4.6 1.3 4.0 1.3 4.2 1.1 4.6 1.1 5.6 1.4 4.4 1.4 5.1 2.0 4.5 2.0 4.7 1.8 4.3 1.8 4.3 Units (Note 11) tPLH Propagation Delay Data to Output tPHL Output Enable Time tPZH tPZL tPHZ Output Disable Time tPLZ tOSHL Output to Output Skew tOSLH (Note 12) Note 11: All typical values are at VCC 3.3V, TA 1.0 ns ns ns 1.0 ns 25qC. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 13) Symbol Parameter Conditions CIN Input Capacitance VCC 0V, VI COUT Output Capacitance VCC 3.0V, VO Note 13: Capacitance is measured at frequency f www.fairchildsemi.com 0V or VCC 0V or VCC 1 MHz, per MIL-STD-883, Method 3012. 4 Typical Units 3 pF 6 pF 74LVT240 • 74LVTH240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVT240 • 74LVTH240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVT240 • 74LVTH240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com 74LVT240 • 74LVTH240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8