74LVQ86 Low Voltage Quad 2-Input Exclusive-OR Gate General Description Features The LVQ86 contains four 2-input exclusive-OR gates. n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number Package Number Package Description 74LVQ86SC M14A 14-Lead (0.150" Wide) Molded Small Outline Package, SOIC JEDEC 74LVQ86SJ M14D 14-Lead Small Outline Package, SOIC EIAJ Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Assignment SOIC JEDEC and EIAJ DS011348-1 DS011348-2 Pin Descriptions Pin Names © 1998 Fairchild Semiconductor Corporation Description A0–A3 Inputs B0–B3 Inputs O0–O3 Outputs DS011348 www.fairchildsemi.com 74LVQ86 Low Voltage Quad 2-Input Exclusive-OR Gate May 1998 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) LVQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 74LVQ Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 3.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 2.0V to 3.6V 0V to VCC 0V to VCC −40˚C to +85˚C 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation . ± 200 mA −65˚C to +150˚C Note 2: Unused inputs must be held HIGH or LOW.. They may not float. ± 100 mA DC Electrical Characteristics Symbol VIH Parameter Minimum High Level VCC (V) 3.0 TA = 25˚C TA = −40˚C to +85˚C Typ 1.5 Units 2.0 2.0 V Input Voltage VIL Maximum Low Level Minimum High Level Output Voltage VOUT = 0.1V or VCC − 0.1V 3.0 1.5 0.8 0.8 V VOUT = 0.1V or VCC − 0.1V Input Voltage VOH Conditions Guaranteed Limits 2.9 2.9 V IOUT = −50 µA 2.58 2.48 V VIN = VIL or VIH (Note 3) 0.1 0.1 V 3.0 0.36 0.44 3.6 ± 0.1 ± 1.0 µA VI = VCC, GND VOLD = 0.8V Max (Note 5) 3.0 2.99 3.0 IOH = −12 mA VOL Maximum Low Level Output Voltage 3.0 0.002 IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA IIN Maximum Input Leakage Current IOLD Minimum Dynamic (Note 4) 3.6 36 mA IOHD Output Current 3.6 −25 mA VOHD = 2.0V Min (Note 5) ICC Maximum Quiescent 3.6 20.0 µA VIN = VCC or GND 2.0 Supply Current VOLP Quiet Output 3.3 0.5 0.8 V (Notes 6, 7) 3.3 −0.5 −0.8 V (Notes 6, 7) 3.3 1.8 2.0 V (Notes 6, 8) 3.3 1.8 0.8 V (Notes 6, 8) Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 20 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 AC Electrical Characteristics Symbol Parameter Min Typ Max Min 2.0 7.2 16.2 1.5 18.0 3.3 ± 0.3 2.0 6.0 11.5 1.5 12.5 Propagation Delay tPHL tOSHL, Output to Output Skew tOSLH (Note 9) TA = −40˚C to +85˚C CL = 50 pF 2.7 Propagation Delay tPLH TA = +25˚C CL = 50 pF VCC (V) Units Max 2.7 2.0 7.8 16.2 1.5 18.0 3.3 ± 0.3 2.0 6.5 11.5 1.5 12.5 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns Note 9: Skews defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units Conditions CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open CPD (Note 10) Power Dissipation Capacitance 23 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 4 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead (0.150" Wide) Molded Small Outline Package, SOIC JEDEC Package Number M14A 5 www.fairchildsemi.com 74LVQ86 Low Voltage Quad 2-Input Exclusive-OR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package, SOIC EIAJ Package Number M14D LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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