MC100LVELT23 3.3 VDual Differential LVPECL/LVDS to LVTTL Translator Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal. The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a VCC of +3.3 V. Features • • • • MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 8 2.0 ns Typical Propagation Delay Maximum Frequency > 180 MHz Differential LVPECL Inputs PECL Mode Operating Range:VCC = 3.0 V to 3.8 V with GND = 0 V 24 mA LVTTL Outputs Flow Through Pinouts Internal Pulldown and Pullup Resistors Pb−Free Packages are Available KVT23 ALYW G 1 TSSOP−8 DT SUFFIX CASE 948R 1 KR23 ALYWG G 4J M G G • • • • http://onsemi.com 1 4 DFN8 MN SUFFIX CASE 506AA A L Y W M G = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 14 1 Publication Order Number: MC100LVELT23/D MC100LVELT23 Table 1. PIN DESCRIPTION D0 D0 1 8 2 LVPECL D1 VCC 7 Q0 6 Q1 Pin Q0, Q1 D0*, D1* D0*, D1* VCC GND EP LVTTL 3 Function LVTTL Outputs Differential LVPECL Inputs Positive Supply Ground Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. ** Pins will default to VCC/2 when left open. D1 4 5 GND Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50 kW Internal Input Pullup Resistor 50 kW ESD Protection Human Body Model Machine Model CDM Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 1500 V > 100 V > 2000 V Level 1 UL 94 V−0 @ 0.125 in 91 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. Refer to Application Note AND8003/D for additional information. http://onsemi.com 2 MC100LVELT23 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Power Supply Parameter GND = 0 V Condition 1 3.8 V VI Input Voltage GND = 0 V, VI not more positive than VCC 3.8 V Iout Output Current Continuous Surge 50 100 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Condition 2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. LVPECL INPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0 V (Note 2) −40°C Symbol Characteristic 25°C Min Typ Max Min Typ Max Min Typ Max Unit 10 18 25 10 18 25 10 18 25 mA 15 26 36 15 26 36 15 26 36 mA 2420 2135 2420 2135 2420 mV 1825 1490 1825 1490 1825 mV VCC 1.2 VCC 1.2 VCC V 150 mA ICCH Power Supply Current (Outputs set to HIGH) ICCL Power Supply Current (Outputs set to LOW) VIH Input HIGH Voltage (Note 4) 2135 VIL Input LOW Voltage (Note 4) 1490 VIHCMR Input HIGH Voltage Common Mode Range (Notes 3 and 4) 1.2 IIH Input HIGH Current IIL Input LOW Current 150 D 85°C −150 150 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. All values vary 1:1 with VCC. VCC can vary ±0.3 V. 3. VIHCMR min varies 1:1 with GND, max varies 1:1 with VCC. 4. LVTTL output RL = 500 W to GND. http://onsemi.com 3 MC100LVELT23 Table 5. LVTTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0V (Note 5) −40°C Characteristic Min VOH Output HIGH Voltage (IOH = −3.0 mA) (Note 6) 2.4 VOL Output LOW Voltage (IOL = 24 mA) (Note 6) IOS Output Short Circuit Current Symbol Typ 25°C Max Min 85°C Typ Max 2.4 −50 Typ Max 2.4 0.5 −180 Min V 0.5 −180 −50 Unit −180 0.5 V −50 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. All values vary 1:1 with VCC. VCC can vary ±0.3 V. 6. LVTTL output RL = 500 W to GND. Table 6. AC CHARACTERISTICS VCC = 3.3 V; GND = 0 V (Notes 7, 8) −40°C Symbol Min Characteristic Fmax Maximum Toggle Frequency (Note 9) 180 tPLH, tPHL Propagation Delay to Output Differential 1.0 tSK+ + tSK− − tSKPP Typ 25°C Max 85°C Typ Max 180 1.5 2.5 Output−to−Output Skew++ Output−to−Output Skew− − Part−to−Part Skew (Note 10) 15 35 70 tJITTER Random Clock Jitter (RMS) VPP Input Voltage Swing (Differential Configuration) (Note 11) tr tf Output Rise/Fall Times (0.8 V − 2.0 V) Q, Q Min Min Typ Max 180 1.0 1.7 2.5 60 80 500 15 40 70 4.0 10 200 800 1000 330 600 900 1.0 Unit MHz 1.7 2.5 ns 70 80 500 30 40 140 125 80 500 ps 4.0 10 4.0 10 ps 200 800 1000 200 800 1000 mV 330 600 900 330 650 900 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. All values vary 1:1 with VCC. VCC can vary ±0.3 V. 8. LVTTL output RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 2. 9. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only. 10. Skews are measured between outputs under identical conditions. 11. 200 mV input guarantees full logic swing at the output. APPLICATION TTL RECEIVER CHARACTERISTIC TEST *CL includes fixture capacitance CL * RL AC TEST LOAD GND Figure 2. TTL Output Loading Used for Device Evaluation http://onsemi.com 4 MC100LVELT23 ORDERING INFORMATION Package Shipping† SOIC−8 98 Units / Rail MC100LVELT23DG SOIC−8 (Pb−Free) 98 Units / Rail MC100LVELT23DR2 SOIC−8 2500 / Tape & Reel MC100LVELT23DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100LVELT23DT TSSOP−8 100 Units / Rail MC100LVELT23DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100LVELT23DTR2 TSSOP−8 2500 / Tape & Reel MC100LVELT23DTRG TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100LVELT23MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel Device MC100LVELT23D MC100LVELT23MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 5 MC100LVELT23 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− H 0.10 (0.004) D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100LVELT23 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF S M T U V S 0.25 (0.010) B −U− 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S M A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 7 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100LVELT23 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 0.10 C TOP VIEW 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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