Rohm BU9706KS Lcd segment driver Datasheet

Standard ICs
LCD segment driver
BU9706KS
The BU9706KS is a 40-output LCD segment driver provided with a 40-bit shift register and a 40-bit latch.
As the 40-bit shift register can be divided into two 20-bit sections, it can be used efficiently, based on the number of
segments and the character configuration.
Also, by using a number of BU9706KS drivers, it is possible to configure an LCD segment driver of more than 80
bits.
As the liquid crystal drive voltage can be set externally to any value, it can be used as a driver IC for both static and
dynamic drive in various types of liquid crystal display panels.
•1)Features
40-bit shift register and 40-bit latch enable serial
5) Can accommodates duty of 1 / 8 to 1 / 16.
6) Can be used as a driver IC for static drive by setting
the liquid crystal drive voltage externally (V3 = VDD,
V2 = V5 = VSS, connect DF as LCD common).
input - parallel output.
2) Shift register can be divided into two 20-bit sections.
3) Power supply voltage: 3.5 to 6V.
4) LCD drive voltage: 3 to 6V.
•Block diagram
O1
O2
O3
41
40
39
O38 O39 O40
4
3
2
VDD 49
LCD Dr
V2 43
V3 44
40
V5 45
DF 51
40 bit Latch
LOAD 47
20
DII 53
20
D
1
D
20 bit SHIFT REGISTER
CP 48
DO40
20-bit SHIFT REGISTER
CK
CK
VSS 42
54
55
DO20 DI21
1
Standard ICs
BU9706KS
•Absolute maximum ratings (Ta = 25°C, V
SS
Parameter
Symbol
Limits
Unit
VDD
– 0.3 ~ + 6.5
V
0 ~ + 6.5
V
Power supply voltage
LCD power supply voltage∗
= 0V)
VDD – V5
Input voltage
VIN
VSS – 0.3 ~ VDD + 0.3
V
Power dissipation
Pd
500
mW
Operating temperature
Topr
– 20 ~ + 70
°C
Storage temperature
Tstg
– 55 ~ + 125
°C
∗ The LCD power supply voltage must satisfy the condition of VDD > V2 ⭌ V3 > V5 ⭌ VSS.
•Recommended operating conditions (Ta = 25°C, V
SS
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
LCD power supply voltage∗
= 0V)
VDD
3.5
—
6.0
V
VDD – V5
3.0
—
6.0
V
VIN
0
—
VDD
V
Input voltage
O13
O12
O11
O9
O8
O7
O6
O5
O4
O3
O2
VSS
O1
•Pin assignments
O10
∗ The LCD power supply voltage must satisfy the condition of VDD > V2 ⭌ V3 > V5 ⭌ VSS.
42 41 40 39 38 37 36 35 34 33 32 31 30 29
V2
V3
V5
43
44
45
28
27
26
O14
O15
O16
N.C.
LOAD
CP
46
47
48
25
24
23
O17
O18
O19
VDD
N.C.
49
50
22
21
O20
O21
BU9706KS
O24
DO20
54
55
56
17
16
O25
O26
15
O27
2
O28
9 10 11 12 13 14
O29
7 8
O30
6
O31
4 5
O32
3
O34
2
O37
1
O38
DI21
N.C.
O33
O23
18
O35
O22
19
O36
20
52
53
O39
51
DO40
O40
DF
N.C.
DI1
Standard ICs
BU9706KS
•Pin descriptions
Pin No.
Pin name
I/O
Function
2 ~ 41
O40
~ O1
O
Output pin for the liquid crystal driver. VDD, V2, V3 or V5 is output depending on
the latch content and the DF signal. Refer to the truth table for the output level.
43 ~ 45
V2 ~ V5
—
Power supply pin for liquid crystal drive
49
VDD
—
Logic power supply pin and liquid crystal drive power supply pin
42
VSS
—
Logic power supply pin
53
DI1
I
Data input pin for the shift register (1 to 20 bits). Data is read to the first bit of
the shift register at the clock signal falling edge.
54
DO20
O
Data output pin for the shift register (1 to 20 bits). Data is output in
synchronization with the clock signal falling edge. A 40-bit shift register is
accomplished by connecting pins 54 and 55.
55
DI21
I
Data input pin for the shift register (21 to 40 bits). Data is read to the 21st bit
of the shift register at the clock signal falling edge.
1
DO40
O
Data output pin for the shift register (21 to 40 bits). Data is output in synchronization
with the clock signal falling edge. It is used to configure an LCD driver with more
than 40 bits by connecting it to the DI pin of the BU9706KS at the next stage.
48
CP
I
Clock signal input pin for the shift register. The contents of the shift register
are shifted by 1 bit only at the clock signal falling edge.
47
LOAD
I
Latch signal input pin for the 40-bit latch. The contents of the shift register are
transferred to O1 to O40 at LOAD = "H" and the data is latched at LOAD = "L". While
LOAD = "L", the latched data is held even if the contents of the shift register change.
51
DF
I
Input pin for the signal which produces AC for LCD drive.
•LCD drive output pin truth table
Latch data
DF
H
H
V5
H
L
VDD
L
H
V3
L
L
V2
•Timing chart
On terminal voltage
40
1
O1
O40
2
3
O39
O38
39
40
1
2
CP
DI1
O2
Load
O1
O40
O39
Load
LOAD
DF
• Shifted at CP input falling.
• When the LOAD input state becomes "H", the contents of the shift register are transferred to the segment
outputs O1 to O40, and when it is "L", the data is latched.
Fig.1
3
Standard ICs
BU9706KS
characteristics (unless otherwise noted, Ta = 25°C, V
•DCElectrical
characteristics
DD
Parameter
= 5 V)
Symbol
Min.
Typ.
Max.
Unit
Conditions
Input high level voltage∗1
VIH
4.0
—
—
V
—
Input low level voltage∗1
VIL
—
—
1.0
V
—
current∗1
IIH
Input high level
Input low level current∗1
Output high level
voltage∗2
—
—
1
µA
VIH = VDD
IIL
—
—
–1
µA
VIL = 0V
VOH
4.2
—
—
V
IO = – 40µA
0.4
V
5
kΩ
| VIN – VO |∗5 = 0.25V
0.5
mA
CP = DC No load
Output low level voltage∗2
VOL
—
—
ON resistance∗3∗4
RON
—
—
Current dissipation
IDD
—
—
∗1 Applied to DF, LOAD, CP, DI1 and DI21 pins
∗2 Applied to DO20 and DO40 pins
∗3 Applied to O1 to O40 pins
IO = 0.4mA
∗4 VDD = 5V, V2 = 2 / 3 VDD, V3 = 1 / 3 VDD, V5 = 0V
∗5 VIN = VDD, V2, V3, V5, Vo = O pin voltage
n
AC characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Propagation delay time 1
tpLH, tpHL
—
—
250
ns
CP → DOn delay time
Propagation delay time 2∗
tp (L)
—
—
250
ns
Load → On delay time
DF → On delay time
Propagation delay time 3∗
tp (D)
—
—
250
ns
DI → CP setup time
tsLH, tsHL
50
—
—
ns
—
CP → DI hold time
thLH, thHL
50
—
—
ns
—
CP pulse width
tw (CP)
125
—
—
ns
—
Load pulse width
tw (L)
125
—
—
ns
—
CP → load time
tCL
250
—
—
ns
—
LOAD → CP time
tLC
0
—
—
ns
—
Maximum clock frequency
fCP
3.3
—
—
MHz
∗ VDD = 5V, V2 = 2 / 3VDD, V3 = 1 / 3VDD, V5 = 0V
䊊 Not designed for radiation resistance.
4
Conditions
DUTY = 50%
Standard ICs
BU9706KS
tw (CP)
CP
tw (CP)
0.8VDD
0.8VDD 0.8VDD
0.2VDD 0.2VDD
tsLH
tsHL
thLH
thHL
0.8VDD
0.2VDD
DI1, DI21
tpLH
tpHL
0.8VDD
0.2VDD
DO20, DO40
tCL
tLC
0.8VDD 0.8VDD
LOAD
0.2VDD
tW (L)
∗
∗
O1 ~ O40
tp (L)
DF
0.8VDD
0.2VDD
tp (D)
tp (D)
∗
∗
O1 ~ O40
∗t
p (L)
∗
∗
and tp (D) are times required before the O1 to O40 output amplitude becomes 80% and 20% respectively.
Fig.2 AC characteristics waveform
•Application example
COM1
LCD panel (16 commons, 120 segments)
COM16
SEG1
O40
DO40
DI1
DO20
DI21
VDD
BU9706KS
CP
LOAD
DF
R
V3
V5
V2
V1
V2
V3
O1
V2
DO40
BU9706KS
CP
DI1
DO20
DI21
LOAD
D
Controller
O40
DF
O1
V3
V5
SEG40
R
R
R
V4
V5
M
CL1
R
CL2
Fig.3
5
Standard ICs
BU9706KS
•External dimensions (Units: mm)
12.4 ± 0.3
10.0 ± 0.2
56
15
2.15 ± 0.1
1
0.05
29
28
43
0.65
14
0.3 ± 0.1
SQFP56
6
0.5
12.4 ± 0.3
10.0 ± 0.2
42
0.15 ± 0.1
0.15
Similar pages